fix(qemu): exclude GPT reserve from BL32_MEM_SIZE

BL32_MEM_SIZE fails to take into account the space reserved for L0 and
L1 GPTs at the end of secure DRAM, when ENABLE_RME==1.

Fixes: cd75693f5ed3 (

fix(qemu): exclude GPT reserve from BL32_MEM_SIZE

BL32_MEM_SIZE fails to take into account the space reserved for L0 and
L1 GPTs at the end of secure DRAM, when ENABLE_RME==1.

Fixes: cd75693f5ed3 ("feat(qemu): setup memory map for RME")
Change-Id: If374b491d82be93c195cf501a9d12b9965d85182
Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>

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fix(qemu): fix L0 GPT page table mapping

Page table mappings are missing the bitlock pages introduced by commit
e9bcbd7b2ee4 ("fix(qemu): allocate space for GPT bitlock"). Add them to
the L0 mapping

fix(qemu): fix L0 GPT page table mapping

Page table mappings are missing the bitlock pages introduced by commit
e9bcbd7b2ee4 ("fix(qemu): allocate space for GPT bitlock"). Add them to
the L0 mapping.

Change-Id: I6b63b9c6ea4bf01ab1fac98723340272babe7bf8
Reported-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Fixes: e9bcbd7b2ee4 ("fix(qemu): allocate space for GPT bitlock")
Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>

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feat(versal): deprecate build time arg VERSAL_PLATFORM

Update Versal platform to enable runtime detection of variants instead
of relying on the build argument VERSAL_PLATFORM.
Integrate functionalit

feat(versal): deprecate build time arg VERSAL_PLATFORM

Update Versal platform to enable runtime detection of variants instead
of relying on the build argument VERSAL_PLATFORM.
Integrate functionality for identifying the board variant during
runtime, allowing dynamic adjustment of CPU and UART clock values
accordingly.
Print the runtime board information during boot.
This advancement streamlines the build process by eliminating
dependencies on variant-specific builds, enabling the use of a single
binary for multiple variants.
Removing all the platform related constants for versal_virt,SPP,EMU as
they are not used.

Change-Id: I8c1a1d391bd1a8971addc1f56f8309a3fb75aa6d
Signed-off-by: Amey Avinash Raghatate <AmeyAvinash.Raghatate@amd.com>
Signed-off-by: Maheedhar Bollapalli <MaheedharSai.Bollapalli@amd.com>

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Merge "feat(handoff): fix register convention r1/x1 value on transfer list" into integration

Merge "fix(xlat): correct attribute retrieval in a RME enabled system" into integration

Merge "feat(fgt2): add support for FEAT_FGT2" into integration

Merge changes from topic "us_dsu_pmu" into integration

* changes:
feat(tc): enable Last-level cache (LLC)
feat(cpus): add sysreg_bitfield_insert_from_gpr macro
feat(tc): add DSU PMU node for t

Merge changes from topic "us_dsu_pmu" into integration

* changes:
feat(tc): enable Last-level cache (LLC)
feat(cpus): add sysreg_bitfield_insert_from_gpr macro
feat(tc): add DSU PMU node for tc3
feat(tc): enable el1 access to DSU PMU registers
style(tc): remove comment for plat_reset_handler
fix(context-mgmt): keep actlr_el2 value in the init context

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feat(tc): enable Last-level cache (LLC)

The EXTLLC bit in CPUECTLR_EL1 register indicates that an external
Last-level cache is present in the system.

This bit is not set for CPUs on TC3 platform de

feat(tc): enable Last-level cache (LLC)

The EXTLLC bit in CPUECTLR_EL1 register indicates that an external
Last-level cache is present in the system.

This bit is not set for CPUs on TC3 platform despite there is
presence of LLC in MCN, so set them.

Change-Id: I5f889e67dce2b1d00e4ee66a8c255cf7911825b0
Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
Signed-off-by: Leo Yan <leo.yan@arm.com>

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Merge "fix(arm): check the presence of the policy check function" into integration

fix(zynqmp): handle secure SGI at EL1 for OP-TEE

OP-TEE requires SGIs to be handled at S-EL1. The
Makefile was not properly setting the flag
GICV2_G0_FOR_EL3 to 0 when the SPD is OP-TEE.

Change-Id:

fix(zynqmp): handle secure SGI at EL1 for OP-TEE

OP-TEE requires SGIs to be handled at S-EL1. The
Makefile was not properly setting the flag
GICV2_G0_FOR_EL3 to 0 when the SPD is OP-TEE.

Change-Id: I256afa37ddf4ad4a154c43d51807de670c3689bb
Signed-off-by: Shen Jiamin <shen_jiamin@comp.nus.edu.sg>

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feat(spm): change UART0-1 to NS device region

To enable device memory sharing test make memory region for UART0
and 1 a NS device region so that it can be shared by tf-a-tests
to the cactus SP.

Sig

feat(spm): change UART0-1 to NS device region

To enable device memory sharing test make memory region for UART0
and 1 a NS device region so that it can be shared by tf-a-tests
to the cactus SP.

Signed-off-by: Daniel Boulby <daniel.boulby@arm.com>
Change-Id: Iadfe02a65f5d4a8b60296f07c4943dd31f201453

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Merge changes I7e2a543a,I932cae6d,I623707c3 into integration

* changes:
build(deps): bump braces
build(deps): bump the pip group across 1 directory with 2 updates
build(deps): bump the pip gro

Merge changes I7e2a543a,I932cae6d,I623707c3 into integration

* changes:
build(deps): bump braces
build(deps): bump the pip group across 1 directory with 2 updates
build(deps): bump the pip group across 1 directory with 7 updates

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feat(cpus): add sysreg_bitfield_insert_from_gpr macro

A macro 'sysreg_bitfield_insert_from_gpr' is introduced for inserting
bitfield from a general register.

Change-Id: I7288a13d70d98e23dc7a93287b0

feat(cpus): add sysreg_bitfield_insert_from_gpr macro

A macro 'sysreg_bitfield_insert_from_gpr' is introduced for inserting
bitfield from a general register.

Change-Id: I7288a13d70d98e23dc7a93287b04b493ffce9171
Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
Signed-off-by: Leo Yan <leo.yan@arm.com>

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feat(tc): add DSU PMU node for tc3

Add DT binding for Arm DSU PMU node.

Change-Id: Iadfb5d3bb3f69c7a771516180d1c165e60eef51d
Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
Signed-off-by: Le

feat(tc): add DSU PMU node for tc3

Add DT binding for Arm DSU PMU node.

Change-Id: Iadfb5d3bb3f69c7a771516180d1c165e60eef51d
Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
Signed-off-by: Leo Yan <leo.yan@arm.com>

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feat(tc): enable el1 access to DSU PMU registers

DSU PMU registers are write accessible in EL1 if the ACTLR_EL3[12] bit
and the ACTLR_EL2[12] bit are set to 1, and these registers are need to
be set

feat(tc): enable el1 access to DSU PMU registers

DSU PMU registers are write accessible in EL1 if the ACTLR_EL3[12] bit
and the ACTLR_EL2[12] bit are set to 1, and these registers are need to
be set for all cores, so set these bits in platform reset handler.

Change-Id: I1db6915939727f0909c05c8b103e37984aadb443
Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
Signed-off-by: Leo Yan <leo.yan@arm.com>

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style(tc): remove comment for plat_reset_handler

The comment for plat_reset_handler doesn't make sense. It is likely a
copy-and-paste error while adding the code, so remove it.

Change-Id: Iab8c8c79

style(tc): remove comment for plat_reset_handler

The comment for plat_reset_handler doesn't make sense. It is likely a
copy-and-paste error while adding the code, so remove it.

Change-Id: Iab8c8c799c184fa99966770d47ecb11bbc640515
Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>

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fix(context-mgmt): keep actlr_el2 value in the init context

The system register actlr_el2 can be set during CPU or platform reset
handler. E.g. on Arm Total Compute platform, the CLUSTERPMUEN bit of

fix(context-mgmt): keep actlr_el2 value in the init context

The system register actlr_el2 can be set during CPU or platform reset
handler. E.g. on Arm Total Compute platform, the CLUSTERPMUEN bit of
actlr_el2 is set in the platform reset handler to enable the write
access to DSU PMU registers from EL1. However, as EL2 context gets
restored without saving it beforehand during jump to SPM and next NS
image, therefore, the initialized value of actlr_el2 is not retained.

To fix this issue, keep track of actlr_el2 value during the EL2 context
initialization. This applies for both secure and non-secure security
state.

Change-Id: I1bd7b984216c042c056ad20c6724bedce5a6a3e2
Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
Signed-off-by: Leo Yan <leo.yan@arm.com>

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Merge "fix(corstone1000): include platform header file" into integration

fix(corstone1000): include platform header file

Include platform.h file in order to remove following compiler errors,
as some warnings are being treated as errors now.
error: implicit declaration of

fix(corstone1000): include platform header file

Include platform.h file in order to remove following compiler errors,
as some warnings are being treated as errors now.
error: implicit declaration of function
'plat_core_pos_by_mpidr'[-Wimplicit-function-declaration]

Change-Id: Ie223e11e138ec9b0eef7342f450b90b215a49b15
Signed-off-by: Harsimran Singh Tungal <harsimransingh.tungal@arm.com>

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Merge "feat(debugv8p9): add support for FEAT_Debugv8p9" into integration

feat(handoff): fix register convention r1/x1 value on transfer list

According to recently firmware handsoff spec [1]'s "Register usage at handoff
boundary", Transfer List's signature value was chang

feat(handoff): fix register convention r1/x1 value on transfer list

According to recently firmware handsoff spec [1]'s "Register usage at handoff
boundary", Transfer List's signature value was changed from 0x40_b10b
(3 bytes) to 4a0f_b10b (4 bytes).

As updating of TL's signature, register value of x1/r1 should be:

In aarch32's r1 value should be
R1[23:0]: set to the TL signature (4a0f_b10b -> masked range value: 0f_b10b)
R1[31:24]: version of the register convention == 1
and
In aarch64's x1 value should be
X1[31:0]: set to the TL signature (4a0f_b10b)
X1[39:32]: version of the register convention == 1
X1[63:40]: MBZ
(See the [2] and [3]).

Therefore, it requires to separate mask and shift value for register
convention version field when sets each r1/x1.

This patch fix two problems:
1. breaking X1 value with updated specification in aarch64
- change of length of signature field.

2. previous error value set in R1 in arm32.
- length of signature should be 24, but it uses 32bit signature.

This change is breaking change. It requires some patch for other
softwares (u-boot[4], optee[5]).

Link: https://github.com/FirmwareHandoff/firmware_handoff [1]
Link: https://github.com/FirmwareHandoff/firmware_handoff/issues/32 [2]
Link: https://github.com/FirmwareHandoff/firmware_handoff/commit/5aa7aa1d3a1db75213e458d392b751f0707de027 [3]
Link: https://lists.denx.de/pipermail/u-boot/2024-July/558628.html [4]
Link: https://github.com/OP-TEE/optee_os/pull/6933 [5]
Signed-off-by: Levi Yun <yeoreum.yun@arm.com>
Change-Id: Ie417e054a7a4c192024a2679419e99efeded1705

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fix(xlat): correct attribute retrieval in a RME enabled system

In a system enabled with RME, the function
'xlat_get_mem_attributes_internal' fails to accurately provide
'output PA space' for Realm a

fix(xlat): correct attribute retrieval in a RME enabled system

In a system enabled with RME, the function
'xlat_get_mem_attributes_internal' fails to accurately provide
'output PA space' for Realm and Root memory because it does not
consider the 'nse' bit in page table descriptor.
This patch resolves the issue by extracting the 'nse' bit value.
As a result, it ensures correct retrieval of attributes
in RME-enabled systems while maintaining unaffected attribute
retrieval for non-RME systems.

Change-Id: If2d01545b921c9074f48c52a98027ff331e14237
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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build(deps): bump braces

Bumps the npm_and_yarn group with 1 update in the / directory: [braces](https://github.com/micromatch/braces).

Updates `braces` from 3.0.2 to 3.0.3
- [Changelog](https://gi

build(deps): bump braces

Bumps the npm_and_yarn group with 1 update in the / directory: [braces](https://github.com/micromatch/braces).

Updates `braces` from 3.0.2 to 3.0.3
- [Changelog](https://github.com/micromatch/braces/blob/master/CHANGELOG.md)
- [Commits](https://github.com/micromatch/braces/compare/3.0.2...3.0.3)

---
updated-dependencies:
- dependency-name: braces
dependency-type: indirect
dependency-group: npm_and_yarn
...

Change-Id: I7e2a543a3bc67d426a69fc25f93b878c9b5a3b11
Signed-off-by: dependabot[bot] <support@github.com>
Signed-off-by: Chris Kay <chris.kay@arm.com>

show more ...

build(deps): bump the pip group across 1 directory with 2 updates

Bumps the pip group with 2 updates in the / directory: [setuptools](https://github.com/pypa/setuptools) and [zipp](https://github.co

build(deps): bump the pip group across 1 directory with 2 updates

Bumps the pip group with 2 updates in the / directory: [setuptools](https://github.com/pypa/setuptools) and [zipp](https://github.com/jaraco/zipp).

Updates `setuptools` from 67.7.2 to 70.0.0
- [Release notes](https://github.com/pypa/setuptools/releases)
- [Changelog](https://github.com/pypa/setuptools/blob/main/NEWS.rst)
- [Commits](https://github.com/pypa/setuptools/compare/v67.7.2...v70.0.0)

Updates `zipp` from 3.15.0 to 3.19.1
- [Release notes](https://github.com/jaraco/zipp/releases)
- [Changelog](https://github.com/jaraco/zipp/blob/main/NEWS.rst)
- [Commits](https://github.com/jaraco/zipp/compare/v3.15.0...v3.19.1)

---
updated-dependencies:
- dependency-name: setuptools
dependency-type: indirect
dependency-group: pip
- dependency-name: zipp
dependency-type: indirect
dependency-group: pip
...

Change-Id: I932cae6df880f35884043d4a78d10f57e32c80fc
Signed-off-by: dependabot[bot] <support@github.com>
Signed-off-by: Chris Kay <chris.kay@arm.com>

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build(deps): bump the pip group across 1 directory with 7 updates

Bumps the pip group with 7 updates in the / directory:

| Package | From | To |
| --- | --- | --- |
| [certifi](https://github.com/c

build(deps): bump the pip group across 1 directory with 7 updates

Bumps the pip group with 7 updates in the / directory:

| Package | From | To |
| --- | --- | --- |
| [certifi](https://github.com/certifi/python-certifi) | `2023.7.22` | `2024.7.4` |
| [idna](https://github.com/kjd/idna) | `3.4` | `3.7` |
| [jinja2](https://github.com/pallets/jinja) | `3.1.2` | `3.1.4` |
| [pip](https://github.com/pypa/pip) | `23.1.2` | `23.3` |
| [requests](https://github.com/psf/requests) | `2.31.0` | `2.32.2` |
| [urllib3](https://github.com/urllib3/urllib3) | `2.0.2` | `2.2.2` |
| [zipp](https://github.com/jaraco/zipp) | `3.15.0` | `3.19.1` |

Updates `certifi` from 2023.7.22 to 2024.7.4
- [Commits](https://github.com/certifi/python-certifi/compare/2023.07.22...2024.07.04)

Updates `idna` from 3.4 to 3.7
- [Release notes](https://github.com/kjd/idna/releases)
- [Changelog](https://github.com/kjd/idna/blob/master/HISTORY.rst)
- [Commits](https://github.com/kjd/idna/compare/v3.4...v3.7)

Updates `jinja2` from 3.1.2 to 3.1.4
- [Release notes](https://github.com/pallets/jinja/releases)
- [Changelog](https://github.com/pallets/jinja/blob/main/CHANGES.rst)
- [Commits](https://github.com/pallets/jinja/compare/3.1.2...3.1.4)

Updates `pip` from 23.1.2 to 23.3
- [Changelog](https://github.com/pypa/pip/blob/main/NEWS.rst)
- [Commits](https://github.com/pypa/pip/compare/23.1.2...23.3)

Updates `requests` from 2.31.0 to 2.32.2
- [Release notes](https://github.com/psf/requests/releases)
- [Changelog](https://github.com/psf/requests/blob/main/HISTORY.md)
- [Commits](https://github.com/psf/requests/compare/v2.31.0...v2.32.2)

Updates `urllib3` from 2.0.2 to 2.2.2
- [Release notes](https://github.com/urllib3/urllib3/releases)
- [Changelog](https://github.com/urllib3/urllib3/blob/main/CHANGES.rst)
- [Commits](https://github.com/urllib3/urllib3/compare/2.0.2...2.2.2)

Updates `zipp` from 3.15.0 to 3.19.1
- [Release notes](https://github.com/jaraco/zipp/releases)
- [Changelog](https://github.com/jaraco/zipp/blob/main/NEWS.rst)
- [Commits](https://github.com/jaraco/zipp/compare/v3.15.0...v3.19.1)

---
updated-dependencies:
- dependency-name: certifi
dependency-type: indirect
dependency-group: pip
- dependency-name: idna
dependency-type: indirect
dependency-group: pip
- dependency-name: jinja2
dependency-type: indirect
dependency-group: pip
- dependency-name: pip
dependency-type: indirect
dependency-group: pip
- dependency-name: requests
dependency-type: indirect
dependency-group: pip
- dependency-name: urllib3
dependency-type: indirect
dependency-group: pip
- dependency-name: zipp
dependency-type: indirect
dependency-group: pip
...

Change-Id: I623707c3eb76598c4bfb3957f090a846c765b1f2
Signed-off-by: dependabot[bot] <support@github.com>
Signed-off-by: Chris Kay <chris.kay@arm.com>

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