Fix compilation warning in Trusty SPD

In release builds, the Trusty SPD fails to build because of an unused
variable. Note that this warning message doesn't show in debug builds
because INFO() messa

Fix compilation warning in Trusty SPD

In release builds, the Trusty SPD fails to build because of an unused
variable. Note that this warning message doesn't show in debug builds
because INFO() messages are not compiled out like in release mode.

This patch fixes this issue by removing this variable and using its
value in place directly in the INFO() macro call.

Change-Id: I1f552421181a09412315eef4eaca586012022018
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>

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Merge pull request #762 from douglas-raillard-arm/dr/doc_build_info

Clarify dependency for PSCI_EXTENDED_STATE_ID

Merge pull request #760 from Xilinx/zynqmp-2016-11

ZynqMP Updates

Merge pull request #755 from vwadekar/trusty-spd

spd: dispatcher for interacting with the Trusty TEE

Clarify dependency for PSCI_EXTENDED_STATE_ID

Add dependency information in the user guide for ARM_RECOM_STATE_ID_ENC
that needs to be set when using PSCI_EXTENDED_STATE_ID on ARM
platforms. Also cl

Clarify dependency for PSCI_EXTENDED_STATE_ID

Add dependency information in the user guide for ARM_RECOM_STATE_ID_ENC
that needs to be set when using PSCI_EXTENDED_STATE_ID on ARM
platforms. Also clarify the build error message.

Change-Id: Id125a0299b179f5f222bca4e2503204bf89a3c59
Signed-off-by: Douglas Raillard <douglas.raillard@arm.com>

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Fix normal memory bakery lock implementation

This patch fixes an issue in the normal memory bakery lock
implementation. During assertion of lock status, there is a possibility
that the assertion cou

Fix normal memory bakery lock implementation

This patch fixes an issue in the normal memory bakery lock
implementation. During assertion of lock status, there is a possibility
that the assertion could fail. This is because the previous update done
to the lock status by the owning CPU when not participating in cache
coherency could result in stale data in the cache due to cache maintenance
operations not propagating to all the caches. This patch fixes this issue
by doing an extra read cache maintenance operation prior to the assertion.

Fixes ARM-software/tf-issues#402

Change-Id: I0f38a7c52476a4f58e17ebe0141d256d198be88d
Signed-off-by: Soby Mathew <soby.mathew@arm.com>

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Add CFI debug frame information for ASM functions

This allows the debugger to print the callstack when there is an
assembly function in the callstack.

It will work as long as the CFA pointer (frame

Add CFI debug frame information for ASM functions

This allows the debugger to print the callstack when there is an
assembly function in the callstack.

It will work as long as the CFA pointer (frame pointer) location is not
modified (i.e. x29 is not touched in AArch64 state). It is the case in
almost all assembly functions, so this patch improves the average
debugging experience. Call stacks from the debugger should still be
interpreted with care. In more complex functions, one could use .cfi*
directives to inform the debugger about the new location of the CFA
pointer.

Change-Id: I9dabfbc033b45e8528e67f4823c17de7bf02fa24
Signed-off-by: Douglas Raillard <douglas.raillard@arm.com>

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Merge pull request #759 from douglas-raillard-arm/dr/cosmetic_vectors_tables

Cosmetic change to exception table

Merge pull request #758 from douglas-raillard-arm/dr/doc_interrupt_handler

Docs: Clarify IRQ/FIQ handler API in Interrupt Design Guide

Docs: Clarify IRQ/FIQ handler API in Interrupt Design Guide

The API description currently states that interrupt handlers
(interrupt_type_handler_t pointers) SHOULD return a pointer
to the target cpu

Docs: Clarify IRQ/FIQ handler API in Interrupt Design Guide

The API description currently states that interrupt handlers
(interrupt_type_handler_t pointers) SHOULD return a pointer
to the target cpu_context.

This patch rewords the description of the interrupts handlers to state
that it MUST return a pointer to the target security context. It also
warns about potential portability issue. Specifically, this pointer is
not used on AArch64 and calls to context library APIs must be used to
ask BL31 to return to a specific context. However, this could change in
the future and interrupt handlers must always return the pointer.

Change-Id: I3f82a046de4d7a5b51a8cbebe7eb2a00dbbdb4f0
Signed-off-by: Douglas Raillard <douglas.raillard@arm.com>

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zynqmp: pm: Add SiP call to obtain PM callback data

The callback IRQ is delivered to the NS OS. Provide an interface to
allow the NS OS to obtain the callback data from the secure HW.

Signed-off-by

zynqmp: pm: Add SiP call to obtain PM callback data

The callback IRQ is delivered to the NS OS. Provide an interface to
allow the NS OS to obtain the callback data from the secure HW.

Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>

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zynqmp: pm: Enable IPI IRQ when API version is probed

The IPI hardware is secure and managed by ATF, nevertheless we deliver
the IRQ to the rich OS. The IRQ is needed to receive PM callbacks.
Enable

zynqmp: pm: Enable IPI IRQ when API version is probed

The IPI hardware is secure and managed by ATF, nevertheless we deliver
the IRQ to the rich OS. The IRQ is needed to receive PM callbacks.
Enable the IPI interrupt when the rich OS probes the API version.

Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>

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zynqmp: Remove dead code

Remove dead code pieces and stale comments.

Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>

zynqmp: Fix UART1 base address

Cc: Michal Simek <michal.simek@xilinx.com>
Reported-by: Jonas Karlsson <jonas.karlsson@atero.se>
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Acked-by:

zynqmp: Fix UART1 base address

Cc: Michal Simek <michal.simek@xilinx.com>
Reported-by: Jonas Karlsson <jonas.karlsson@atero.se>
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Acked-by: Michal Simek <michal.simek@xilinx.com>

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zynqmp: PM: Migrate to new shutdown interface

Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>

zynqmp: pm: Plumb get_chipid through FW interface

Use the PMUFW get_chipid call to obtain IDCODE and version register.

Cc: Michal Simek <michal.simek@xilinx.com>
Cc: Siva Durga Prasad Paladugu <siv

zynqmp: pm: Plumb get_chipid through FW interface

Use the PMUFW get_chipid call to obtain IDCODE and version register.

Cc: Michal Simek <michal.simek@xilinx.com>
Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>

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zynqmp: pm: Allow obtaining additional return values from FW

Allow reading more than just a single value from the message buffer.

Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>

zynqmp: Do not alter system counter

On ZynqMP the FSBL will configure the system counter. Hence, remove the
initialization of the system counter with hardcoded values from the ATF
and use the setup

zynqmp: Do not alter system counter

On ZynqMP the FSBL will configure the system counter. Hence, remove the
initialization of the system counter with hardcoded values from the ATF
and use the setup provided by the bootloader.

Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Acked-by: Michal Simek <michal.simek@xilinx.com>

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zynqmp: Read silicon ID register only once

The silicon ID does not change at runtime. Skip the IO access if the
ID has been read before.

Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>

zynqmp: Read silicon ID register only once

The silicon ID does not change at runtime. Skip the IO access if the
ID has been read before.

Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Acked-by: Michal Simek <michal.simek@xilinx.com>

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Merge pull request #757 from douglas-raillard-arm/dr/doc_plat_psci_ops

Document plat_psci_ops.(system_off|system_reset)

Merge pull request #756 from douglas-raillard-arm/dr/doc_fix_link_fw_design

firmware-design.md: Fix broken link

Merge pull request #754 from davidcunado-arm/dc/reset_debug_reg

Reset debug registers MDCR-EL3/SDCR and MDCR_EL2/HDCR

Cosmetic change to exception table

* Move comments on unhandled exceptions at the right place.
* Reformat the existing comments to highlight the start of
each block of 4 entries in the exception t

Cosmetic change to exception table

* Move comments on unhandled exceptions at the right place.
* Reformat the existing comments to highlight the start of
each block of 4 entries in the exception table to ease
navigation (lines of dash reserved for head comments).
* Reflow comments to 80 columns.

Change-Id: I5ab88a93d0628af8e151852cb5b597eb34437677
Signed-off-by: Douglas Raillard <douglas.raillard@arm.com>

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firmware-design.md: Fix broken link

Fix a link broken by a missing space that turned
it into a link to an non-existent anchor.

Change-Id: Ie863e963db28afa3a28b69d3f63bd7638bdf5af9
Signed-off-by: Do

firmware-design.md: Fix broken link

Fix a link broken by a missing space that turned
it into a link to an non-existent anchor.

Change-Id: Ie863e963db28afa3a28b69d3f63bd7638bdf5af9
Signed-off-by: Douglas Raillard <douglas.raillard@arm.com>

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Document plat_psci_ops.(system_off|system_reset)

fixes ARM-Software/tf-issues#346

Change-Id: I946c8eab650bba7407775462ce91f394d767e079
Signed-off-by: Douglas Raillard <douglas.raillard@arm.com>