Merge pull request #1676 from Yann-lms/static_analysis

Correct some issues found with static analysis tools

Merge pull request #1677 from acolinisi/PR--drivers-cadence-uart-prototype

cadence: uart: comply to console_register prototype

cadence: uart: comply to console_register prototype

Signed-off-by: Alexei Colin <acolin@isi.edu>

Merge pull request #1674 from jforissier/hisi-multi-console

hikey, hikey960, poplar: use new console APIs

Merge pull request #1605 from sivadur/integration

Add support new Xilinx Versal ACAP platform

stm32mp1: remove duplicate function declaration

It is already in include/drivers/st/stm32mp1_ddr_helpers.h.

Signed-off-by: Yann Gautier <yann.gautier@st.com>

stm32mp1: correct some static analysis tools issues

These issues wer found by sparse:

drivers/st/clk/stm32mp1_clk.c:1524:19:
warning: incorrect type in assignment (different base types)
expect

stm32mp1: correct some static analysis tools issues

These issues wer found by sparse:

drivers/st/clk/stm32mp1_clk.c:1524:19:
warning: incorrect type in assignment (different base types)
expected restricted fdt32_t const [usertype] *pkcs_cell
got unsigned int const [usertype] *

plat/st/stm32mp1/plat_image_load.c:13:6:
warning: symbol 'plat_flush_next_bl_params' was not declared.
Should it be static?
plat/st/stm32mp1/plat_image_load.c:21:16:
warning: symbol 'plat_get_bl_image_load_info' was not declared.
Should it be static?
plat/st/stm32mp1/plat_image_load.c:29:13:
warning: symbol 'plat_get_next_bl_params' was not declared.
Should it be static?

plat/st/stm32mp1/bl2_io_storage.c:40:10:
warning: symbol 'block_buffer' was not declared. Should it be static?

Signed-off-by: Yann Gautier <yann.gautier@st.com>

show more ...

drivers: partition: correct some static analysis tools issues

cppcheck:
[drivers/partition/gpt.c:19] -> [drivers/partition/gpt.c:19]:
(warning) Either the condition 'str_in!=((void*)0)' is redundan

drivers: partition: correct some static analysis tools issues

cppcheck:
[drivers/partition/gpt.c:19] -> [drivers/partition/gpt.c:19]:
(warning) Either the condition 'str_in!=((void*)0)' is redundant
or there is possible null pointer dereference: name.

sparse:
drivers/partition/gpt.c:39:9:
warning: Using plain integer as NULL pointer

Signed-off-by: Yann Gautier <yann.gautier@st.com>

show more ...

psci: put __dead2 attribute after void in plat_psci_ops

These warnings were issued by sparse:
plat/st/stm32mp1/stm32mp1_pm.c:365:36:
warning: incorrect type in initializer (different modifiers)

psci: put __dead2 attribute after void in plat_psci_ops

These warnings were issued by sparse:
plat/st/stm32mp1/stm32mp1_pm.c:365:36:
warning: incorrect type in initializer (different modifiers)
expected void ( *[noreturn] pwr_domain_pwr_down_wfi )( ... )
got void ( [noreturn] *<noident> )( ... )
plat/st/stm32mp1/stm32mp1_pm.c:366:23:
warning: incorrect type in initializer (different modifiers)
expected void ( *[noreturn] system_off )( ... )
got void ( [noreturn] *<noident> )( ... )
plat/st/stm32mp1/stm32mp1_pm.c:367:25:
warning: incorrect type in initializer (different modifiers)
expected void ( *[noreturn] system_reset )( ... )
got void ( [noreturn] *<noident> )( ... )

This cannot be changed the other way in all platforms pm drivers
or else there is a compilation error:
plat/st/stm32mp1/stm32mp1_pm.c:234:1: error: attributes should be specified
before the declarator in a function definition

Signed-off-by: Yann Gautier <yann.gautier@st.com>

show more ...

arm64: versal: Add support for new Xilinx Versal ACAPs

Xilinx is introducing Versal, an adaptive compute acceleration platform
(ACAP), built on 7nm FinFET process technology. Versal ACAPs combine Sc

arm64: versal: Add support for new Xilinx Versal ACAPs

Xilinx is introducing Versal, an adaptive compute acceleration platform
(ACAP), built on 7nm FinFET process technology. Versal ACAPs combine Scalar
Processing Engines, Adaptable Hardware Engines, and Intelligent Engines with
leading-edge memory and interfacing technologies to deliver powerful
heterogeneous acceleration for any application. The Versal AI Core series has
five devices, offering 128 to 400 AI Engines. The series includes dual-core Arm
Cortex-A72 application processors, dual-core Arm Cortex-R5 real-time
processors, 256KB of on-chip memory with ECC, more than 1,900 DSP engines
optimized for high-precision floating point with low latency.

This patch adds Virtual QEMU platform support for
this SoC "versal_virt".

Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

show more ...

poplar: Use new console APIs

Switch to the new console APIs enabled by setting MULTI_CONSOLE_API=1.
Enables building with ERROR_DEPRECATED=1.

Signed-off-by: Jerome Forissier <jerome.forissier@linar

poplar: Use new console APIs

Switch to the new console APIs enabled by setting MULTI_CONSOLE_API=1.
Enables building with ERROR_DEPRECATED=1.

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>

show more ...

hikey960: Use new console APIs

Switch to the new console APIs enabled by setting MULTI_CONSOLE_API=1.
Enables building with ERROR_DEPRECATED=1.

Signed-off-by: Jerome Forissier <jerome.forissier@lin

hikey960: Use new console APIs

Switch to the new console APIs enabled by setting MULTI_CONSOLE_API=1.
Enables building with ERROR_DEPRECATED=1.

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>

show more ...

hikey: Use new console APIs

Switch to the new console APIs enabled by setting MULTI_CONSOLE_API=1.
Enables building with ERROR_DEPRECATED=1.

Signed-off-by: Jerome Forissier <jerome.forissier@linaro

hikey: Use new console APIs

Switch to the new console APIs enabled by setting MULTI_CONSOLE_API=1.
Enables building with ERROR_DEPRECATED=1.

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>

show more ...

Merge pull request #1673 from antonio-nino-diaz-arm/an/headers

Standardise header guards across codebase

Standardise header guards across codebase

All identifiers, regardless of use, that start with two underscores are
reserved. This means they can't be used in header guards.

The style that this proje

Standardise header guards across codebase

All identifiers, regardless of use, that start with two underscores are
reserved. This means they can't be used in header guards.

The style that this project is now to use the full name of the file in
capital letters followed by 'H'. For example, for a file called
"uart_example.h", the header guard is UART_EXAMPLE_H.

The exceptions are files that are imported from other projects:

- CryptoCell driver
- dt-bindings folders
- zlib headers

Change-Id: I50561bf6c88b491ec440d0c8385c74650f3c106e
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

show more ...

Merge pull request #1672 from sandrine-bailleux-arm/sb/fix-dram-constants

Arm platforms: Fix DRAM address macros

Merge pull request #1668 from ldts/rcar_gen3/e3_build

rcar_gen3: E3 target: fix compilation issues

Merge pull request #1670 from antonio-nino-diaz-arm/an/misra-arm

plat/arm: Fix MISRA defects in common code

Merge pull request #1669 from sandrine-bailleux-arm/sb/rm-tzc-top-fn

Remove unneeded _tzc_get_max_top_addr() function

Merge pull request #1666 from pmanish87/mp2/manish_local

plat/arm: Support direct Linux kernel boot in AArch32

Arm platforms: Fix DRAM address macros

On AArch32, ARM_DRAM1_BASE and ARM_DRAM1_SIZE constants are currently
32-bit values (because they are suffixed with UL and the value
0x80000000 fits in a unsig

Arm platforms: Fix DRAM address macros

On AArch32, ARM_DRAM1_BASE and ARM_DRAM1_SIZE constants are currently
32-bit values (because they are suffixed with UL and the value
0x80000000 fits in a unsigned long int, i.e. a 32-bit value). When
summing them up, the result overflows the maximum value that can be
encoded in a 32-bit value so it wraps around and does not result in
the expected value.

This patch changes the suffix of these constants into ULL so that they
always are 64-bit values.

Change-Id: I3b19b1805e35cc7e43050458df379081b1e882d5
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>

show more ...

Remove _tzc_get_max_top_addr() function

This function was needed at the time where we didn't have the
compiler_rt lib. An AArch32-specific variant was provided to handle
the 64-bit shift operation i

Remove _tzc_get_max_top_addr() function

This function was needed at the time where we didn't have the
compiler_rt lib. An AArch32-specific variant was provided to handle
the 64-bit shift operation in 32-bit. This is no longer needed.

Change-Id: Ibab709a95e3a723ae2eeaddf873dba70ff2012b3
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>

show more ...

compiler_rt: Import lshrdi3.c file

Imported from the LLVM compiler_rt library on master branch as of
30 Oct 2018 (SVN revision: r345645).

This is to get the __aeabi_llsr() builtin, which is require

compiler_rt: Import lshrdi3.c file

Imported from the LLVM compiler_rt library on master branch as of
30 Oct 2018 (SVN revision: r345645).

This is to get the __aeabi_llsr() builtin, which is required by a
subsequent patch that uses a logical right shift operator in AArch32.

Change-Id: I9884139a12855a8a87206fb572aaa7dd35582b09
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>

show more ...

compiler_rt: Import latest changes on int_lib.h

Imported from the LLVM compiler_rt library on master branch as of
30 Oct 2018 (SVN revision: r345645).

Change-Id: I058cfb5894daf1d12e1ef971c0ba36b0aa

compiler_rt: Import latest changes on int_lib.h

Imported from the LLVM compiler_rt library on master branch as of
30 Oct 2018 (SVN revision: r345645).

Change-Id: I058cfb5894daf1d12e1ef971c0ba36b0aa089be5
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>

show more ...

plat/arm: Fix MISRA defects in common code

Change-Id: I2419416fadfcdf64da8b7690a348007591c4edf3
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>