feat(mt8189): add pmic driver

1. add pmic shutdown/reset function
2. add pmic low power setting api

Signed-off-by: Zhigang Qin <zhigang.qin@mediatek.corp-partner.google.com>
Change-Id: Ie23e8ae50a6

feat(mt8189): add pmic driver

1. add pmic shutdown/reset function
2. add pmic low power setting api

Signed-off-by: Zhigang Qin <zhigang.qin@mediatek.corp-partner.google.com>
Change-Id: Ie23e8ae50a67be07f9025d69335c26b9569b3d70

show more ...

feat(mt8189): add PWRAP driver

Add PWRAP driver for mt6365 pmic communication

Signed-off-by: Zhigang Qin <zhigang.qin@mediatek.corp-partner.google.com>
Change-Id: I4d142cb020f0e1b0372f7ef2ba1eb0328

feat(mt8189): add PWRAP driver

Add PWRAP driver for mt6365 pmic communication

Signed-off-by: Zhigang Qin <zhigang.qin@mediatek.corp-partner.google.com>
Change-Id: I4d142cb020f0e1b0372f7ef2ba1eb03287cbcd8f

show more ...

feat(mt8189): add SPMI driver

Add SPMI driver for PMIC communication

Signed-off-by: Zhigang Qin <zhigang.qin@mediatek.corp-partner.google.com>
Change-Id: I528a111791798cc442dbd43e56eddfe91735be2e

Merge changes I54d18f01,I4e06c8a7,Ib5fc7dcd,Id5db5558,Ib941a04a into integration

* changes:
feat(st): adapt .stm32 file creation for clang
feat(st): adapt stm32 linker scripts for clang
feat(s

Merge changes I54d18f01,I4e06c8a7,Ib5fc7dcd,Id5db5558,Ib941a04a into integration

* changes:
feat(st): adapt .stm32 file creation for clang
feat(st): adapt stm32 linker scripts for clang
feat(st): update stm32 linker scripts
fix(st): mark INCBIN-generated sections as SHF_ALLOC
feat(st): remove unsupported option for clang

show more ...

Merge "fix(build): remove SUPPORT_STACK_MEMTAG" into integration

fix(build): remove SUPPORT_STACK_MEMTAG

This flag enables the memtag sanitizer in clang. However, for this to
work, other generic and platform-specific logic is required that was
never implemented.

fix(build): remove SUPPORT_STACK_MEMTAG

This flag enables the memtag sanitizer in clang. However, for this to
work, other generic and platform-specific logic is required that was
never implemented. So in effect, the feature is half-baked and at best a
simple test (of which we have plenty in tftf) or a NOP at worst.

So remove the option to simplify code a little.

Change-Id: Iab4150871c89545d813c5ae14be67bf6459d051a
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

show more ...

Merge "fix(libc): add the memcpy declaration back" into integration

fix(libc): add the memcpy declaration back

Patch 34d7f196b moved definitions to a new file but missed that of
memcpy. Put it back.

Change-Id: I5e9797e611e6f1f97232f03de98f81db86a66c2a
Signed-off-by

fix(libc): add the memcpy declaration back

Patch 34d7f196b moved definitions to a new file but missed that of
memcpy. Put it back.

Change-Id: I5e9797e611e6f1f97232f03de98f81db86a66c2a
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

show more ...

Merge "build(poetry): wrap docs build in poetry" into integration

fix(cpus): workaround for Cortex-A710 erratum 1917258

Cortex-A710 erratum 1917258 is a Cat B erratum that applies
to revisions r0p0 and r1p0 and is fixed in r2p0.

The workaround is to set CPUACTLR4

fix(cpus): workaround for Cortex-A710 erratum 1917258

Cortex-A710 erratum 1917258 is a Cat B erratum that applies
to revisions r0p0 and r1p0 and is fixed in r2p0.

The workaround is to set CPUACTLR4_EL1[43]. This has no
performance impact.

SDEN documentation:
https://developer.arm.com/documentation/SDEN1775101

Change-Id: I1fae91a5e3a8ecea255f0f0a481bfd6196a7db51
Signed-off-by: John Powell <john.powell@arm.com>

show more ...

fix(cpus): workaround for Cortex-A710 erratum 1916945

Cortex-A710 erratum 1916945 is a Cat B erratum that applies
to revisions r0p0 and r1p0 and is fixed in r2p0.

The workaround is to set CPUECTLR_

fix(cpus): workaround for Cortex-A710 erratum 1916945

Cortex-A710 erratum 1916945 is a Cat B erratum that applies
to revisions r0p0 and r1p0 and is fixed in r2p0.

The workaround is to set CPUECTLR_EL1[8]. This has a slight
performance impact.

SDEN documentation:
https://developer.arm.com/documentation/SDEN1775101

Change-Id: I54793492c527928d7f266165a31b8613de838e69
Signed-off-by: John Powell <john.powell@arm.com>

show more ...

fix(cpus): workaround for Cortex-A710 erratum 1901946

Cortex-A710 erratum 1901946 is a Cat B erratum that applies
to revision r1p0 and is fixed in r2p0.

The workaround is to set CPUACTLR4_EL1[15].

fix(cpus): workaround for Cortex-A710 erratum 1901946

Cortex-A710 erratum 1901946 is a Cat B erratum that applies
to revision r1p0 and is fixed in r2p0.

The workaround is to set CPUACTLR4_EL1[15]. This has a slight
performance impact.

SDEN documentation:
https://developer.arm.com/documentation/SDEN1775101

Change-Id: I703f0e6ee122e44a9bc284d90f1465039e3b40e4
Signed-off-by: John Powell <john.powell@arm.com>

show more ...

Merge changes If4cd4e71,I0b5158ef into integration

* changes:
docs(fvp): add FVP_HW_CONFIG_ADDR documentation
feat(fvp): add FVP_HW_CONFIG_ADDR make variable

Merge "docs(commit-style): add a message about lower case" into integration

Merge "fix(errata): keep leading zeros in CVE ID prints" into integration

Merge changes I6422cd05,Idd01179d,I5c557616,I343a46d6,Id48671ae, ... into integration

* changes:
feat(st-clock): add STM32MP21 and STM32MP23 RCC variants
feat(stm32mp21): add RCC registers file

Merge changes I6422cd05,Idd01179d,I5c557616,I343a46d6,Id48671ae, ... into integration

* changes:
feat(st-clock): add STM32MP21 and STM32MP23 RCC variants
feat(stm32mp21): add RCC registers file
feat(stm32mp21): add clock and reset bindings
refactor(stm32mp2): update display of reset reason
feat(stm32mp25): add RCC register to display all IWDG flags
feat(stm32mp21): add PWR registers file
feat(st): introduce SoC family compilation switch
docs(changelog): add subsections for STM32MP2
docs(stm32mp2): introduce new STM32MP23 family
docs(stm32mp2): introduce new STM32MP21 family

show more ...

Merge "fix(ti): remove validate_power_state definition" into integration

Merge changes I3303ca9a,I682da2d3 into integration

* changes:
feat(intel): migrate RSU client to SiPSVC V3
fix(intel): support generic mailbox command in SiPSVC V3

Merge "fix(intel): support SMC 64bit return args in SiPSVC V3" into integration

Merge changes I23e51bf9,I0fa9adaf into integration

* changes:
fix(intel): verify data size in AES GCM and GCM-GHASH modes
fix(intel): update FCS AES method for GCM block modes

Merge "fix(intel): update initialization to prevent warnings message" into integration

Merge "feat(intel): support IO96B ECC Error Injection via SMC call" into integration

Merge changes from topic "nxp-mmc/fixes" into integration

* changes:
feat(nxp-mmc): add dynamic mapping
fix(nxp-mmc): wait SDSTB before changing the clock
fix(nxp-mmc): fix the clock rate calc

Merge changes from topic "nxp-mmc/fixes" into integration

* changes:
feat(nxp-mmc): add dynamic mapping
fix(nxp-mmc): wait SDSTB before changing the clock
fix(nxp-mmc): fix the clock rate calculation
fix(nxp-mmc): remove unnecessary delay
feat(nxp-mmc): flush and invalidate buffers
feat(nxp-mmc): add data buffer
refactor(nxp-mmc): check multi block transfer
refactor(nxp-mmc): set MIXCTRL_DTDSEL
refactor(nxp-mmc): populate command transfer type
fix(nxp-mmc): fix clk_rate and bus_width type
fix(nxp-mmc): correct the usage of BIT and GENMASK
docs(changelog): add subsection for uSDHC

show more ...

Merge changes from topic "xlnx_versal2_cpuidle_fix" into integration

* changes:
fix(versal2): fix offsets for apu pcil
fix(versal2): initialize counter-timer frequency register
fix(versal2): u

Merge changes from topic "xlnx_versal2_cpuidle_fix" into integration

* changes:
fix(versal2): fix offsets for apu pcil
fix(versal2): initialize counter-timer frequency register
fix(versal2): use common function to get system counter frequency
fix(versal2): align IOU_SCNTR base address macro name with other platforms

show more ...

fix(versal2): validate Node ID in PM callback events

The PM_NOTIFY_CB is used to notify both events and errors from the PLM
firmware. The values of events and errors can overlap, they can be
disting

fix(versal2): validate Node ID in PM callback events

The PM_NOTIFY_CB is used to notify both events and errors from the PLM
firmware. The values of events and errors can overlap, they can be
distinguished using the Node ID, which is included in the callback payload.

Currently, when an EVENT_CPU_PWRDWN notification is received, TF-A powers
down cores without validating the Node ID. This leads to incorrect
behavior, as TFA powers down cores even when an error occurs that shares
the same event value.

Add a Node ID check to differentiate between events and errors to fix
this issue.

Change-Id: I65d69731b692928597e47678c684aea2b90b5e6d
Signed-off-by: Naman Trivedi <naman.trivedimanojbhai@amd.com>

show more ...