feat(juno): change PLAT_SP_IMAGE_NS_BUF_BASE

As PLAT_SP_IMAGE_NS_BUF_BASE is moved to NS_DRAM1 area [0],
PLAT_ARM_SP_IMAGE_STACK_BASE should be changed to
(PLAT_SPM_BUF_BASE + PLAT_SPM_BUF_SIZE)

Li

feat(juno): change PLAT_SP_IMAGE_NS_BUF_BASE

As PLAT_SP_IMAGE_NS_BUF_BASE is moved to NS_DRAM1 area [0],
PLAT_ARM_SP_IMAGE_STACK_BASE should be changed to
(PLAT_SPM_BUF_BASE + PLAT_SPM_BUF_SIZE)

Link: https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/40336 [0]
Signed-off-by: Yeoreum Yun <yeoreum.yun@arm.com>
Change-Id: I638fd7346853894d3377d63fc7fb4daf48415602

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feat(fvp): add extra DRAM configuration for TZC

As number of ARM_TZC_REGIONS_DEF is reduced by moving
PLAT_SP_IMAGE_NS_BUF_BASE into NS_DRAM1 area [0],
in SPM_MM or SPMC_AT_EL3, extra DRAM can be co

feat(fvp): add extra DRAM configuration for TZC

As number of ARM_TZC_REGIONS_DEF is reduced by moving
PLAT_SP_IMAGE_NS_BUF_BASE into NS_DRAM1 area [0],
in SPM_MM or SPMC_AT_EL3, extra DRAM can be configured in TZC.

Link: https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/40336 [0]
Signed-off-by: Yeoreum Yun <yeoreum.yun@arm.com>
Change-Id: I08e01016f0f4c534e08744117f36fb1fbd1b6e04

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feat(fvp): change PLAT_SP_IMAGE_NS_BUF_BASE

As PLAT_SP_IMAGE_NS_BUF_BASE is moved to NS_DRAM1 area [0],
PLAT_ARM_SP_IMAGE_STACK_BASE should be changed to
(PLAT_SPM_BUF_BASE + PLAT_SPM_BUF_SIZE)

Lin

feat(fvp): change PLAT_SP_IMAGE_NS_BUF_BASE

As PLAT_SP_IMAGE_NS_BUF_BASE is moved to NS_DRAM1 area [0],
PLAT_ARM_SP_IMAGE_STACK_BASE should be changed to
(PLAT_SPM_BUF_BASE + PLAT_SPM_BUF_SIZE)

Link: https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/40336 [0]
Signed-off-by: Yeoreum Yun <yeoreum.yun@arm.com>
Change-Id: Ic784dfcce921182968854a0fc90487754a8f59c8

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feat(neoverse-rd): change PLAT_SP_IMAGE_NS_BUF_BASE

As PLAT_SP_IMAGE_NS_BUF_BASE is moved to NS_DRAM1 area [0],
PLAT_ARM_SP_IMAGE_STACK_BASE should be changed to
(PLAT_SPM_BUF_BASE + PLAT_SPM_BUF_SI

feat(neoverse-rd): change PLAT_SP_IMAGE_NS_BUF_BASE

As PLAT_SP_IMAGE_NS_BUF_BASE is moved to NS_DRAM1 area [0],
PLAT_ARM_SP_IMAGE_STACK_BASE should be changed to
(PLAT_SPM_BUF_BASE + PLAT_SPM_BUF_SIZE)

Link: https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/40336 [0]
Signed-off-by: Yeoreum Yun <yeoreum.yun@arm.com>
Change-Id: I421b1f1283600de81024c7415af9919c9afbe138

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feat(tc): change PLAT_SP_IMAGE_NS_BUF_BASE

As PLAT_SP_IMAGE_NS_BUF_BASE is moved to NS_DRAM1 area [0],
PLAT_ARM_SP_IMAGE_STACK_BASE should be changed to
(PLAT_SPM_BUF_BASE + PLAT_SPM_BUF_SIZE)

Link

feat(tc): change PLAT_SP_IMAGE_NS_BUF_BASE

As PLAT_SP_IMAGE_NS_BUF_BASE is moved to NS_DRAM1 area [0],
PLAT_ARM_SP_IMAGE_STACK_BASE should be changed to
(PLAT_SPM_BUF_BASE + PLAT_SPM_BUF_SIZE)

Link: https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/40336 [0]
Signed-off-by: Yeoreum Yun <yeoreum.yun@arm.com>
Change-Id: I6e97954a1ce91fdbda4edcdba5ccfa1d7c8ff475

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feat(arm): introduce ARM_SPM_NS_MEM_BASE and move NS buffer

PLAT_SP_IMAGE_NS_BUF_BASE in arm_spm_def.h is located in
ARM_AP_TZC_DRAM1_BASE.
Because of this, to use PLAT_SP_IMAGE_NS_BUF_BASE in norma

feat(arm): introduce ARM_SPM_NS_MEM_BASE and move NS buffer

PLAT_SP_IMAGE_NS_BUF_BASE in arm_spm_def.h is located in
ARM_AP_TZC_DRAM1_BASE.
Because of this, to use PLAT_SP_IMAGE_NS_BUF_BASE in normal world,
the TZC region configuration is required like this:

0: ARM_AP_TZC_DRAM1_BASE to PLAT_SP_IMAGE_NS_BUF_BASE (secure only)
1: PLAT_SP_IMAGE_NS_BUF_BASE to PLAT_SP_IMAGE_NS_BUF_SIZE
(ns and secure)
2: PLAT_SP_IMAGE_NS_BASE + PLAT_SP_IMAGE_NS_BUF_SIZE to
ARM_AP_TZC_DRAM1_BASE + ARM_EL3_TZC_DRAM1_END (secure only)

To reduce TZC area for PLAT_SP_IMAGE_NS_BUF_BASE
Let add ARM_SPM_NS_MEM_BASE where located in
(ARM_AP_TZC_DRAM1_BASE) - 1MB as much as 1MB.
and locate PLAT_SP_IMAGE_NS_BUF in this area.

So that reduce the TZC region in ARM_TZC_REGIONS_DEF.

Change-Id: Ia6170f5eec893dde2e3bbd85de46788c4bf35292
Signed-off-by: Yeoreum Yun <yeoreum.yun@arm.com>

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Merge "fix(smccc): modify feat discovery to use aarch64 value" into integration

Merge "build: fix incorrect `memory summary` command" into integration

build: fix incorrect `memory summary` command

Change-Id: I2bce33a373ba44bddeccf31f0ba55a0ffe76711f
Signed-off-by: Chris Kay <chris.kay@arm.com>

fix(smccc): modify feat discovery to use aarch64 value

Fix SMCCC_ARCH_FEAT_AVAILABILITY to use aarch64 value

Change-Id: I0ff49a388070c90fd0d7d7c071b4109a7d59a9c9
Signed-off-by: Sona Mathew <SonaReb

fix(smccc): modify feat discovery to use aarch64 value

Fix SMCCC_ARCH_FEAT_AVAILABILITY to use aarch64 value

Change-Id: I0ff49a388070c90fd0d7d7c071b4109a7d59a9c9
Signed-off-by: Sona Mathew <SonaRebecca.Mathew@arm.com>

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fix(cpus): organize Cortex-X2 errata entries

The entries in cpu-ops.mk and cpu-specific-build-macros.rst are out of
order and the formatting is not consistent. This patch corrects these
minor format

fix(cpus): organize Cortex-X2 errata entries

The entries in cpu-ops.mk and cpu-specific-build-macros.rst are out of
order and the formatting is not consistent. This patch corrects these
minor formatting issues.

Change-Id: Ic01517d58d3ca1b2d39be5282b0058c94fa5d0e7
Signed-off-by: John Powell <john.powell@arm.com>

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fix(cpus): workaround for Cortex-X2 erratum 2291219

Cortex-X2 erratum 2291219 is a Cat B erratum that applies to
revisions r0p0, r1p0 and r2p0 and is fixed in r2p1.

The workaround is to set CPUACTL

fix(cpus): workaround for Cortex-X2 erratum 2291219

Cortex-X2 erratum 2291219 is a Cat B erratum that applies to
revisions r0p0, r1p0 and r2p0 and is fixed in r2p1.

The workaround is to set CPUACTLR2_EL1[36] before the power
down sequence that sets PWRDN_EN and executes WFI. This bit
should be be cleared after exiting WFI.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-1775100/latest

Change-Id: I43af57961feba3a1c001d09ad804740b996f1db7
Signed-off-by: John Powell <john.powell@arm.com>

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fix(cpus): workaround for Cortex-X2 erratum 2267065

Cortex-X2 erratum 2267065 is a Cat B erratum that applies to
revisions r0p0, r1p0 and r2p0 and is fixed in r2p1.

The workaround is to set CPUACTL

fix(cpus): workaround for Cortex-X2 erratum 2267065

Cortex-X2 erratum 2267065 is a Cat B erratum that applies to
revisions r0p0, r1p0 and r2p0 and is fixed in r2p1.

The workaround is to set CPUACTLR_EL1[22].

SDEN documentation:
https://developer.arm.com/documentation/SDEN-1775100/latest

Change-Id: I540e113f209ef11ec7103d4ef4e48ffb52416b4e
Signed-off-by: John Powell <john.powell@arm.com>

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fix(cpus): workaround for Cortex-X2 erratum 2136059

Cortex-X2 erratum 2136059 is a Cat B erratum that applies to
revisions r0p0, r1p0 and r2p0 and is fixed in r2p1.

The workaround is to set CPUACTL

fix(cpus): workaround for Cortex-X2 erratum 2136059

Cortex-X2 erratum 2136059 is a Cat B erratum that applies to
revisions r0p0, r1p0 and r2p0 and is fixed in r2p1.

The workaround is to set CPUACTLR5_EL1[44].

SDEN documentation:
https://developer.arm.com/documentation/SDEN-1775100/latest

Change-Id: I156467537c3f235b50fc8aa19a969f2798bd891b
Signed-off-by: John Powell <john.powell@arm.com>

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fix(cpus): workaround for Cortex-X2 erratum 1934260

Cortex-X2 erratum 1934260 is a Cat B erratum that applies only
to revision r1p0 and is fixed in r2p0.

The workaround is to set CPUECTLR_EL1[25:18

fix(cpus): workaround for Cortex-X2 erratum 1934260

Cortex-X2 erratum 1934260 is a Cat B erratum that applies only
to revision r1p0 and is fixed in r2p0.

The workaround is to set CPUECTLR_EL1[25:18] to 0xFF. This
workaround will result in reduced performance for workloads
that benefit from write streaming.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-1775100/latest

Change-Id: I180d38fee27175dc8ac5fa6726e5b71c3340285f
Signed-off-by: John Powell <john.powell@arm.com>

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fix(cpus): workaround for Cortex-X2 erratum 1927200

Cortex-X2 erratum 1927200 is a Cat B erratum that applies to
revisions r0p0 and r1p0 and is fixed in r2p0.

The workaround is to use instruction p

fix(cpus): workaround for Cortex-X2 erratum 1927200

Cortex-X2 erratum 1927200 is a Cat B erratum that applies to
revisions r0p0 and r1p0 and is fixed in r2p0.

The workaround is to use instruction patching to insert a DMB ST
before acquire atomic instructions without release semantics.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-1775100/latest

Change-Id: I8d9038df1907888b3c5b2520d06bc150665e74a1
Signed-off-by: John Powell <john.powell@arm.com>

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fix(cpus): workaround for Cortex-X2 erratum 1917258

Cortex-X2 erratum 1917258 is a Cat B erratum that applies to
revisions r0p0 and r1p0 and is fixed in r2p0.

The workaround is to set CPUACTLR4_EL1

fix(cpus): workaround for Cortex-X2 erratum 1917258

Cortex-X2 erratum 1917258 is a Cat B erratum that applies to
revisions r0p0 and r1p0 and is fixed in r2p0.

The workaround is to set CPUACTLR4_EL1[43]. This has no
performance impact.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-1775100/latest

Change-Id: Ic18a5179856f861701f09b2556906a6722db8150
Signed-off-by: John Powell <john.powell@arm.com>

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fix(cpus): workaround for Cortex-X2 erratum 1916945

Cortex-X2 erratum 1916945 is a Cat B erratum that applies to
revisions r0p0 and r1p0 and is fixed in r2p0.

The workaround is to set CPUECTLR_EL1[

fix(cpus): workaround for Cortex-X2 erratum 1916945

Cortex-X2 erratum 1916945 is a Cat B erratum that applies to
revisions r0p0 and r1p0 and is fixed in r2p0.

The workaround is to set CPUECTLR_EL1[8]. This has a small
performance impact (<0.5%).

SDEN documentation:
https://developer.arm.com/documentation/SDEN-1775100/latest

Change-Id: If810b1d0a07c43b3e1aa70d2ec88c1dcfa6f735f
Signed-off-by: John Powell <john.powell@arm.com>

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fix(cpus): workaround for Cortex-X2 erratum 1901946

Cortex-X2 erratum 1901946 is a Cat B erratum that applies to
revision r1p0 and is fixed in r2p0.

The workaround is to set CPUACTLR4_EL1[15]. This

fix(cpus): workaround for Cortex-X2 erratum 1901946

Cortex-X2 erratum 1901946 is a Cat B erratum that applies to
revision r1p0 and is fixed in r2p0.

The workaround is to set CPUACTLR4_EL1[15]. This has a small
performance impact.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-1775100/latest

Change-Id: I5a65db60f06982191994db49815419c4d72506cf
Signed-off-by: John Powell <john.powell@arm.com>

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Merge "fix(cpus): put back the global declaration for erratum #3701747" into integration

fix(cpus): put back the global declaration for erratum #3701747

Patch 89dba82df accidentally removed it. Put it back.

Change-Id: Ic7a5a13ae89b0b86ccbea56fecfe12bef57a90b9
Signed-off-by: Boyan Karat

fix(cpus): put back the global declaration for erratum #3701747

Patch 89dba82df accidentally removed it. Put it back.

Change-Id: Ic7a5a13ae89b0b86ccbea56fecfe12bef57a90b9
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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fix(tools): renesas: rzg: Fix tool build

Since 2f1c5e7eb177 ("build: use GCC to link by default") the
code does not even compile with GCC14 on debian/unstable with
the following error:

/usr/lib/gcc

fix(tools): renesas: rzg: Fix tool build

Since 2f1c5e7eb177 ("build: use GCC to link by default") the
code does not even compile with GCC14 on debian/unstable with
the following error:

/usr/lib/gcc-cross/aarch64-linux-gnu/14/../../../../aarch64-linux-gnu/bin/ld: bootparam_sa0.elf: error: PHDR segment not covered by LOAD segment
/usr/lib/gcc-cross/aarch64-linux-gnu/14/../../../../aarch64-linux-gnu/bin/ld: cert_header_sa6.elf: error: PHDR segment not covered by LOAD segment

Fix the tools build.

This change is similar to commit 72f4b70e8e8e ("fix(rcar-layout): fix tool build") done for R-Car tools.

Change-Id: Ie4fb6c4d32982a8ce399e1fde0736cb43c18b34d
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

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Merge "feat(gic): make IRQ groups optional" into integration

Merge changes from topic "hm/handoff-cot" into integration

* changes:
docs(fconf): streamline TB_FW_CONFIG bindings
refactor(fconf): use macro to set image info

fix(intel): remove wfi polling when performing cpu on

Polling the WFI status produces vague result as
the secondary CPU will keep changing it's states.

Removing the polling WFI code as this will ca

fix(intel): remove wfi polling when performing cpu on

Polling the WFI status produces vague result as
the secondary CPU will keep changing it's states.

Removing the polling WFI code as this will cause
polling timeout since the CPU state is uncertain.

The CPU ON function will still work by removing this
check.

Change-Id: I1bb556a83ca16e122dfa35343de3e7cc39c5b678
Signed-off-by: Boon Khai Ng <boon.khai.ng@altera.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@altera.com>

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