1/* 2 * Copyright (c) 2021-2025, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <cortex_x2.h> 11#include <cpu_macros.S> 12#include <dsu_macros.S> 13#include <plat_macros.S> 14#include "wa_cve_2022_23960_bhb_vector.S" 15 16/* Hardware handled coherency */ 17#if HW_ASSISTED_COHERENCY == 0 18#error "Cortex X2 must be compiled with HW_ASSISTED_COHERENCY enabled" 19#endif 20 21/* 64-bit only core */ 22#if CTX_INCLUDE_AARCH32_REGS == 1 23#error "Cortex X2 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 24#endif 25 26.global check_erratum_cortex_x2_3701772 27 28#if WORKAROUND_CVE_2022_23960 29 wa_cve_2022_23960_bhb_vector_table CORTEX_X2_BHB_LOOP_COUNT, cortex_x2 30#endif /* WORKAROUND_CVE_2022_23960 */ 31 32cpu_reset_prologue cortex_x2 33 34workaround_reset_start cortex_x2, ERRATUM(1901946), ERRATA_X2_1901946 35 sysreg_bit_set CORTEX_X2_CPUACTLR4_EL1, BIT(15) 36workaround_reset_end cortex_x2, ERRATUM(1901946) 37 38check_erratum_range cortex_x2, ERRATUM(1901946), CPU_REV(1, 0), CPU_REV(1, 0) 39 40workaround_reset_start cortex_x2, ERRATUM(2002765), ERRATA_X2_2002765 41 ldr x0, =0x6 42 msr S3_6_C15_C8_0, x0 /* CPUPSELR_EL3 */ 43 ldr x0, =0xF3A08002 44 msr S3_6_C15_C8_2, x0 /* CPUPOR_EL3 */ 45 ldr x0, =0xFFF0F7FE 46 msr S3_6_C15_C8_3, x0 /* CPUPMR_EL3 */ 47 ldr x0, =0x40000001003ff 48 msr S3_6_C15_C8_1, x0 /* CPUPCR_EL3 */ 49workaround_reset_end cortex_x2, ERRATUM(2002765) 50 51check_erratum_ls cortex_x2, ERRATUM(2002765), CPU_REV(2, 0) 52 53workaround_reset_start cortex_x2, ERRATUM(2017096), ERRATA_X2_2017096 54 sysreg_bit_set CORTEX_X2_CPUECTLR_EL1, CORTEX_X2_CPUECTLR_EL1_PFSTIDIS_BIT 55workaround_reset_end cortex_x2, ERRATUM(2017096) 56 57check_erratum_ls cortex_x2, ERRATUM(2017096), CPU_REV(2, 0) 58 59workaround_reset_start cortex_x2, ERRATUM(2081180), ERRATA_X2_2081180 60 /* Apply instruction patching sequence */ 61 ldr x0, =0x3 62 msr CORTEX_X2_IMP_CPUPSELR_EL3, x0 63 ldr x0, =0xF3A08002 64 msr CORTEX_X2_IMP_CPUPOR_EL3, x0 65 ldr x0, =0xFFF0F7FE 66 msr CORTEX_X2_IMP_CPUPMR_EL3, x0 67 ldr x0, =0x10002001003FF 68 msr CORTEX_X2_IMP_CPUPCR_EL3, x0 69 ldr x0, =0x4 70 msr CORTEX_X2_IMP_CPUPSELR_EL3, x0 71 ldr x0, =0xBF200000 72 msr CORTEX_X2_IMP_CPUPOR_EL3, x0 73 ldr x0, =0xFFEF0000 74 msr CORTEX_X2_IMP_CPUPMR_EL3, x0 75 ldr x0, =0x10002001003F3 76 msr CORTEX_X2_IMP_CPUPCR_EL3, x0 77workaround_reset_end cortex_x2, ERRATUM(2081180) 78 79check_erratum_ls cortex_x2, ERRATUM(2081180), CPU_REV(2, 0) 80 81workaround_reset_start cortex_x2, ERRATUM(2083908), ERRATA_X2_2083908 82 /* Apply the workaround by setting bit 13 in CPUACTLR5_EL1. */ 83 sysreg_bit_set CORTEX_X2_CPUACTLR5_EL1, BIT(13) 84workaround_reset_end cortex_x2, ERRATUM(2083908) 85 86check_erratum_range cortex_x2, ERRATUM(2083908), CPU_REV(2, 0), CPU_REV(2, 0) 87 88workaround_reset_start cortex_x2, ERRATUM(2147715), ERRATA_X2_2147715 89 /* Apply the workaround by setting bit 22 in CPUACTLR_EL1. */ 90 sysreg_bit_set CORTEX_X2_CPUACTLR_EL1, CORTEX_X2_CPUACTLR_EL1_BIT_22 91workaround_reset_end cortex_x2, ERRATUM(2147715) 92 93check_erratum_range cortex_x2, ERRATUM(2147715), CPU_REV(2, 0), CPU_REV(2, 0) 94 95workaround_reset_start cortex_x2, ERRATUM(2216384), ERRATA_X2_2216384 96 sysreg_bit_set CORTEX_X2_CPUACTLR5_EL1, CORTEX_X2_CPUACTLR5_EL1_BIT_17 97 98 /* Apply instruction patching sequence */ 99 ldr x0, =0x5 100 msr CORTEX_X2_IMP_CPUPSELR_EL3, x0 101 ldr x0, =0x10F600E000 102 msr CORTEX_X2_IMP_CPUPOR_EL3, x0 103 ldr x0, =0x10FF80E000 104 msr CORTEX_X2_IMP_CPUPMR_EL3, x0 105 ldr x0, =0x80000000003FF 106 msr CORTEX_X2_IMP_CPUPCR_EL3, x0 107workaround_reset_end cortex_x2, ERRATUM(2216384) 108 109check_erratum_ls cortex_x2, ERRATUM(2216384), CPU_REV(2, 0) 110 111workaround_reset_start cortex_x2, ERRATUM(2282622), ERRATA_X2_2282622 112 /* Apply the workaround */ 113 sysreg_bit_set CORTEX_X2_CPUACTLR2_EL1, BIT(0) 114workaround_reset_end cortex_x2, ERRATUM(2282622) 115 116check_erratum_ls cortex_x2, ERRATUM(2282622), CPU_REV(2, 1) 117 118workaround_reset_start cortex_x2, ERRATUM(2313941), ERRATA_DSU_2313941 119 errata_dsu_2313941_wa_impl 120workaround_reset_end cortex_x2, ERRATUM(2313941) 121 122check_erratum_custom_start cortex_x2, ERRATUM(2313941) 123 check_errata_dsu_2313941_impl 124 ret 125check_erratum_custom_end cortex_x2, ERRATUM(2313941) 126 127workaround_reset_start cortex_x2, ERRATUM(2371105), ERRATA_X2_2371105 128 /* Set bit 40 in CPUACTLR2_EL1 */ 129 sysreg_bit_set CORTEX_X2_CPUACTLR2_EL1, CORTEX_X2_CPUACTLR2_EL1_BIT_40 130workaround_reset_end cortex_x2, ERRATUM(2371105) 131 132check_erratum_ls cortex_x2, ERRATUM(2371105), CPU_REV(2, 0) 133 134workaround_reset_start cortex_x2, ERRATUM(2742423), ERRATA_X2_2742423 135 /* Set CPUACTLR5_EL1[56:55] to 2'b01 */ 136 sysreg_bit_set CORTEX_X2_CPUACTLR5_EL1, BIT(55) 137 sysreg_bit_clear CORTEX_X2_CPUACTLR5_EL1, BIT(56) 138workaround_reset_end cortex_x2, ERRATUM(2742423) 139 140check_erratum_ls cortex_x2, ERRATUM(2742423), CPU_REV(2, 1) 141 142workaround_runtime_start cortex_x2, ERRATUM(2768515), ERRATA_X2_2768515 143 /* dsb before isb of power down sequence */ 144 dsb sy 145workaround_runtime_end cortex_x2, ERRATUM(2768515) 146 147check_erratum_ls cortex_x2, ERRATUM(2768515), CPU_REV(2, 1) 148 149workaround_reset_start cortex_x2, ERRATUM(2778471), ERRATA_X2_2778471 150 sysreg_bit_set CORTEX_X2_CPUACTLR3_EL1, BIT(47) 151workaround_reset_end cortex_x2, ERRATUM(2778471) 152 153check_erratum_ls cortex_x2, ERRATUM(2778471), CPU_REV(2, 1) 154 155add_erratum_entry cortex_x2, ERRATUM(3701772), ERRATA_X2_3701772 156 157check_erratum_ls cortex_x2, ERRATUM(3701772), CPU_REV(2, 1) 158 159workaround_reset_start cortex_x2, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 160#if IMAGE_BL31 161 /* 162 * The Cortex-X2 generic vectors are overridden to apply errata 163 * mitigation on exception entry from lower ELs. 164 */ 165 override_vector_table wa_cve_vbar_cortex_x2 166#endif /* IMAGE_BL31 */ 167workaround_reset_end cortex_x2, CVE(2022, 23960) 168 169check_erratum_chosen cortex_x2, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 170 171/* Disable hardware page aggregation. Enables mitigation for `CVE-2024-5660` */ 172workaround_reset_start cortex_x2, CVE(2024, 5660), WORKAROUND_CVE_2024_5660 173 sysreg_bit_set CORTEX_X2_CPUECTLR_EL1, BIT(46) 174workaround_reset_end cortex_x2, CVE(2024, 5660) 175 176check_erratum_ls cortex_x2, CVE(2024, 5660), CPU_REV(2, 1) 177 178 /* ---------------------------------------------------- 179 * HW will do the cache maintenance while powering down 180 * ---------------------------------------------------- 181 */ 182func cortex_x2_core_pwr_dwn 183 /* --------------------------------------------------- 184 * Enable CPU power down bit in power control register 185 * --------------------------------------------------- 186 */ 187 sysreg_bit_set CORTEX_X2_CPUPWRCTLR_EL1, CORTEX_X2_CPUPWRCTLR_EL1_CORE_PWRDN_BIT 188 189 apply_erratum cortex_x2, ERRATUM(2768515), ERRATA_X2_2768515 190 isb 191 ret 192endfunc cortex_x2_core_pwr_dwn 193 194cpu_reset_func_start cortex_x2 195 /* Disable speculative loads */ 196 msr SSBS, xzr 197 enable_mpmm 198cpu_reset_func_end cortex_x2 199 200 /* --------------------------------------------- 201 * This function provides Cortex X2 specific 202 * register information for crash reporting. 203 * It needs to return with x6 pointing to 204 * a list of register names in ascii and 205 * x8 - x15 having values of registers to be 206 * reported. 207 * --------------------------------------------- 208 */ 209.section .rodata.cortex_x2_regs, "aS" 210cortex_x2_regs: /* The ascii list of register names to be reported */ 211 .asciz "cpuectlr_el1", "" 212 213func cortex_x2_cpu_reg_dump 214 adr x6, cortex_x2_regs 215 mrs x8, CORTEX_X2_CPUECTLR_EL1 216 ret 217endfunc cortex_x2_cpu_reg_dump 218 219declare_cpu_ops cortex_x2, CORTEX_X2_MIDR, \ 220 cortex_x2_reset_func, \ 221 cortex_x2_core_pwr_dwn 222