1/* 2 * Copyright (c) 2021-2025, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <cortex_x2.h> 11#include <cpu_macros.S> 12#include <dsu_macros.S> 13#include <plat_macros.S> 14#include "wa_cve_2022_23960_bhb_vector.S" 15 16/* Hardware handled coherency */ 17#if HW_ASSISTED_COHERENCY == 0 18#error "Cortex X2 must be compiled with HW_ASSISTED_COHERENCY enabled" 19#endif 20 21/* 64-bit only core */ 22#if CTX_INCLUDE_AARCH32_REGS == 1 23#error "Cortex X2 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 24#endif 25 26.global check_erratum_cortex_x2_3701772 27 28#if WORKAROUND_CVE_2022_23960 29 wa_cve_2022_23960_bhb_vector_table CORTEX_X2_BHB_LOOP_COUNT, cortex_x2 30#endif /* WORKAROUND_CVE_2022_23960 */ 31 32cpu_reset_prologue cortex_x2 33 34workaround_reset_start cortex_x2, ERRATUM(1901946), ERRATA_X2_1901946 35 sysreg_bit_set CORTEX_X2_CPUACTLR4_EL1, BIT(15) 36workaround_reset_end cortex_x2, ERRATUM(1901946) 37 38check_erratum_range cortex_x2, ERRATUM(1901946), CPU_REV(1, 0), CPU_REV(1, 0) 39 40workaround_reset_start cortex_x2, ERRATUM(1916945), ERRATA_X2_1916945 41 sysreg_bit_set CORTEX_X2_CPUECTLR_EL1, BIT(8) 42workaround_reset_end cortex_x2, ERRATUM(1916945) 43 44check_erratum_ls cortex_x2, ERRATUM(1916945), CPU_REV(1, 0) 45 46workaround_reset_start cortex_x2, ERRATUM(2002765), ERRATA_X2_2002765 47 ldr x0, =0x6 48 msr S3_6_C15_C8_0, x0 /* CPUPSELR_EL3 */ 49 ldr x0, =0xF3A08002 50 msr S3_6_C15_C8_2, x0 /* CPUPOR_EL3 */ 51 ldr x0, =0xFFF0F7FE 52 msr S3_6_C15_C8_3, x0 /* CPUPMR_EL3 */ 53 ldr x0, =0x40000001003ff 54 msr S3_6_C15_C8_1, x0 /* CPUPCR_EL3 */ 55workaround_reset_end cortex_x2, ERRATUM(2002765) 56 57check_erratum_ls cortex_x2, ERRATUM(2002765), CPU_REV(2, 0) 58 59workaround_reset_start cortex_x2, ERRATUM(2017096), ERRATA_X2_2017096 60 sysreg_bit_set CORTEX_X2_CPUECTLR_EL1, CORTEX_X2_CPUECTLR_EL1_PFSTIDIS_BIT 61workaround_reset_end cortex_x2, ERRATUM(2017096) 62 63check_erratum_ls cortex_x2, ERRATUM(2017096), CPU_REV(2, 0) 64 65workaround_reset_start cortex_x2, ERRATUM(2081180), ERRATA_X2_2081180 66 /* Apply instruction patching sequence */ 67 ldr x0, =0x3 68 msr CORTEX_X2_IMP_CPUPSELR_EL3, x0 69 ldr x0, =0xF3A08002 70 msr CORTEX_X2_IMP_CPUPOR_EL3, x0 71 ldr x0, =0xFFF0F7FE 72 msr CORTEX_X2_IMP_CPUPMR_EL3, x0 73 ldr x0, =0x10002001003FF 74 msr CORTEX_X2_IMP_CPUPCR_EL3, x0 75 ldr x0, =0x4 76 msr CORTEX_X2_IMP_CPUPSELR_EL3, x0 77 ldr x0, =0xBF200000 78 msr CORTEX_X2_IMP_CPUPOR_EL3, x0 79 ldr x0, =0xFFEF0000 80 msr CORTEX_X2_IMP_CPUPMR_EL3, x0 81 ldr x0, =0x10002001003F3 82 msr CORTEX_X2_IMP_CPUPCR_EL3, x0 83workaround_reset_end cortex_x2, ERRATUM(2081180) 84 85check_erratum_ls cortex_x2, ERRATUM(2081180), CPU_REV(2, 0) 86 87workaround_reset_start cortex_x2, ERRATUM(2083908), ERRATA_X2_2083908 88 /* Apply the workaround by setting bit 13 in CPUACTLR5_EL1. */ 89 sysreg_bit_set CORTEX_X2_CPUACTLR5_EL1, BIT(13) 90workaround_reset_end cortex_x2, ERRATUM(2083908) 91 92check_erratum_range cortex_x2, ERRATUM(2083908), CPU_REV(2, 0), CPU_REV(2, 0) 93 94workaround_reset_start cortex_x2, ERRATUM(2147715), ERRATA_X2_2147715 95 /* Apply the workaround by setting bit 22 in CPUACTLR_EL1. */ 96 sysreg_bit_set CORTEX_X2_CPUACTLR_EL1, CORTEX_X2_CPUACTLR_EL1_BIT_22 97workaround_reset_end cortex_x2, ERRATUM(2147715) 98 99check_erratum_range cortex_x2, ERRATUM(2147715), CPU_REV(2, 0), CPU_REV(2, 0) 100 101workaround_reset_start cortex_x2, ERRATUM(2216384), ERRATA_X2_2216384 102 sysreg_bit_set CORTEX_X2_CPUACTLR5_EL1, CORTEX_X2_CPUACTLR5_EL1_BIT_17 103 104 /* Apply instruction patching sequence */ 105 ldr x0, =0x5 106 msr CORTEX_X2_IMP_CPUPSELR_EL3, x0 107 ldr x0, =0x10F600E000 108 msr CORTEX_X2_IMP_CPUPOR_EL3, x0 109 ldr x0, =0x10FF80E000 110 msr CORTEX_X2_IMP_CPUPMR_EL3, x0 111 ldr x0, =0x80000000003FF 112 msr CORTEX_X2_IMP_CPUPCR_EL3, x0 113workaround_reset_end cortex_x2, ERRATUM(2216384) 114 115check_erratum_ls cortex_x2, ERRATUM(2216384), CPU_REV(2, 0) 116 117workaround_reset_start cortex_x2, ERRATUM(2282622), ERRATA_X2_2282622 118 /* Apply the workaround */ 119 sysreg_bit_set CORTEX_X2_CPUACTLR2_EL1, BIT(0) 120workaround_reset_end cortex_x2, ERRATUM(2282622) 121 122check_erratum_ls cortex_x2, ERRATUM(2282622), CPU_REV(2, 1) 123 124workaround_reset_start cortex_x2, ERRATUM(2313941), ERRATA_DSU_2313941 125 errata_dsu_2313941_wa_impl 126workaround_reset_end cortex_x2, ERRATUM(2313941) 127 128check_erratum_custom_start cortex_x2, ERRATUM(2313941) 129 check_errata_dsu_2313941_impl 130 ret 131check_erratum_custom_end cortex_x2, ERRATUM(2313941) 132 133workaround_reset_start cortex_x2, ERRATUM(2371105), ERRATA_X2_2371105 134 /* Set bit 40 in CPUACTLR2_EL1 */ 135 sysreg_bit_set CORTEX_X2_CPUACTLR2_EL1, CORTEX_X2_CPUACTLR2_EL1_BIT_40 136workaround_reset_end cortex_x2, ERRATUM(2371105) 137 138check_erratum_ls cortex_x2, ERRATUM(2371105), CPU_REV(2, 0) 139 140workaround_reset_start cortex_x2, ERRATUM(2742423), ERRATA_X2_2742423 141 /* Set CPUACTLR5_EL1[56:55] to 2'b01 */ 142 sysreg_bit_set CORTEX_X2_CPUACTLR5_EL1, BIT(55) 143 sysreg_bit_clear CORTEX_X2_CPUACTLR5_EL1, BIT(56) 144workaround_reset_end cortex_x2, ERRATUM(2742423) 145 146check_erratum_ls cortex_x2, ERRATUM(2742423), CPU_REV(2, 1) 147 148workaround_runtime_start cortex_x2, ERRATUM(2768515), ERRATA_X2_2768515 149 /* dsb before isb of power down sequence */ 150 dsb sy 151workaround_runtime_end cortex_x2, ERRATUM(2768515) 152 153check_erratum_ls cortex_x2, ERRATUM(2768515), CPU_REV(2, 1) 154 155workaround_reset_start cortex_x2, ERRATUM(2778471), ERRATA_X2_2778471 156 sysreg_bit_set CORTEX_X2_CPUACTLR3_EL1, BIT(47) 157workaround_reset_end cortex_x2, ERRATUM(2778471) 158 159check_erratum_ls cortex_x2, ERRATUM(2778471), CPU_REV(2, 1) 160 161add_erratum_entry cortex_x2, ERRATUM(3701772), ERRATA_X2_3701772 162 163check_erratum_ls cortex_x2, ERRATUM(3701772), CPU_REV(2, 1) 164 165workaround_reset_start cortex_x2, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 166#if IMAGE_BL31 167 /* 168 * The Cortex-X2 generic vectors are overridden to apply errata 169 * mitigation on exception entry from lower ELs. 170 */ 171 override_vector_table wa_cve_vbar_cortex_x2 172#endif /* IMAGE_BL31 */ 173workaround_reset_end cortex_x2, CVE(2022, 23960) 174 175check_erratum_chosen cortex_x2, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 176 177/* Disable hardware page aggregation. Enables mitigation for `CVE-2024-5660` */ 178workaround_reset_start cortex_x2, CVE(2024, 5660), WORKAROUND_CVE_2024_5660 179 sysreg_bit_set CORTEX_X2_CPUECTLR_EL1, BIT(46) 180workaround_reset_end cortex_x2, CVE(2024, 5660) 181 182check_erratum_ls cortex_x2, CVE(2024, 5660), CPU_REV(2, 1) 183 184 /* ---------------------------------------------------- 185 * HW will do the cache maintenance while powering down 186 * ---------------------------------------------------- 187 */ 188func cortex_x2_core_pwr_dwn 189 /* --------------------------------------------------- 190 * Enable CPU power down bit in power control register 191 * --------------------------------------------------- 192 */ 193 sysreg_bit_set CORTEX_X2_CPUPWRCTLR_EL1, CORTEX_X2_CPUPWRCTLR_EL1_CORE_PWRDN_BIT 194 195 apply_erratum cortex_x2, ERRATUM(2768515), ERRATA_X2_2768515 196 isb 197 ret 198endfunc cortex_x2_core_pwr_dwn 199 200cpu_reset_func_start cortex_x2 201 /* Disable speculative loads */ 202 msr SSBS, xzr 203 enable_mpmm 204cpu_reset_func_end cortex_x2 205 206 /* --------------------------------------------- 207 * This function provides Cortex X2 specific 208 * register information for crash reporting. 209 * It needs to return with x6 pointing to 210 * a list of register names in ascii and 211 * x8 - x15 having values of registers to be 212 * reported. 213 * --------------------------------------------- 214 */ 215.section .rodata.cortex_x2_regs, "aS" 216cortex_x2_regs: /* The ascii list of register names to be reported */ 217 .asciz "cpuectlr_el1", "" 218 219func cortex_x2_cpu_reg_dump 220 adr x6, cortex_x2_regs 221 mrs x8, CORTEX_X2_CPUECTLR_EL1 222 ret 223endfunc cortex_x2_cpu_reg_dump 224 225declare_cpu_ops cortex_x2, CORTEX_X2_MIDR, \ 226 cortex_x2_reset_func, \ 227 cortex_x2_core_pwr_dwn 228