1/* 2 * Copyright (c) 2021-2025, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <cortex_x2.h> 11#include <cpu_macros.S> 12#include <dsu_macros.S> 13#include <plat_macros.S> 14#include "wa_cve_2022_23960_bhb_vector.S" 15 16/* Hardware handled coherency */ 17#if HW_ASSISTED_COHERENCY == 0 18#error "Cortex X2 must be compiled with HW_ASSISTED_COHERENCY enabled" 19#endif 20 21/* 64-bit only core */ 22#if CTX_INCLUDE_AARCH32_REGS == 1 23#error "Cortex X2 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 24#endif 25 26.global check_erratum_cortex_x2_3701772 27 28#if WORKAROUND_CVE_2022_23960 29 wa_cve_2022_23960_bhb_vector_table CORTEX_X2_BHB_LOOP_COUNT, cortex_x2 30#endif /* WORKAROUND_CVE_2022_23960 */ 31 32cpu_reset_prologue cortex_x2 33 34workaround_reset_start cortex_x2, ERRATUM(1901946), ERRATA_X2_1901946 35 sysreg_bit_set CORTEX_X2_CPUACTLR4_EL1, BIT(15) 36workaround_reset_end cortex_x2, ERRATUM(1901946) 37 38check_erratum_range cortex_x2, ERRATUM(1901946), CPU_REV(1, 0), CPU_REV(1, 0) 39 40workaround_reset_start cortex_x2, ERRATUM(1916945), ERRATA_X2_1916945 41 sysreg_bit_set CORTEX_X2_CPUECTLR_EL1, BIT(8) 42workaround_reset_end cortex_x2, ERRATUM(1916945) 43 44check_erratum_ls cortex_x2, ERRATUM(1916945), CPU_REV(1, 0) 45 46workaround_reset_start cortex_x2, ERRATUM(1917258), ERRATA_X2_1917258 47 sysreg_bit_set CORTEX_X2_CPUACTLR4_EL1, BIT(43) 48workaround_reset_end cortex_x2, ERRATUM(1917258) 49 50check_erratum_ls cortex_x2, ERRATUM(1917258), CPU_REV(1, 0) 51 52workaround_reset_start cortex_x2, ERRATUM(2002765), ERRATA_X2_2002765 53 ldr x0, =0x6 54 msr S3_6_C15_C8_0, x0 /* CPUPSELR_EL3 */ 55 ldr x0, =0xF3A08002 56 msr S3_6_C15_C8_2, x0 /* CPUPOR_EL3 */ 57 ldr x0, =0xFFF0F7FE 58 msr S3_6_C15_C8_3, x0 /* CPUPMR_EL3 */ 59 ldr x0, =0x40000001003ff 60 msr S3_6_C15_C8_1, x0 /* CPUPCR_EL3 */ 61workaround_reset_end cortex_x2, ERRATUM(2002765) 62 63check_erratum_ls cortex_x2, ERRATUM(2002765), CPU_REV(2, 0) 64 65workaround_reset_start cortex_x2, ERRATUM(2017096), ERRATA_X2_2017096 66 sysreg_bit_set CORTEX_X2_CPUECTLR_EL1, CORTEX_X2_CPUECTLR_EL1_PFSTIDIS_BIT 67workaround_reset_end cortex_x2, ERRATUM(2017096) 68 69check_erratum_ls cortex_x2, ERRATUM(2017096), CPU_REV(2, 0) 70 71workaround_reset_start cortex_x2, ERRATUM(2081180), ERRATA_X2_2081180 72 /* Apply instruction patching sequence */ 73 ldr x0, =0x3 74 msr CORTEX_X2_IMP_CPUPSELR_EL3, x0 75 ldr x0, =0xF3A08002 76 msr CORTEX_X2_IMP_CPUPOR_EL3, x0 77 ldr x0, =0xFFF0F7FE 78 msr CORTEX_X2_IMP_CPUPMR_EL3, x0 79 ldr x0, =0x10002001003FF 80 msr CORTEX_X2_IMP_CPUPCR_EL3, x0 81 ldr x0, =0x4 82 msr CORTEX_X2_IMP_CPUPSELR_EL3, x0 83 ldr x0, =0xBF200000 84 msr CORTEX_X2_IMP_CPUPOR_EL3, x0 85 ldr x0, =0xFFEF0000 86 msr CORTEX_X2_IMP_CPUPMR_EL3, x0 87 ldr x0, =0x10002001003F3 88 msr CORTEX_X2_IMP_CPUPCR_EL3, x0 89workaround_reset_end cortex_x2, ERRATUM(2081180) 90 91check_erratum_ls cortex_x2, ERRATUM(2081180), CPU_REV(2, 0) 92 93workaround_reset_start cortex_x2, ERRATUM(2083908), ERRATA_X2_2083908 94 /* Apply the workaround by setting bit 13 in CPUACTLR5_EL1. */ 95 sysreg_bit_set CORTEX_X2_CPUACTLR5_EL1, BIT(13) 96workaround_reset_end cortex_x2, ERRATUM(2083908) 97 98check_erratum_range cortex_x2, ERRATUM(2083908), CPU_REV(2, 0), CPU_REV(2, 0) 99 100workaround_reset_start cortex_x2, ERRATUM(2147715), ERRATA_X2_2147715 101 /* Apply the workaround by setting bit 22 in CPUACTLR_EL1. */ 102 sysreg_bit_set CORTEX_X2_CPUACTLR_EL1, CORTEX_X2_CPUACTLR_EL1_BIT_22 103workaround_reset_end cortex_x2, ERRATUM(2147715) 104 105check_erratum_range cortex_x2, ERRATUM(2147715), CPU_REV(2, 0), CPU_REV(2, 0) 106 107workaround_reset_start cortex_x2, ERRATUM(2216384), ERRATA_X2_2216384 108 sysreg_bit_set CORTEX_X2_CPUACTLR5_EL1, CORTEX_X2_CPUACTLR5_EL1_BIT_17 109 110 /* Apply instruction patching sequence */ 111 ldr x0, =0x5 112 msr CORTEX_X2_IMP_CPUPSELR_EL3, x0 113 ldr x0, =0x10F600E000 114 msr CORTEX_X2_IMP_CPUPOR_EL3, x0 115 ldr x0, =0x10FF80E000 116 msr CORTEX_X2_IMP_CPUPMR_EL3, x0 117 ldr x0, =0x80000000003FF 118 msr CORTEX_X2_IMP_CPUPCR_EL3, x0 119workaround_reset_end cortex_x2, ERRATUM(2216384) 120 121check_erratum_ls cortex_x2, ERRATUM(2216384), CPU_REV(2, 0) 122 123workaround_reset_start cortex_x2, ERRATUM(2282622), ERRATA_X2_2282622 124 /* Apply the workaround */ 125 sysreg_bit_set CORTEX_X2_CPUACTLR2_EL1, BIT(0) 126workaround_reset_end cortex_x2, ERRATUM(2282622) 127 128check_erratum_ls cortex_x2, ERRATUM(2282622), CPU_REV(2, 1) 129 130workaround_reset_start cortex_x2, ERRATUM(2313941), ERRATA_DSU_2313941 131 errata_dsu_2313941_wa_impl 132workaround_reset_end cortex_x2, ERRATUM(2313941) 133 134check_erratum_custom_start cortex_x2, ERRATUM(2313941) 135 check_errata_dsu_2313941_impl 136 ret 137check_erratum_custom_end cortex_x2, ERRATUM(2313941) 138 139workaround_reset_start cortex_x2, ERRATUM(2371105), ERRATA_X2_2371105 140 /* Set bit 40 in CPUACTLR2_EL1 */ 141 sysreg_bit_set CORTEX_X2_CPUACTLR2_EL1, CORTEX_X2_CPUACTLR2_EL1_BIT_40 142workaround_reset_end cortex_x2, ERRATUM(2371105) 143 144check_erratum_ls cortex_x2, ERRATUM(2371105), CPU_REV(2, 0) 145 146workaround_reset_start cortex_x2, ERRATUM(2742423), ERRATA_X2_2742423 147 /* Set CPUACTLR5_EL1[56:55] to 2'b01 */ 148 sysreg_bit_set CORTEX_X2_CPUACTLR5_EL1, BIT(55) 149 sysreg_bit_clear CORTEX_X2_CPUACTLR5_EL1, BIT(56) 150workaround_reset_end cortex_x2, ERRATUM(2742423) 151 152check_erratum_ls cortex_x2, ERRATUM(2742423), CPU_REV(2, 1) 153 154workaround_runtime_start cortex_x2, ERRATUM(2768515), ERRATA_X2_2768515 155 /* dsb before isb of power down sequence */ 156 dsb sy 157workaround_runtime_end cortex_x2, ERRATUM(2768515) 158 159check_erratum_ls cortex_x2, ERRATUM(2768515), CPU_REV(2, 1) 160 161workaround_reset_start cortex_x2, ERRATUM(2778471), ERRATA_X2_2778471 162 sysreg_bit_set CORTEX_X2_CPUACTLR3_EL1, BIT(47) 163workaround_reset_end cortex_x2, ERRATUM(2778471) 164 165check_erratum_ls cortex_x2, ERRATUM(2778471), CPU_REV(2, 1) 166 167add_erratum_entry cortex_x2, ERRATUM(3701772), ERRATA_X2_3701772 168 169check_erratum_ls cortex_x2, ERRATUM(3701772), CPU_REV(2, 1) 170 171workaround_reset_start cortex_x2, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 172#if IMAGE_BL31 173 /* 174 * The Cortex-X2 generic vectors are overridden to apply errata 175 * mitigation on exception entry from lower ELs. 176 */ 177 override_vector_table wa_cve_vbar_cortex_x2 178#endif /* IMAGE_BL31 */ 179workaround_reset_end cortex_x2, CVE(2022, 23960) 180 181check_erratum_chosen cortex_x2, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 182 183/* Disable hardware page aggregation. Enables mitigation for `CVE-2024-5660` */ 184workaround_reset_start cortex_x2, CVE(2024, 5660), WORKAROUND_CVE_2024_5660 185 sysreg_bit_set CORTEX_X2_CPUECTLR_EL1, BIT(46) 186workaround_reset_end cortex_x2, CVE(2024, 5660) 187 188check_erratum_ls cortex_x2, CVE(2024, 5660), CPU_REV(2, 1) 189 190 /* ---------------------------------------------------- 191 * HW will do the cache maintenance while powering down 192 * ---------------------------------------------------- 193 */ 194func cortex_x2_core_pwr_dwn 195 /* --------------------------------------------------- 196 * Enable CPU power down bit in power control register 197 * --------------------------------------------------- 198 */ 199 sysreg_bit_set CORTEX_X2_CPUPWRCTLR_EL1, CORTEX_X2_CPUPWRCTLR_EL1_CORE_PWRDN_BIT 200 201 apply_erratum cortex_x2, ERRATUM(2768515), ERRATA_X2_2768515 202 isb 203 ret 204endfunc cortex_x2_core_pwr_dwn 205 206cpu_reset_func_start cortex_x2 207 /* Disable speculative loads */ 208 msr SSBS, xzr 209 enable_mpmm 210cpu_reset_func_end cortex_x2 211 212 /* --------------------------------------------- 213 * This function provides Cortex X2 specific 214 * register information for crash reporting. 215 * It needs to return with x6 pointing to 216 * a list of register names in ascii and 217 * x8 - x15 having values of registers to be 218 * reported. 219 * --------------------------------------------- 220 */ 221.section .rodata.cortex_x2_regs, "aS" 222cortex_x2_regs: /* The ascii list of register names to be reported */ 223 .asciz "cpuectlr_el1", "" 224 225func cortex_x2_cpu_reg_dump 226 adr x6, cortex_x2_regs 227 mrs x8, CORTEX_X2_CPUECTLR_EL1 228 ret 229endfunc cortex_x2_cpu_reg_dump 230 231declare_cpu_ops cortex_x2, CORTEX_X2_MIDR, \ 232 cortex_x2_reset_func, \ 233 cortex_x2_core_pwr_dwn 234