1/* 2 * Copyright (c) 2021-2025, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <cortex_x2.h> 11#include <cpu_macros.S> 12#include <dsu_macros.S> 13#include <plat_macros.S> 14#include "wa_cve_2022_23960_bhb_vector.S" 15 16/* Hardware handled coherency */ 17#if HW_ASSISTED_COHERENCY == 0 18#error "Cortex X2 must be compiled with HW_ASSISTED_COHERENCY enabled" 19#endif 20 21/* 64-bit only core */ 22#if CTX_INCLUDE_AARCH32_REGS == 1 23#error "Cortex X2 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 24#endif 25 26.global check_erratum_cortex_x2_3701772 27 28#if WORKAROUND_CVE_2022_23960 29 wa_cve_2022_23960_bhb_vector_table CORTEX_X2_BHB_LOOP_COUNT, cortex_x2 30#endif /* WORKAROUND_CVE_2022_23960 */ 31 32cpu_reset_prologue cortex_x2 33 34workaround_reset_start cortex_x2, ERRATUM(1901946), ERRATA_X2_1901946 35 sysreg_bit_set CORTEX_X2_CPUACTLR4_EL1, BIT(15) 36workaround_reset_end cortex_x2, ERRATUM(1901946) 37 38check_erratum_range cortex_x2, ERRATUM(1901946), CPU_REV(1, 0), CPU_REV(1, 0) 39 40workaround_reset_start cortex_x2, ERRATUM(1916945), ERRATA_X2_1916945 41 sysreg_bit_set CORTEX_X2_CPUECTLR_EL1, BIT(8) 42workaround_reset_end cortex_x2, ERRATUM(1916945) 43 44check_erratum_ls cortex_x2, ERRATUM(1916945), CPU_REV(1, 0) 45 46workaround_reset_start cortex_x2, ERRATUM(1917258), ERRATA_X2_1917258 47 sysreg_bit_set CORTEX_X2_CPUACTLR4_EL1, BIT(43) 48workaround_reset_end cortex_x2, ERRATUM(1917258) 49 50check_erratum_ls cortex_x2, ERRATUM(1917258), CPU_REV(1, 0) 51 52workaround_reset_start cortex_x2, ERRATUM(1927200), ERRATA_X2_1927200 53 mov x0, #0 54 msr S3_6_C15_C8_0, x0 /* CPUPSELR_EL3 */ 55 ldr x0, =0x10E3900002 56 msr S3_6_C15_C8_2, x0 /* CPUPOR_EL3 */ 57 ldr x0, =0x10FFF00083 58 msr S3_6_C15_C8_3, x0 /* CPUPMR_EL3 */ 59 ldr x0, =0x2001003FF 60 msr S3_6_C15_C8_1, x0 /* CPUPCR_EL3 */ 61 62 mov x0, #1 63 msr S3_6_C15_C8_0, x0 /* CPUPSELR_EL3 */ 64 ldr x0, =0x10E3800082 65 msr S3_6_C15_C8_2, x0 /* CPUPOR_EL3 */ 66 ldr x0, =0x10FFF00083 67 msr S3_6_C15_C8_3, x0 /* CPUPMR_EL3 */ 68 ldr x0, =0x2001003FF 69 msr S3_6_C15_C8_1, x0 /* CPUPCR_EL3 */ 70 71 mov x0, #2 72 msr S3_6_C15_C8_0, x0 /* CPUPSELR_EL3 */ 73 ldr x0, =0x10E3800200 74 msr S3_6_C15_C8_2, x0 /* CPUPOR_EL3 */ 75 ldr x0, =0x10FFF003E0 76 msr S3_6_C15_C8_3, x0 /* CPUPMR_EL3 */ 77 ldr x0, =0x2001003FF 78 msr S3_6_C15_C8_1, x0 /* CPUPCR_EL3 */ 79workaround_reset_end cortex_x2, ERRATUM(1927200) 80 81check_erratum_ls cortex_x2, ERRATUM(1927200), CPU_REV(1, 0) 82 83workaround_reset_start cortex_x2, ERRATUM(1934260), ERRATA_X2_1934260 84 sysreg_bit_set CORTEX_X2_CPUECTLR_EL1, CORTEX_X2_CPUECTLR_EL1_WS_THR_DISABLE_ALL_BITS 85workaround_reset_end cortex_x2, ERRATUM(1934260) 86 87check_erratum_range cortex_x2, ERRATUM(1934260), CPU_REV(1, 0), CPU_REV(1, 0) 88 89workaround_reset_start cortex_x2, ERRATUM(2002765), ERRATA_X2_2002765 90 ldr x0, =0x6 91 msr S3_6_C15_C8_0, x0 /* CPUPSELR_EL3 */ 92 ldr x0, =0xF3A08002 93 msr S3_6_C15_C8_2, x0 /* CPUPOR_EL3 */ 94 ldr x0, =0xFFF0F7FE 95 msr S3_6_C15_C8_3, x0 /* CPUPMR_EL3 */ 96 ldr x0, =0x40000001003ff 97 msr S3_6_C15_C8_1, x0 /* CPUPCR_EL3 */ 98workaround_reset_end cortex_x2, ERRATUM(2002765) 99 100check_erratum_ls cortex_x2, ERRATUM(2002765), CPU_REV(2, 0) 101 102workaround_reset_start cortex_x2, ERRATUM(2017096), ERRATA_X2_2017096 103 sysreg_bit_set CORTEX_X2_CPUECTLR_EL1, CORTEX_X2_CPUECTLR_EL1_PFSTIDIS_BIT 104workaround_reset_end cortex_x2, ERRATUM(2017096) 105 106check_erratum_ls cortex_x2, ERRATUM(2017096), CPU_REV(2, 0) 107 108workaround_reset_start cortex_x2, ERRATUM(2081180), ERRATA_X2_2081180 109 /* Apply instruction patching sequence */ 110 ldr x0, =0x3 111 msr CORTEX_X2_IMP_CPUPSELR_EL3, x0 112 ldr x0, =0xF3A08002 113 msr CORTEX_X2_IMP_CPUPOR_EL3, x0 114 ldr x0, =0xFFF0F7FE 115 msr CORTEX_X2_IMP_CPUPMR_EL3, x0 116 ldr x0, =0x10002001003FF 117 msr CORTEX_X2_IMP_CPUPCR_EL3, x0 118 ldr x0, =0x4 119 msr CORTEX_X2_IMP_CPUPSELR_EL3, x0 120 ldr x0, =0xBF200000 121 msr CORTEX_X2_IMP_CPUPOR_EL3, x0 122 ldr x0, =0xFFEF0000 123 msr CORTEX_X2_IMP_CPUPMR_EL3, x0 124 ldr x0, =0x10002001003F3 125 msr CORTEX_X2_IMP_CPUPCR_EL3, x0 126workaround_reset_end cortex_x2, ERRATUM(2081180) 127 128check_erratum_ls cortex_x2, ERRATUM(2081180), CPU_REV(2, 0) 129 130workaround_reset_start cortex_x2, ERRATUM(2083908), ERRATA_X2_2083908 131 /* Apply the workaround by setting bit 13 in CPUACTLR5_EL1. */ 132 sysreg_bit_set CORTEX_X2_CPUACTLR5_EL1, BIT(13) 133workaround_reset_end cortex_x2, ERRATUM(2083908) 134 135check_erratum_range cortex_x2, ERRATUM(2083908), CPU_REV(2, 0), CPU_REV(2, 0) 136 137workaround_reset_start cortex_x2, ERRATUM(2147715), ERRATA_X2_2147715 138 /* Apply the workaround by setting bit 22 in CPUACTLR_EL1. */ 139 sysreg_bit_set CORTEX_X2_CPUACTLR_EL1, CORTEX_X2_CPUACTLR_EL1_BIT_22 140workaround_reset_end cortex_x2, ERRATUM(2147715) 141 142check_erratum_range cortex_x2, ERRATUM(2147715), CPU_REV(2, 0), CPU_REV(2, 0) 143 144workaround_reset_start cortex_x2, ERRATUM(2216384), ERRATA_X2_2216384 145 sysreg_bit_set CORTEX_X2_CPUACTLR5_EL1, CORTEX_X2_CPUACTLR5_EL1_BIT_17 146 147 /* Apply instruction patching sequence */ 148 ldr x0, =0x5 149 msr CORTEX_X2_IMP_CPUPSELR_EL3, x0 150 ldr x0, =0x10F600E000 151 msr CORTEX_X2_IMP_CPUPOR_EL3, x0 152 ldr x0, =0x10FF80E000 153 msr CORTEX_X2_IMP_CPUPMR_EL3, x0 154 ldr x0, =0x80000000003FF 155 msr CORTEX_X2_IMP_CPUPCR_EL3, x0 156workaround_reset_end cortex_x2, ERRATUM(2216384) 157 158check_erratum_ls cortex_x2, ERRATUM(2216384), CPU_REV(2, 0) 159 160workaround_reset_start cortex_x2, ERRATUM(2282622), ERRATA_X2_2282622 161 /* Apply the workaround */ 162 sysreg_bit_set CORTEX_X2_CPUACTLR2_EL1, BIT(0) 163workaround_reset_end cortex_x2, ERRATUM(2282622) 164 165check_erratum_ls cortex_x2, ERRATUM(2282622), CPU_REV(2, 1) 166 167workaround_reset_start cortex_x2, ERRATUM(2313941), ERRATA_DSU_2313941 168 errata_dsu_2313941_wa_impl 169workaround_reset_end cortex_x2, ERRATUM(2313941) 170 171check_erratum_custom_start cortex_x2, ERRATUM(2313941) 172 check_errata_dsu_2313941_impl 173 ret 174check_erratum_custom_end cortex_x2, ERRATUM(2313941) 175 176workaround_reset_start cortex_x2, ERRATUM(2371105), ERRATA_X2_2371105 177 /* Set bit 40 in CPUACTLR2_EL1 */ 178 sysreg_bit_set CORTEX_X2_CPUACTLR2_EL1, CORTEX_X2_CPUACTLR2_EL1_BIT_40 179workaround_reset_end cortex_x2, ERRATUM(2371105) 180 181check_erratum_ls cortex_x2, ERRATUM(2371105), CPU_REV(2, 0) 182 183workaround_reset_start cortex_x2, ERRATUM(2742423), ERRATA_X2_2742423 184 /* Set CPUACTLR5_EL1[56:55] to 2'b01 */ 185 sysreg_bit_set CORTEX_X2_CPUACTLR5_EL1, BIT(55) 186 sysreg_bit_clear CORTEX_X2_CPUACTLR5_EL1, BIT(56) 187workaround_reset_end cortex_x2, ERRATUM(2742423) 188 189check_erratum_ls cortex_x2, ERRATUM(2742423), CPU_REV(2, 1) 190 191workaround_runtime_start cortex_x2, ERRATUM(2768515), ERRATA_X2_2768515 192 /* dsb before isb of power down sequence */ 193 dsb sy 194workaround_runtime_end cortex_x2, ERRATUM(2768515) 195 196check_erratum_ls cortex_x2, ERRATUM(2768515), CPU_REV(2, 1) 197 198workaround_reset_start cortex_x2, ERRATUM(2778471), ERRATA_X2_2778471 199 sysreg_bit_set CORTEX_X2_CPUACTLR3_EL1, BIT(47) 200workaround_reset_end cortex_x2, ERRATUM(2778471) 201 202check_erratum_ls cortex_x2, ERRATUM(2778471), CPU_REV(2, 1) 203 204add_erratum_entry cortex_x2, ERRATUM(3701772), ERRATA_X2_3701772 205 206check_erratum_ls cortex_x2, ERRATUM(3701772), CPU_REV(2, 1) 207 208workaround_reset_start cortex_x2, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 209#if IMAGE_BL31 210 /* 211 * The Cortex-X2 generic vectors are overridden to apply errata 212 * mitigation on exception entry from lower ELs. 213 */ 214 override_vector_table wa_cve_vbar_cortex_x2 215#endif /* IMAGE_BL31 */ 216workaround_reset_end cortex_x2, CVE(2022, 23960) 217 218check_erratum_chosen cortex_x2, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 219 220/* Disable hardware page aggregation. Enables mitigation for `CVE-2024-5660` */ 221workaround_reset_start cortex_x2, CVE(2024, 5660), WORKAROUND_CVE_2024_5660 222 sysreg_bit_set CORTEX_X2_CPUECTLR_EL1, BIT(46) 223workaround_reset_end cortex_x2, CVE(2024, 5660) 224 225check_erratum_ls cortex_x2, CVE(2024, 5660), CPU_REV(2, 1) 226 227 /* ---------------------------------------------------- 228 * HW will do the cache maintenance while powering down 229 * ---------------------------------------------------- 230 */ 231func cortex_x2_core_pwr_dwn 232 /* --------------------------------------------------- 233 * Enable CPU power down bit in power control register 234 * --------------------------------------------------- 235 */ 236 sysreg_bit_set CORTEX_X2_CPUPWRCTLR_EL1, CORTEX_X2_CPUPWRCTLR_EL1_CORE_PWRDN_BIT 237 238 apply_erratum cortex_x2, ERRATUM(2768515), ERRATA_X2_2768515 239 isb 240 ret 241endfunc cortex_x2_core_pwr_dwn 242 243cpu_reset_func_start cortex_x2 244 /* Disable speculative loads */ 245 msr SSBS, xzr 246 enable_mpmm 247cpu_reset_func_end cortex_x2 248 249 /* --------------------------------------------- 250 * This function provides Cortex X2 specific 251 * register information for crash reporting. 252 * It needs to return with x6 pointing to 253 * a list of register names in ascii and 254 * x8 - x15 having values of registers to be 255 * reported. 256 * --------------------------------------------- 257 */ 258.section .rodata.cortex_x2_regs, "aS" 259cortex_x2_regs: /* The ascii list of register names to be reported */ 260 .asciz "cpuectlr_el1", "" 261 262func cortex_x2_cpu_reg_dump 263 adr x6, cortex_x2_regs 264 mrs x8, CORTEX_X2_CPUECTLR_EL1 265 ret 266endfunc cortex_x2_cpu_reg_dump 267 268declare_cpu_ops cortex_x2, CORTEX_X2_MIDR, \ 269 cortex_x2_reset_func, \ 270 cortex_x2_core_pwr_dwn 271