Merge "docs(changelog): put full name for Granule Protection Tables" into integration

fix(zynqmp): workaround issue around cntpct_el0

cntvct_el0 after power up has an architecturally UNKNOWN value.
In ZynqMP case the value is very high (e.g. 0xefffffe80d4de62d).
At best value should

fix(zynqmp): workaround issue around cntpct_el0

cntvct_el0 after power up has an architecturally UNKNOWN value.
In ZynqMP case the value is very high (e.g. 0xefffffe80d4de62d).
At best value should be 0 because it is used for time measuring when
systemd analyze command is called (via storing it in UEFI variables).
As a workaround for this issue use cntvoff_el2 to record offset from actual value which clears cntvct_el0.
There could be different way how to achieve this behavior but till that
time use this workaround to fix systemd analyze behavior.

Change-Id: Ie43096bb33bb0e02c8cac07f965610b4565e141c
Signed-off-by: Michal Simek <michal.simek@amd.com>

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fix(libc): replace true-false with explicit comparisons

This corrects the MISRA violation C2012-10.1:
This change avoids implicit conversions between standard boolean
types and integer types, ensuri

fix(libc): replace true-false with explicit comparisons

This corrects the MISRA violation C2012-10.1:
This change avoids implicit conversions between standard boolean
types and integer types, ensuring type safety and compliance.
Replaced definitions of `true` and `false` in <stdbool.h> with
explicit equality ('0'=='0') and inequality ('1'=='0') checks.

Change-Id: I507522c8be8654d830f73f32dd4ca9fe98cf0f8f
Signed-off-by: Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>

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Merge changes I1fae91a5,I54793492,I703f0e6e into integration

* changes:
fix(cpus): workaround for Cortex-A710 erratum 1917258
fix(cpus): workaround for Cortex-A710 erratum 1916945
fix(cpus): w

Merge changes I1fae91a5,I54793492,I703f0e6e into integration

* changes:
fix(cpus): workaround for Cortex-A710 erratum 1917258
fix(cpus): workaround for Cortex-A710 erratum 1916945
fix(cpus): workaround for Cortex-A710 erratum 1901946

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fix(cpus): workaround for Cortex-A710 erratum 1927200

Cortex-A710 erratum 1927200 is a Cat B erratum that applies
to revisions r0p0 and r1p0 and is fixed in r2p0.

The fix is to insert DMB ST before

fix(cpus): workaround for Cortex-A710 erratum 1927200

Cortex-A710 erratum 1927200 is a Cat B erratum that applies
to revisions r0p0 and r1p0 and is fixed in r2p0.

The fix is to insert DMB ST before acquire atomic instructions
without release semantics via instruction patching.

SDEN documentation:
https://developer.arm.com/documentation/SDEN1775101

Change-Id: I53c4aa17c1c2dc85b68f17d58f93bb1ee6b3d488
Signed-off-by: John Powell <john.powell@arm.com>

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refactor(versal2): guard handoff logic w/ build flag

Prepare for environments where the Firmware Handoff (LibTL) submodule
may not be available. Wrap all Transfer List dependent logic in `#if
TRANSF

refactor(versal2): guard handoff logic w/ build flag

Prepare for environments where the Firmware Handoff (LibTL) submodule
may not be available. Wrap all Transfer List dependent logic in `#if
TRANSFER_LIST` guards, ensuring the platform can build and run without
the submodule.

This is useful for builds not integrating the firmware handoff
mechanism.

Change-Id: Ia34bc0f4d352a3014c71eda6589c0f3e0a107ca0
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>

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refactor(qemu): guard handoff logic w/ build flag

Prepare for environments where the Firmware Handoff (LibTL)
submodule may not be available. Wrap all Transfer List dependent logic
in `#if TRANSFER

refactor(qemu): guard handoff logic w/ build flag

Prepare for environments where the Firmware Handoff (LibTL)
submodule may not be available. Wrap all Transfer List dependent logic
in `#if TRANSFER_LIST` guards, ensuring QEMU can build and run without
the submodule.

This is useful for builds not integrating the firmware handoff
mechanism.

Change-Id: I0be3773bf300b02cd3beccf738a021925e3c53c6
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>

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feat(s32g274a): move fip in a dedicated partition

Modify the deployment method for TF-A binaries on the SD card. To
simplify deployment, BL2 will be decorated with an IVT, making it a
bootable image

feat(s32g274a): move fip in a dedicated partition

Modify the deployment method for TF-A binaries on the SD card. To
simplify deployment, BL2 will be decorated with an IVT, making it a
bootable image, while fip.bin will be deployed as a raw MBR partition on
the SD card. This approach allows the FIP location to be auto-discovered
based on information found in the MBR. The partition ID where the image
is stored is set to partition zero but can be changed using the FIP_PART
makefile parameter. The GPT header cannot be used instead of MBR due to
the boot header on the S32G274A, which may overlap with the GPT reserved
area.

Change-Id: I26746023dba7788613a74ae69c86124b450e6bdb
Co-developed-by: Bogdan Roman <bogdan-gabriel.roman@nxp.com>
Signed-off-by: Bogdan Roman <bogdan-gabriel.roman@nxp.com>
Co-developed-by: Khristine Andreea Barbulescu <khristineandreea.barbulescu@nxp.com>
Signed-off-by: Khristine Andreea Barbulescu <khristineandreea.barbulescu@nxp.com>
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(s32g274ardb): initialize the IO buffer

Define and initialize the IO buffer that will be used by the uSDHC
driver to load images from the SD card.

Change-Id: I8d9712b1243a58fd6830f2682edbb9e661

feat(s32g274ardb): initialize the IO buffer

Define and initialize the IO buffer that will be used by the uSDHC
driver to load images from the SD card.

Change-Id: I8d9712b1243a58fd6830f2682edbb9e661d2f6b5
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(s32g274ardb): initialize the uSDHC driver

S32G2 and IMX share the same uSDHC controller. Therefore, it is
initialized during BL2 to facilitate the loading of subsequent boot
stages.

Change-Id:

feat(s32g274ardb): initialize the uSDHC driver

S32G2 and IMX share the same uSDHC controller. Therefore, it is
initialized during BL2 to facilitate the loading of subsequent boot
stages.

Change-Id: I223904c24a14a89ef676626b54a5937f39a17eda
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(s32g274ardb): set the system counter rate

Generic timer initialization at the BL2 stage is incomplete without
configuring the system counter frequency. This configuration is
performed by the PS

feat(s32g274ardb): set the system counter rate

Generic timer initialization at the BL2 stage is incomplete without
configuring the system counter frequency. This configuration is
performed by the PSCI layer in BL31.

Change-Id: I134cffe47819061f1608386cf98a39014cd12396
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(s32g274ardb): init the generic timer for BL2

The generic timer must be initialized during BL2 because the uSDHC
driver, which will be enabled in subsequent commits, requires it for
delays.

Cha

feat(s32g274ardb): init the generic timer for BL2

The generic timer must be initialized during BL2 because the uSDHC
driver, which will be enabled in subsequent commits, requires it for
delays.

Change-Id: Ia09b3d3565a09ace7389d2e063af1185cc80fa27
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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fix(nxp-mmc): handle response for CMD0

Fixed a regression introduced by commit
a59d43fc222d ("refactor(nxp-mmc): populate command transfer type").

The commit incorrectly assumes that all commands w

fix(nxp-mmc): handle response for CMD0

Fixed a regression introduced by commit
a59d43fc222d ("refactor(nxp-mmc): populate command transfer type").

The commit incorrectly assumes that all commands will have a response
type, which is not always the case. For instance, Command 0 (used to
reset the card and enter idle state) does not expect a response. As a
result, the response type field will be explicitly set to zero in
such cases.

Change-Id: Id97b765b9720bbd02fafb30a271f134536fab5a6
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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refactor(mmc): replace 0 with MMC_RESPONSE_NONE

Use the newly introduced MMC_RESPONSE_NONE macro for Command 0,
where no response is expected.

Change-Id: I861a1bd009ea131677a23e2d94ea27bff3653360
S

refactor(mmc): replace 0 with MMC_RESPONSE_NONE

Use the newly introduced MMC_RESPONSE_NONE macro for Command 0,
where no response is expected.

Change-Id: I861a1bd009ea131677a23e2d94ea27bff3653360
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(mmc): add define for no response

Introduce a new macro definition to represent the response type for
commands that do not expect a response. This is particularly applicable
to commands like Com

feat(mmc): add define for no response

Introduce a new macro definition to represent the response type for
commands that do not expect a response. This is particularly applicable
to commands like Command 0, which is used to reset the card and place it
into the idle state.

Change-Id: I6fe298504a7166ccd7e47c23f88945b2ce064cf9
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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Merge changes I2af839ae,Ifd0c7b4e,I56763cb4,I93aec580,Icbd43503, ... into integration

* changes:
docs(fvp): add GICv5 build instructions and limitations
feat(fvp): add GICv5 support
feat(gicv5

Merge changes I2af839ae,Ifd0c7b4e,I56763cb4,I93aec580,Icbd43503, ... into integration

* changes:
docs(fvp): add GICv5 build instructions and limitations
feat(fvp): add GICv5 support
feat(gicv5): probe components
feat(gicv5): initialise the IWB
feat(gicv5): initialise the IRS
feat(gicv5): assign interrupt sources to appropriate security states
feat(gicv5): add a barebones GICv5 driver
feat(gicv5): add support for building with gicv5

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docs(fvp): add GICv5 build instructions and limitations

Add documentation for enabling GICv5 support in the FVP platform,
including required build options and guidance on usage. Also document
curren

docs(fvp): add GICv5 build instructions and limitations

Add documentation for enabling GICv5 support in the FVP platform,
including required build options and guidance on usage. Also document
current limitations and known constraints.

Introduce build-time checks to ensure incompatible configurations
(e.g., with SPMD or RMMD) fail early with a clear error message.

Initial GICv5 support in FVP is intended to facilitate early Linux
kernel bring-up and to assist with upstream kernel patch development.

Note: This patch is a temporary measure and should be reverted once
proper and complete GICv5 support is upstreamed in TF-A.

Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: I2af839aec600040dfde75d74d02eff5a57ecda4e

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feat(fvp): add GICv5 support

Factors out GICv3 specific code and replace it with GICv5. This can be
selected with FVP_USE_GIC_DRIVER=FVP_GICV5. Specifically, the FCONF
logic does not apply to GICv5

feat(fvp): add GICv5 support

Factors out GICv3 specific code and replace it with GICv5. This can be
selected with FVP_USE_GIC_DRIVER=FVP_GICV5. Specifically, the FCONF
logic does not apply to GICv5 as the bindings are completely different.

This patch does not include a device tree. This will be added at a later
date.

Change-Id: Ifd0c7b4e0bc2ea1e53a6779ab4c50c4aec39dafb
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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feat(gicv5): probe components

Asserts that the platform configuration is correct. No dynamic
discovery so only done in debug builds.

Change-Id: I56763cb422dcaa4a816a619ab4acfc6946427c64
Signed-off-

feat(gicv5): probe components

Asserts that the platform configuration is correct. No dynamic
discovery so only done in debug builds.

Change-Id: I56763cb422dcaa4a816a619ab4acfc6946427c64
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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feat(gicv5): initialise the IWB

Same idea as the IRS - do IWB initialisation that's only accessible from
EL3 when it is the MPPAS. Relies on the platform to provide wire domain
assignments and trig

feat(gicv5): initialise the IWB

Same idea as the IRS - do IWB initialisation that's only accessible from
EL3 when it is the MPPAS. Relies on the platform to provide wire domain
assignments and triggers as well as to map the config frame in device
nGnRnE memory. All wires will default to the NS domain and the platform
can override this.

Change-Id: I93aec5809aec4328d1cba832c2c6e5891e398e5b
Co-developed-by: Sascha Bischoff <sascha.bischoff@arm.com>
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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feat(gicv5): initialise the IRS

Do IRS initialisation that's only accessible from the EL3 interrupt
domain. Relies on the platform to provide SPI domain assignments and
trigger modes as well as to m

feat(gicv5): initialise the IRS

Do IRS initialisation that's only accessible from the EL3 interrupt
domain. Relies on the platform to provide SPI domain assignments and
trigger modes as well as to map the config frame in device nGnRnE
memory. All wires will default to NS and the platform may override this.

Change-Id: Icbd43503753cd76fd3d80ed47eba6926494bc323
Co-developed-by: Sascha Bischoff <sascha.bischoff@arm.com>
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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feat(gicv5): assign interrupt sources to appropriate security states

Assign the PPI interrupts we commonly have in the device tree to the NS
domain. This is a short-term solution that allows Linux t

feat(gicv5): assign interrupt sources to appropriate security states

Assign the PPI interrupts we commonly have in the device tree to the NS
domain. This is a short-term solution that allows Linux to fully boot.
This is expected to be fully replaced with context management when
adding world switching support as some of these are expected to be
shared between worlds.

Change-Id: I59a7b5a63f878c9a717ef81e977be7133a402f3f
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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feat(locks): add non-blocking spinlock_try() API

Add a non-blocking `spin_trylock()` function to the existing spinlock
implementation. This API attempts to acquire the lock and returns `1`
on succes

feat(locks): add non-blocking spinlock_try() API

Add a non-blocking `spin_trylock()` function to the existing spinlock
implementation. This API attempts to acquire the lock and returns `1`
on success or `0` if the lock is already held. It enables conditional
locking scenarios where blocking is undesirable.

Change-Id: I9483206952d1a34dc245ebf69e80c3645b658946
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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Merge "fix(fvp): workaround when PCIe 2 region is not present in DTB" into integration

feat(gicv5): add a barebones GICv5 driver

This is the absolute minimum that's needed to compile an NS-only build
end exit out of EL3. The GIC is not used and/or configured in any way
but all the nec

feat(gicv5): add a barebones GICv5 driver

This is the absolute minimum that's needed to compile an NS-only build
end exit out of EL3. The GIC is not used and/or configured in any way
but all the necessary hooks are populated.

Notably, SCR_EL3.FIQ becomes RES1 as GICv5 behaves in a similar manner
to a GICv3 with FIQ set.

Change-Id: Idae52b9df97f4ca2996b2dcd1e5efc45478a43f2
Co-developed-by: Achin Gupta <achin.gupta@arm.com>
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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