1 /* 2 * Copyright (c) 2015-2025, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <drivers/arm/css/sds.h> 8 #include <lib/smccc.h> 9 #include <lib/utils_def.h> 10 #include <services/arm_arch_svc.h> 11 12 #include <plat/arm/common/plat_arm.h> 13 #include <platform_def.h> 14 15 /* 16 * Table of memory regions for different BL stages to map using the MMU. 17 * This doesn't include Trusted SRAM as setup_page_tables() already takes care 18 * of mapping it. 19 */ 20 #ifdef IMAGE_BL1 21 const mmap_region_t plat_arm_mmap[] = { 22 ARM_MAP_SHARED_RAM, 23 V2M_MAP_FLASH0_RW, 24 V2M_MAP_IOFPGA, 25 CSS_MAP_DEVICE, 26 SOC_CSS_MAP_DEVICE, 27 #if TRUSTED_BOARD_BOOT 28 /* Map DRAM to authenticate NS_BL2U image. */ 29 ARM_MAP_NS_DRAM1, 30 #endif 31 {0} 32 }; 33 #endif 34 #ifdef IMAGE_BL2 35 const mmap_region_t plat_arm_mmap[] = { 36 ARM_MAP_SHARED_RAM, 37 V2M_MAP_FLASH0_RW, 38 #ifdef PLAT_ARM_MEM_PROT_ADDR 39 ARM_V2M_MAP_MEM_PROTECT, 40 #endif 41 V2M_MAP_IOFPGA, 42 CSS_MAP_DEVICE, 43 SOC_CSS_MAP_DEVICE, 44 ARM_MAP_NS_DRAM1, 45 #ifdef __aarch64__ 46 ARM_MAP_DRAM2, 47 #endif 48 #ifdef SPD_tspd 49 ARM_MAP_TSP_SEC_MEM, 50 #endif 51 #ifdef SPD_opteed 52 ARM_MAP_OPTEE_CORE_MEM, 53 ARM_OPTEE_PAGEABLE_LOAD_MEM, 54 #endif 55 #if TRUSTED_BOARD_BOOT && !RESET_TO_BL2 56 ARM_MAP_BL1_RW, 57 #endif 58 #ifdef JUNO_ETHOSN_TZMP1 59 JUNO_ETHOSN_PROT_FW_RW, 60 #endif 61 #if SPMC_AT_EL3 62 ARM_SP_IMAGE_MMAP, 63 #endif 64 {0} 65 }; 66 #endif 67 #ifdef IMAGE_BL2U 68 const mmap_region_t plat_arm_mmap[] = { 69 ARM_MAP_SHARED_RAM, 70 CSS_MAP_DEVICE, 71 CSS_MAP_SCP_BL2U, 72 V2M_MAP_IOFPGA, 73 SOC_CSS_MAP_DEVICE, 74 {0} 75 }; 76 #endif 77 #ifdef IMAGE_BL31 78 const mmap_region_t plat_arm_mmap[] = { 79 ARM_MAP_SHARED_RAM, 80 V2M_MAP_IOFPGA, 81 CSS_MAP_DEVICE, 82 #ifdef PLAT_ARM_MEM_PROT_ADDR 83 ARM_V2M_MAP_MEM_PROTECT, 84 #endif 85 SOC_CSS_MAP_DEVICE, 86 ARM_DTB_DRAM_NS, 87 #ifdef JUNO_ETHOSN_TZMP1 88 JUNO_ETHOSN_PROT_FW_RO, 89 #endif 90 #ifdef JUNO_MAP_FW_NS_HANDOFF 91 JUNO_MAP_FW_NS_HANDOFF, 92 #endif 93 #if defined(JUNO_MAP_EL3_FW_HANDOFF) && !RESET_TO_BL31 94 JUNO_MAP_EL3_FW_HANDOFF, 95 #endif 96 {0} 97 }; 98 #endif 99 #ifdef IMAGE_BL32 100 const mmap_region_t plat_arm_mmap[] = { 101 #ifndef __aarch64__ 102 ARM_MAP_SHARED_RAM, 103 #ifdef PLAT_ARM_MEM_PROT_ADDR 104 ARM_V2M_MAP_MEM_PROTECT, 105 #endif 106 #endif 107 V2M_MAP_IOFPGA, 108 CSS_MAP_DEVICE, 109 SOC_CSS_MAP_DEVICE, 110 {0} 111 }; 112 #endif 113 114 ARM_CASSERT_MMAP 115 116 /***************************************************************************** 117 * plat_is_smccc_feature_available() - This function checks whether SMCCC 118 * feature is availabile for platform. 119 * @fid: SMCCC function id 120 * 121 * Return SMC_ARCH_CALL_SUCCESS if SMCCC feature is available and 122 * SMC_ARCH_CALL_NOT_SUPPORTED otherwise. 123 *****************************************************************************/ 124 int32_t plat_is_smccc_feature_available(u_register_t fid) 125 { 126 switch (fid) { 127 case SMCCC_ARCH_SOC_ID: 128 return SMC_ARCH_CALL_SUCCESS; 129 default: 130 return SMC_ARCH_CALL_NOT_SUPPORTED; 131 } 132 } 133 134 /* Get SOC version */ 135 int32_t plat_get_soc_version(void) 136 { 137 return (int32_t) 138 (SOC_ID_SET_JEP_106(ARM_SOC_CONTINUATION_CODE, 139 ARM_SOC_IDENTIFICATION_CODE) | 140 (JUNO_SOC_ID & SOC_ID_IMPL_DEF_MASK)); 141 } 142 143 /* Get SOC revision */ 144 int32_t plat_get_soc_revision(void) 145 { 146 unsigned int sys_id; 147 148 sys_id = mmio_read_32(V2M_SYSREGS_BASE + V2M_SYS_ID); 149 return (int32_t)(((sys_id >> V2M_SYS_ID_REV_SHIFT) & 150 V2M_SYS_ID_REV_MASK) & SOC_ID_REV_MASK); 151 } 152 153 #if CSS_USE_SCMI_SDS_DRIVER 154 static sds_region_desc_t juno_sds_regions[] = { 155 { .base = PLAT_ARM_SDS_MEM_BASE }, 156 }; 157 158 sds_region_desc_t *plat_sds_get_regions(unsigned int *region_count) 159 { 160 *region_count = ARRAY_SIZE(juno_sds_regions); 161 162 return juno_sds_regions; 163 } 164 #endif /* CSS_USE_SCMI_SDS_DRIVER */ 165