1 /* 2 * Copyright (c) 2019-2023, Intel Corporation. All rights reserved. 3 Copyright (c) 2024-2025, Altera Corporation. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #ifndef SOCFPGA_RESETMANAGER_H 9 #define SOCFPGA_RESETMANAGER_H 10 11 #include "socfpga_plat_def.h" 12 13 /* Status Response */ 14 #define RSTMGR_RET_OK 0 15 #define RSTMGR_RET_ERROR -1 16 17 #define SOCFPGA_BRIDGE_ENABLE BIT(0) 18 #define SOCFPGA_BRIDGE_HAS_MASK BIT(1) 19 20 #define SOC2FPGA_MASK (1<<0) 21 #define LWHPS2FPGA_MASK (1<<1) 22 #define FPGA2SOC_MASK (1<<2) 23 #define F2SDRAM0_MASK (1<<3) 24 #define F2SDRAM1_MASK (1<<4) 25 #define F2SDRAM2_MASK (1<<5) 26 27 /* Register Mapping */ 28 29 #define SOCFPGA_RSTMGR_STAT 0x000 30 #define SOCFPGA_RSTMGR_MISCSTAT 0x008 31 #define SOCFPGA_RSTMGR_HDSKEN 0x010 32 #define SOCFPGA_RSTMGR_HDSKREQ 0x014 33 #define SOCFPGA_RSTMGR_HDSKACK 0x018 34 #define SOCFPGA_RSTMGR_HDSKSTALL 0x01C 35 #if PLATFORM_MODEL != PLAT_SOCFPGA_AGILEX5 36 #define SOCFPGA_RSTMGR_MPUMODRST 0x020 37 #endif 38 #define SOCFPGA_RSTMGR_PER0MODRST 0x024 39 #define SOCFPGA_RSTMGR_PER1MODRST 0x028 40 #define SOCFPGA_RSTMGR_BRGMODRST 0x02C 41 #if PLATFORM_MODEL != PLAT_SOCFPGA_AGILEX5 42 #define SOCFPGA_RSTMGR_COLDMODRST 0x034 43 #endif 44 #define SOCFPGA_RSTMGR_DBGMODRST 0x03C 45 #define SOCFPGA_RSTMGR_BRGWARMMASK 0x04C 46 #define SOCFPGA_RSTMGR_TSTSTA 0x05C 47 #define SOCFPGA_RSTMGR_HDSKTIMEOUT 0x064 48 #define SOCFPGA_RSTMGR_DBGHDSKTIMEOUT 0x06C 49 #define SOCFPGA_RSTMGR_DBGRSTCMPLT 0x070 50 #define SOCFPGA_RSTMGR_HPSRSTCMPLT 0x080 51 #define SOCFPGA_RSTMGR_CPUINREST 0x090 52 #define SOCFPGA_RSTMGR_CPURSTRELEASE 0x094 53 #define SOCFPGA_RSTMGR_CPUBASELOW_0 0x098 54 #define SOCFPGA_RSTMGR_CPUBASEHIGH_0 0x09C 55 #define SOCFPGA_RSTMGR_CPUBASELOW_1 0x0A0 56 #define SOCFPGA_RSTMGR_CPUBASEHIGH_1 0x0A4 57 #define SOCFPGA_RSTMGR_CPUBASELOW_2 0x0A8 58 #define SOCFPGA_RSTMGR_CPUBASEHIGH_2 0x0AC 59 #define SOCFPGA_RSTMGR_CPUBASELOW_3 0x0B0 60 #define SOCFPGA_RSTMGR_CPUBASEHIGH_3 0x0B4 61 62 /* Field Mapping */ 63 /* PER0MODRST */ 64 #define RSTMGR_PER0MODRST_EMAC0 0x00000001 //TSN0 65 #define RSTMGR_PER0MODRST_EMAC1 0x00000002 //TSN1 66 #define RSTMGR_PER0MODRST_EMAC2 0x00000004 //TSN2 67 #define RSTMGR_PER0MODRST_USB0 0x00000008 68 #define RSTMGR_PER0MODRST_USB1 0x00000010 69 #define RSTMGR_PER0MODRST_NAND 0x00000020 70 #define RSTMGR_PER0MODRST_SOFTPHY 0x00000040 71 #define RSTMGR_PER0MODRST_SDMMC 0x00000080 72 #define RSTMGR_PER0MODRST_EMAC0OCP 0x00000100 //TSN0ECC 73 #define RSTMGR_PER0MODRST_EMAC1OCP 0x00000200 //TSN1ECC 74 #define RSTMGR_PER0MODRST_EMAC2OCP 0x00000400 //TSN2ECC 75 #define RSTMGR_PER0MODRST_USB0OCP 0x00000800 76 #define RSTMGR_PER0MODRST_USB1OCP 0x00001000 77 #define RSTMGR_PER0MODRST_NANDOCP 0x00002000 78 #define RSTMGR_PER0MODRST_SDMMCOCP 0x00008000 79 #define RSTMGR_PER0MODRST_DMA 0x00010000 80 #define RSTMGR_PER0MODRST_SPIM0 0x00020000 81 #define RSTMGR_PER0MODRST_SPIM1 0x00040000 82 #define RSTMGR_PER0MODRST_SPIS0 0x00080000 83 #define RSTMGR_PER0MODRST_SPIS1 0x00100000 84 #define RSTMGR_PER0MODRST_DMAOCP 0x00200000 85 #define RSTMGR_PER0MODRST_EMACPTP 0x00400000 86 #define RSTMGR_PER0MODRST_DMAIF0 0x01000000 87 #define RSTMGR_PER0MODRST_DMAIF1 0x02000000 88 #define RSTMGR_PER0MODRST_DMAIF2 0x04000000 89 #define RSTMGR_PER0MODRST_DMAIF3 0x08000000 90 #define RSTMGR_PER0MODRST_DMAIF4 0x10000000 91 #define RSTMGR_PER0MODRST_DMAIF5 0x20000000 92 #define RSTMGR_PER0MODRST_DMAIF6 0x40000000 93 #define RSTMGR_PER0MODRST_DMAIF7 0x80000000 94 95 /* PER1MODRST */ 96 #define RSTMGR_PER1MODRST_WATCHDOG0 0x00000001 97 #define RSTMGR_PER1MODRST_WATCHDOG1 0x00000002 98 #define RSTMGR_PER1MODRST_WATCHDOG2 0x00000004 99 #define RSTMGR_PER1MODRST_WATCHDOG3 0x00000008 100 #define RSTMGR_PER1MODRST_L4SYSTIMER0 0x00000010 101 #define RSTMGR_PER1MODRST_L4SYSTIMER1 0x00000020 102 #define RSTMGR_PER1MODRST_SPTIMER0 0x00000040 103 #define RSTMGR_PER1MODRST_SPTIMER1 0x00000080 104 #define RSTMGR_PER1MODRST_I2C0 0x00000100 105 #define RSTMGR_PER1MODRST_I2C1 0x00000200 106 #define RSTMGR_PER1MODRST_I2C2 0x00000400 107 #define RSTMGR_PER1MODRST_I2C3 0x00000800 108 #define RSTMGR_PER1MODRST_I2C4 0x00001000 109 #define RSTMGR_PER1MODRST_I3C0 0x00002000 110 #define RSTMGR_PER1MODRST_I3C1 0x00004000 111 #define RSTMGR_PER1MODRST_UART0 0x00010000 112 #define RSTMGR_PER1MODRST_UART1 0x00020000 113 #define RSTMGR_PER1MODRST_GPIO0 0x01000000 114 #define RSTMGR_PER1MODRST_GPIO1 0x02000000 115 #define RSTMGR_PER1MODRST_WATCHDOG4 0x04000000 116 117 /* HDSKEN */ 118 #define RSTMGR_HDSKEN_EMIF_FLUSH 0x00000001 119 #define RSTMGR_HDSKEN_FPGAHSEN 0x00000004 120 #define RSTMGR_HDSKEN_ETRSTALLEN 0x00000008 121 #define RSTMGR_HDSKEN_LWS2F_FLUSH 0x00000200 122 #define RSTMGR_HDSKEN_S2F_FLUSH 0x00000400 123 #define RSTMGR_HDSKEN_F2SDRAM_FLUSH 0x00000800 124 #define RSTMGR_HDSKEN_F2S_FLUSH 0x00001000 125 #define RSTMGR_HDSKEN_L3NOC_DBG 0x00010000 126 #define RSTMGR_HDSKEN_DEBUG_L3NOC 0x00020000 127 128 /* HDSKREQ */ 129 #define RSTMGR_HDSKREQ_EMIFFLUSHREQ 0x00000001 130 #define RSTMGR_HDSKREQ_ETRSTALLREQ 0x00000008 131 #define RSTMGR_HDSKREQ_LWS2F_FLUSH 0x00000200 132 #define RSTMGR_HDSKREQ_S2F_FLUSH 0x00000400 133 #define RSTMGR_HDSKREQ_F2SDRAM_FLUSH 0x00000800 134 #define RSTMGR_HDSKREQ_F2S_FLUSH 0x00001000 135 #define RSTMGR_HDSKREQ_L3NOC_DBG 0x00010000 136 #define RSTMGR_HDSKREQ_DEBUG_L3NOC 0x00020000 137 #define RSTMGR_HDSKREQ_FPGAHSREQ 0x00000004 138 #define RSTMGR_HDSKREQ_LWSOC2FPGAREQ 0x00000200 139 #define RSTMGR_HDSKREQ_SOC2FPGAREQ 0x00000400 140 #define RSTMGR_HDSKREQ_F2SDRAM0REQ 0x00000800 141 #define RSTMGR_HDSKREQ_FPGA2SOCREQ 0x00001000 142 143 /* HDSKACK */ 144 #define RSTMGR_HDSKACK_EMIFFLUSHREQ 0x00000001 145 #define RSTMGR_HDSKACK_FPGAHSREQ 0x00000004 146 #define RSTMGR_HDSKACK_ETRSTALLREQ 0x00000008 147 #define RSTMGR_HDSKACK_LWS2F_FLUSH 0x00000200 148 #define RSTMGR_HDSKACK_S2F_FLUSH 0x00000400 149 #define RSTMGR_HDSKACK_F2SDRAM_FLUSH 0x00000800 150 #define RSTMGR_HDSKACK_F2S_FLUSH 0x00001000 151 #define RSTMGR_HDSKACK_L3NOC_DBG 0x00010000 152 #define RSTMGR_HDSKACK_DEBUG_L3NOC 0x00020000 153 #define RSTMGR_HDSKACK_FPGAHSACK 0x00000004 154 #define RSTMGR_HDSKACK_LWSOC2FPGAACK 0x00000200 155 #define RSTMGR_HDSKACK_SOC2FPGAACK 0x00000400 156 #define RSTMGR_HDSKACK_F2SDRAM0ACK 0x00000800 157 #define RSTMGR_HDSKACK_FPGA2SOCACK 0x00001000 158 #define RSTMGR_HDSKACK_FPGAHSACK_DASRT 0x00000000 159 #define RSTMGR_HDSKACK_LWSOC2FPGAACK_DASRT 0x00000000 160 #define RSTMGR_HDSKACK_SOC2FPGAACK_DASRT 0x00000000 161 #define RSTMGR_HDSKACK_F2SDRAM0ACK_DASRT 0x00000000 162 #define RSTMGR_HDSKACK_FPGA2SOCACK_DASRT 0x00000000 163 164 /* HDSKSTALL */ 165 #define RSTMGR_HDSKACK_ETRSTALLWARMRST 0x00000001 166 167 /* BRGMODRST */ 168 #define RSTMGR_BRGMODRST_SOC2FPGA 0x00000001 169 #define RSTMGR_BRGMODRST_LWHPS2FPGA 0x00000002 170 #define RSTMGR_BRGMODRST_FPGA2SOC 0x00000004 171 #define RSTMGR_BRGMODRST_F2SSDRAM0 0x00000008 172 #if PLATFORM_MODEL == PLAT_SOCFPGA_STRATIX10 173 #define RSTMGR_BRGMODRST_F2SSDRAM1 0x10 174 #define RSTMGR_BRGMODRST_F2SSDRAM2 0x20 175 #define RSTMGR_BRGMODRST_DDRSCH 0x40 176 #elif PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5 177 #define RSTMGR_BRGMODRST_F2SSDRAM1 0x10 178 #define RSTMGR_BRGMODRST_F2SSDRAM2 0x20 179 #endif 180 181 #define RSTMGR_BRGMODRST_MPFE 0x40 182 183 /* DBGMODRST */ 184 #define RSTMGR_DBGMODRST_DBG_RST 0x00000001 185 186 /* BRGMODRSTMASK */ 187 #define RSTMGR_BRGMODRSTMASK_SOC2FPGA 0x00000001 188 #define RSTMGR_BRGMODRSTMASK_LWHPS2FPGA 0x00000002 189 #define RSTMGR_BRGMODRSTMASK_FPGA2SOC 0x00000004 190 #define RSTMGR_BRGMODRSTMASK_F2SDRAM0 0x00000008 191 #define RSTMGR_BRGMODRSTMASK_MPFE 0x00000040 192 193 /* TSTSTA */ 194 #define RSTMGR_TSTSTA_RSTST 0x0000001F 195 196 /* HDSKTIMEOUT */ 197 #define RSTMGR_HDSKTIMEOUT_VAL 0xFFFFFFFF 198 199 /* DBGHDSKTIMEOUT */ 200 #define RSTMGR_DBGHDSKTIMEOUT_VAL 0xFFFFFFFF 201 202 /* DBGRSTCMPLT */ 203 #define RSTMGR_DBGRSTCMPLT_VAL 0xFFFFFFFF 204 205 /* HPSRSTCMPLT */ 206 #define RSTMGR_DBGRSTCMPLT_VAL 0xFFFFFFFF 207 208 /* CPUINRESET */ 209 #define RSTMGR_CPUINRESET_CPU0 0x00000001 210 #define RSTMGR_CPUINRESET_CPU1 0x00000002 211 #define RSTMGR_CPUINRESET_CPU2 0x00000004 212 #define RSTMGR_CPUINRESET_CPU3 0x00000008 213 214 /* CPUSTRELEASE */ 215 #define RSTMGR_CPUSTRELEASE_CPUx 0x10D11094 216 217 /* CPUxRESETBASE */ 218 #define RSTMGR_CPUxRESETBASELOW_CPU0 0x10D11098 219 #define RSTMGR_CPUxRESETBASEHIGH_CPU0 0x10D1109C 220 #define RSTMGR_CPUxRESETBASELOW_CPU1 0x10D110A0 221 #define RSTMGR_CPUxRESETBASEHIGH_CPU1 0x10D110A4 222 #define RSTMGR_CPUxRESETBASELOW_CPU2 0x10D110A8 223 #define RSTMGR_CPUxRESETBASEHIGH_CPU2 0x10D110AC 224 #define RSTMGR_CPUxRESETBASELOW_CPU3 0x10D110B0 225 #define RSTMGR_CPUxRESETBASEHIGH_CPU3 0x10D110B4 226 227 /* Definitions */ 228 229 #define RSTMGR_L2_MODRST 0x0100 230 #define RSTMGR_HDSKEN_SET 0x010D 231 232 /* Macros */ 233 #define SOCFPGA_RSTMGR(_reg) (SOCFPGA_RSTMGR_REG_BASE + (SOCFPGA_RSTMGR_##_reg)) 234 #define RSTMGR_FIELD(_reg, _field) (RSTMGR_##_reg##MODRST_##_field) 235 236 /* Reset type to SDM from PSCI */ 237 // Temp add macro here for reset type 238 #define SOCFPGA_RESET_TYPE_COLD 0 239 #define SOCFPGA_RESET_TYPE_WARM 1 240 241 /* Function Declarations */ 242 243 void deassert_peripheral_reset(void); 244 void config_hps_hs_before_warm_reset(void); 245 246 int socfpga_bridges_reset(uint32_t mask); 247 int socfpga_bridges_enable(uint32_t mask); 248 int socfpga_bridges_disable(uint32_t mask); 249 250 int socfpga_cpurstrelease(unsigned int cpu_id); 251 int socfpga_cpu_reset_base(unsigned int cpu_id); 252 253 /* SMP: Func proto */ 254 void bl31_plat_set_secondary_cpu_entrypoint(unsigned int cpu_id); 255 void bl31_plat_set_secondary_cpu_off(void); 256 void bl31_plat_reset_secondary_cpu(unsigned int cpu_id); 257 258 #endif /* SOCFPGA_RESETMANAGER_H */ 259