1/* 2 * Copyright (c) 2022-2025, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <cortex_x4.h> 11#include <cpu_macros.S> 12#include <dsu_macros.S> 13#include <plat_macros.S> 14#include "wa_cve_2022_23960_bhb_vector.S" 15 16/* Hardware handled coherency */ 17#if HW_ASSISTED_COHERENCY == 0 18#error "Cortex X4 must be compiled with HW_ASSISTED_COHERENCY enabled" 19#endif 20 21/* 64-bit only core */ 22#if CTX_INCLUDE_AARCH32_REGS == 1 23#error "Cortex X4 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 24#endif 25 26cpu_reset_prologue cortex_x4 27 28.global check_erratum_cortex_x4_2726228 29.global check_erratum_cortex_x4_3701758 30 31#if WORKAROUND_CVE_2022_23960 32 wa_cve_2022_23960_bhb_vector_table CORTEX_X4_BHB_LOOP_COUNT, cortex_x4 33#endif /* WORKAROUND_CVE_2022_23960 */ 34 35add_erratum_entry cortex_x4, ERRATUM(2726228), ERRATA_X4_2726228 36 37check_erratum_ls cortex_x4, ERRATUM(2726228), CPU_REV(0, 1) 38 39workaround_runtime_start cortex_x4, ERRATUM(2740089), ERRATA_X4_2740089 40 /* dsb before isb of power down sequence */ 41 dsb sy 42workaround_runtime_end cortex_x4, ERRATUM(2740089) 43 44check_erratum_ls cortex_x4, ERRATUM(2740089), CPU_REV(0, 1) 45 46workaround_reset_start cortex_x4, ERRATUM(2763018), ERRATA_X4_2763018 47 sysreg_bit_set CORTEX_X4_CPUACTLR3_EL1, BIT(47) 48workaround_reset_end cortex_x4, ERRATUM(2763018) 49 50check_erratum_ls cortex_x4, ERRATUM(2763018), CPU_REV(0, 1) 51 52workaround_reset_start cortex_x4, ERRATUM(2816013), ERRATA_X4_2816013 53 mrs x1, id_aa64pfr1_el1 54 ubfx x2, x1, ID_AA64PFR1_EL1_MTE_SHIFT, #4 55 cbz x2, #1f 56 sysreg_bit_set CORTEX_X4_CPUACTLR5_EL1, BIT(14) 571: 58workaround_reset_end cortex_x4, ERRATUM(2816013) 59 60check_erratum_ls cortex_x4, ERRATUM(2816013), CPU_REV(0, 1) 61 62workaround_reset_start cortex_x4, ERRATUM(2897503), ERRATA_X4_2897503 63 sysreg_bit_set CORTEX_X4_CPUACTLR4_EL1, BIT(8) 64workaround_reset_end cortex_x4, ERRATUM(2897503) 65 66check_erratum_ls cortex_x4, ERRATUM(2897503), CPU_REV(0, 1) 67 68workaround_reset_start cortex_x4, ERRATUM(2900952), ERRATA_DSU_2900952 69 errata_dsu_2900952_wa_apply 70workaround_reset_end cortex_x4, ERRATUM(2900952) 71 72check_erratum_custom_start cortex_x4, ERRATUM(2900952) 73 check_errata_dsu_2900952_applies 74 ret 75check_erratum_custom_end cortex_x4, ERRATUM(2900952) 76 77workaround_reset_start cortex_x4, ERRATUM(2923985), ERRATA_X4_2923985 78 sysreg_bit_set CORTEX_X4_CPUACTLR4_EL1, (BIT(11) | BIT(10)) 79workaround_reset_end cortex_x4, ERRATUM(2923985) 80 81check_erratum_ls cortex_x4, ERRATUM(2923985), CPU_REV(0, 1) 82 83workaround_reset_start cortex_x4, ERRATUM(2957258), ERRATA_X4_2957258 84 /* Add ISB before MRS reads of MPIDR_EL1/MIDR_EL1 */ 85 ldr x0, =0x1 86 msr S3_6_c15_c8_0, x0 /* msr CPUPSELR_EL3, X0 */ 87 ldr x0, =0xd5380000 88 msr S3_6_c15_c8_2, x0 /* msr CPUPOR_EL3, X0 */ 89 ldr x0, =0xFFFFFF40 90 msr S3_6_c15_c8_3,x0 /* msr CPUPMR_EL3, X0 */ 91 ldr x0, =0x000080010033f 92 msr S3_6_c15_c8_1, x0 /* msr CPUPCR_EL3, X0 */ 93 isb 94workaround_reset_end cortex_x4, ERRATUM(2957258) 95 96check_erratum_ls cortex_x4, ERRATUM(2957258), CPU_REV(0, 1) 97 98workaround_reset_start cortex_x4, ERRATUM(3076789), ERRATA_X4_3076789 99 sysreg_bit_set CORTEX_X4_CPUACTLR3_EL1, BIT(14) 100 sysreg_bit_set CORTEX_X4_CPUACTLR3_EL1, BIT(13) 101 sysreg_bit_set CORTEX_X4_CPUACTLR_EL1, BIT(52) 102workaround_reset_end cortex_x4, ERRATUM(3076789) 103 104check_erratum_ls cortex_x4, ERRATUM(3076789), CPU_REV(0, 1) 105 106workaround_reset_start cortex_x4, ERRATUM(3133195), ERRATA_X4_3133195 107 ldr x0,=0x2 108 msr s3_6_c15_c8_0,x0 /* msr cpupselr_el3, x0 */ 109 ldr x0,=0xd503225f 110 msr s3_6_c15_c8_2,x0 /* msr cpupor_el3, x0 */ 111 ldr x0,=0xffffffff 112 msr s3_6_c15_c8_3,x0 /* msr cpupmr_el3, x0 */ 113 ldr x0,=0x00000000404003fd 114 msr s3_6_c15_c8_1,x0 /* msr cpupcr_el3, x0 */ 115workaround_reset_end cortex_x4, ERRATUM(3133195) 116 117check_erratum_range cortex_x4, ERRATUM(3133195), CPU_REV(0, 2), CPU_REV(0, 2) 118 119add_erratum_entry cortex_x4, ERRATUM(3701758), ERRATA_X4_3701758 120 121check_erratum_ls cortex_x4, ERRATUM(3701758), CPU_REV(0, 3) 122 123workaround_reset_start cortex_x4, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 124#if IMAGE_BL31 125 /* 126 * The Cortex X4 generic vectors are overridden to apply errata 127 * mitigation on exception entry from lower ELs. 128 */ 129 override_vector_table wa_cve_vbar_cortex_x4 130#endif /* IMAGE_BL31 */ 131workaround_reset_end cortex_x4, CVE(2022, 23960) 132 133check_erratum_chosen cortex_x4, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 134 135/* Disable hardware page aggregation. Enables mitigation for `CVE-2024-5660` */ 136workaround_reset_start cortex_x4, CVE(2024, 5660), WORKAROUND_CVE_2024_5660 137 sysreg_bit_set CORTEX_X4_CPUECTLR_EL1, BIT(46) 138workaround_reset_end cortex_x4, CVE(2024, 5660) 139 140check_erratum_ls cortex_x4, CVE(2024, 5660), CPU_REV(0, 2) 141 142workaround_reset_start cortex_x4, CVE(2024, 7881), WORKAROUND_CVE_2024_7881 143 /* --------------------------------- 144 * Sets BIT41 of CPUACTLR6_EL1 which 145 * disables L1 Data cache prefetcher 146 * --------------------------------- 147 */ 148 sysreg_bit_set CORTEX_X4_CPUACTLR6_EL1, BIT(41) 149workaround_reset_end cortex_x4, CVE(2024, 7881) 150 151check_erratum_chosen cortex_x4, CVE(2024, 7881), WORKAROUND_CVE_2024_7881 152 153cpu_reset_func_start cortex_x4 154 /* Disable speculative loads */ 155 msr SSBS, xzr 156 enable_mpmm 157cpu_reset_func_end cortex_x4 158 159 /* ---------------------------------------------------- 160 * HW will do the cache maintenance while powering down 161 * ---------------------------------------------------- 162 */ 163func cortex_x4_core_pwr_dwn 164 /* --------------------------------------------------- 165 * Enable CPU power down bit in power control register 166 * --------------------------------------------------- 167 */ 168 sysreg_bit_set CORTEX_X4_CPUPWRCTLR_EL1, CORTEX_X4_CPUPWRCTLR_EL1_CORE_PWRDN_BIT 169 170 apply_erratum cortex_x4, ERRATUM(2740089), ERRATA_X4_2740089 171 172 isb 173 ret 174endfunc cortex_x4_core_pwr_dwn 175 176 /* --------------------------------------------- 177 * This function provides Cortex X4-specific 178 * register information for crash reporting. 179 * It needs to return with x6 pointing to 180 * a list of register names in ascii and 181 * x8 - x15 having values of registers to be 182 * reported. 183 * --------------------------------------------- 184 */ 185.section .rodata.cortex_x4_regs, "aS" 186cortex_x4_regs: /* The ascii list of register names to be reported */ 187 .asciz "cpuectlr_el1", "" 188 189func cortex_x4_cpu_reg_dump 190 adr x6, cortex_x4_regs 191 mrs x8, CORTEX_X4_CPUECTLR_EL1 192 ret 193endfunc cortex_x4_cpu_reg_dump 194 195declare_cpu_ops cortex_x4, CORTEX_X4_MIDR, \ 196 cortex_x4_reset_func, \ 197 cortex_x4_core_pwr_dwn 198