1 /*
2 * Copyright (c) 2015-2025, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <assert.h>
8
9 #include <platform_def.h>
10
11 #include <arch.h>
12 #include <arch_helpers.h>
13 #include <common/debug.h>
14 #include <common/romlib.h>
15 #include <common/par.h>
16 #include <lib/extensions/sysreg128.h>
17 #include <lib/mmio.h>
18 #include <lib/smccc.h>
19 #include <lib/xlat_tables/xlat_tables_compat.h>
20 #include <services/arm_arch_svc.h>
21 #include <plat/arm/common/plat_arm.h>
22 #include <plat/common/platform.h>
23
24 /* Weak definitions may be overridden in specific ARM standard platform */
25 #pragma weak plat_get_ns_image_entrypoint
26 #pragma weak plat_arm_get_mmap
27
28 /* Conditionally provide a weak definition of plat_get_syscnt_freq2 to avoid
29 * conflicts with the definition in plat/common. */
30 #pragma weak plat_get_syscnt_freq2
31
32 /* Get ARM SOC-ID */
33 #pragma weak plat_arm_get_soc_id
34
35 /*******************************************************************************
36 * Changes the memory attributes for the region of mapped memory where the BL
37 * image's translation tables are located such that the tables will have
38 * read-only permissions.
39 ******************************************************************************/
40 #if PLAT_RO_XLAT_TABLES
arm_xlat_make_tables_readonly(void)41 void arm_xlat_make_tables_readonly(void)
42 {
43 int rc = xlat_make_tables_readonly();
44
45 if (rc != 0) {
46 ERROR("Failed to make translation tables read-only at EL%u.\n",
47 get_current_el());
48 panic();
49 }
50
51 INFO("Translation tables are now read-only at EL%u.\n",
52 get_current_el());
53 }
54 #endif
55
arm_setup_romlib(void)56 void arm_setup_romlib(void)
57 {
58 #if USE_ROMLIB
59 if (!rom_lib_init(ROMLIB_VERSION))
60 panic();
61 #endif
62 }
63
plat_get_ns_image_entrypoint(void)64 uintptr_t plat_get_ns_image_entrypoint(void)
65 {
66 #ifdef PRELOADED_BL33_BASE
67 return PRELOADED_BL33_BASE;
68 #else
69 return PLAT_ARM_NS_IMAGE_BASE;
70 #endif
71 }
72
73 /*******************************************************************************
74 * Gets SPSR for next stage images.
75 ******************************************************************************/
arm_get_spsr(unsigned int image_id)76 uint32_t arm_get_spsr(unsigned int image_id)
77 {
78 unsigned int __unused hyp_status, mode, spsr;
79
80 if (image_id == BL32_IMAGE_ID) {
81 /* The Secure Payload Dispatcher service is responsible for
82 * setting the SPSR prior to entry into the BL32 image.
83 */
84 return 0;
85 }
86
87 #ifdef __aarch64__
88 /* Figure out what mode we enter the non-secure world in */
89 mode = (el_implemented(2) != EL_IMPL_NONE) ? MODE_EL2 : MODE_EL1;
90
91 /*
92 * TODO: Consider the possibility of specifying the SPSR in
93 * the FIP ToC and allowing the platform to have a say as
94 * well.
95 */
96 spsr = SPSR_64((uint64_t)mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS);
97 #else
98 hyp_status = GET_VIRT_EXT(read_id_pfr1());
99
100 mode = (hyp_status) ? MODE32_hyp : MODE32_svc;
101
102 /*
103 * TODO: Consider the possibility of specifying the SPSR in
104 * the FIP ToC and allowing the platform to have a say as
105 * well.
106 */
107 spsr = SPSR_MODE32(mode, plat_get_ns_image_entrypoint() & 0x1,
108 SPSR_E_LITTLE, DISABLE_ALL_EXCEPTIONS);
109 #endif /* __aarch64__ */
110
111 return spsr;
112 }
113
114 /*******************************************************************************
115 * Configures access to the system counter timer module.
116 ******************************************************************************/
117 #ifdef ARM_SYS_TIMCTL_BASE
arm_configure_sys_timer(void)118 void arm_configure_sys_timer(void)
119 {
120 unsigned int reg_val;
121
122 /* Read the frequency of the system counter */
123 unsigned int freq_val = plat_get_syscnt_freq2();
124
125 #if ARM_CONFIG_CNTACR
126 reg_val = (1U << CNTACR_RPCT_SHIFT) | (1U << CNTACR_RVCT_SHIFT);
127 reg_val |= (1U << CNTACR_RFRQ_SHIFT) | (1U << CNTACR_RVOFF_SHIFT);
128 reg_val |= (1U << CNTACR_RWVT_SHIFT) | (1U << CNTACR_RWPT_SHIFT);
129 mmio_write_32(ARM_SYS_TIMCTL_BASE + CNTACR_BASE(PLAT_ARM_NSTIMER_FRAME_ID), reg_val);
130 #endif /* ARM_CONFIG_CNTACR */
131
132 reg_val = (1U << CNTNSAR_NS_SHIFT(PLAT_ARM_NSTIMER_FRAME_ID));
133 mmio_write_32(ARM_SYS_TIMCTL_BASE + CNTNSAR, reg_val);
134
135 /*
136 * Initialize CNTFRQ register in CNTCTLBase frame. The CNTFRQ
137 * system register initialized during psci_arch_setup() is different
138 * from this and has to be updated independently.
139 */
140 mmio_write_32(ARM_SYS_TIMCTL_BASE + CNTCTLBASE_CNTFRQ, freq_val);
141
142 #if defined(PLAT_juno) || defined(PLAT_n1sdp) || defined(PLAT_morello)
143 /*
144 * Initialize CNTFRQ register in Non-secure CNTBase frame.
145 * This is required for Juno, N1SDP and Morello because they do not
146 * follow ARM ARM in that the value updated in CNTFRQ is not
147 * reflected in CNTBASEN_CNTFRQ. Hence update the value manually.
148 */
149 mmio_write_32(ARM_SYS_CNT_BASE_NS + CNTBASEN_CNTFRQ, freq_val);
150 #endif
151 }
152 #endif /* ARM_SYS_TIMCTL_BASE */
153
154 /*******************************************************************************
155 * Returns ARM platform specific memory map regions.
156 ******************************************************************************/
plat_arm_get_mmap(void)157 const mmap_region_t *plat_arm_get_mmap(void)
158 {
159 return plat_arm_mmap;
160 }
161
162 #ifdef ARM_SYS_CNTCTL_BASE
163
plat_get_syscnt_freq2(void)164 unsigned int plat_get_syscnt_freq2(void)
165 {
166 unsigned int counter_base_frequency;
167
168 /* Read the frequency from Frequency modes table */
169 counter_base_frequency = mmio_read_32(ARM_SYS_CNTCTL_BASE + CNTFID_OFF);
170
171 /* The first entry of the frequency modes table must not be 0 */
172 if (counter_base_frequency == 0U)
173 panic();
174
175 return counter_base_frequency;
176 }
177
178 #endif /* ARM_SYS_CNTCTL_BASE */
179
180 #if SDEI_SUPPORT
181 /*
182 * Translate SDEI entry point to PA, and perform standard ARM entry point
183 * validation on it.
184 */
plat_sdei_validate_entry_point(uintptr_t ep,unsigned int client_mode)185 int plat_sdei_validate_entry_point(uintptr_t ep, unsigned int client_mode)
186 {
187 uint64_t pa;
188 sysreg_t par;
189 u_register_t scr_el3;
190
191 /* Doing Non-secure address translation requires SCR_EL3.NS set */
192 scr_el3 = read_scr_el3();
193 write_scr_el3(scr_el3 | SCR_NS_BIT);
194 isb();
195
196 assert((client_mode == MODE_EL2) || (client_mode == MODE_EL1));
197 if (client_mode == MODE_EL2) {
198 /*
199 * Translate entry point to Physical Address using the EL2
200 * translation regime.
201 */
202 ats1e2r(ep);
203 } else {
204 /*
205 * Translate entry point to Physical Address using the EL1&0
206 * translation regime, including stage 2.
207 */
208 AT(ats12e1r, ep);
209 }
210 isb();
211 par = read_par_el1();
212
213 /* Restore original SCRL_EL3 */
214 write_scr_el3(scr_el3);
215 isb();
216
217 /* If the translation resulted in fault, return failure */
218 if ((par & PAR_F_MASK) != 0)
219 return -1;
220
221 /* Extract Physical Address from PAR */
222 pa = get_par_el1_pa(par);
223
224 /* Perform NS entry point validation on the physical address */
225 return arm_validate_ns_entrypoint(pa);
226 }
227 #endif
228
plat_get_addr_mmap(void)229 const mmap_region_t *plat_get_addr_mmap(void)
230 {
231 return plat_arm_mmap;
232 }
233
234 #if ENABLE_RME
arm_gpt_setup(void)235 void arm_gpt_setup(void)
236 {
237 /*
238 * It is to be noted that any Arm platform that reuses arm_gpt_setup
239 * must implement plat_arm_get_gpt_info within its platform code
240 */
241 const arm_gpt_info_t *arm_gpt_info =
242 plat_arm_get_gpt_info();
243
244 if (arm_gpt_info == NULL) {
245 ERROR("arm_gpt_info not initialized!!\n");
246 panic();
247 }
248
249 /* Initialize entire protected space to GPT_GPI_ANY. */
250 if (gpt_init_l0_tables(arm_gpt_info->pps, arm_gpt_info->l0_base,
251 arm_gpt_info->l0_size) < 0) {
252 ERROR("gpt_init_l0_tables() failed!\n");
253 panic();
254 }
255
256 /* Carve out defined PAS ranges. */
257 if (gpt_init_pas_l1_tables(arm_gpt_info->pgs,
258 arm_gpt_info->l1_base,
259 arm_gpt_info->l1_size,
260 arm_gpt_info->pas_region_base,
261 arm_gpt_info->pas_region_count) < 0) {
262 ERROR("gpt_init_pas_l1_tables() failed!\n");
263 panic();
264 }
265
266 INFO("Enabling Granule Protection Checks\n");
267 if (gpt_enable() < 0) {
268 ERROR("gpt_enable() failed!\n");
269 panic();
270 }
271 }
272 #endif /* ENABLE_RME */
273