| 0be136d2 | 19-Sep-2018 |
Kalyani Chidambaram <kalyanic@nvidia.com> |
Tegra194: Update t194_nvg.h to v6.7
This patch updates the t194_nvg.h header file received from the CPU team to v6.7.
Change-Id: I5d25dfc60448e14b7085250946bd002fcb80a774 Signed-off-by: Kalyani Chi
Tegra194: Update t194_nvg.h to v6.7
This patch updates the t194_nvg.h header file received from the CPU team to v6.7.
Change-Id: I5d25dfc60448e14b7085250946bd002fcb80a774 Signed-off-by: Kalyani Chidambaram <kalyanic@nvidia.com>
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| c9796852 | 18-Mar-2020 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
Merge changes from topic "rpix-multi-console" into integration
* changes: rpi: docs: Update maintainers file to new RPi directory scheme rpi: console: Autodetect Mini-UART vs. PL011 configuratio
Merge changes from topic "rpix-multi-console" into integration
* changes: rpi: docs: Update maintainers file to new RPi directory scheme rpi: console: Autodetect Mini-UART vs. PL011 configuration rpi3: build: Include GPIO driver in all BL stages rpi: Allow using PL011 UART for RPi3/RPi4 rpi3: console: Use same "clock-less" setup scheme as RPi4 rpi3: gpio: Simplify GPIO setup
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| ea32cf50 | 18-Mar-2020 |
Manish Pandey <manish.pandey2@arm.com> |
Merge "Implement SMCCC_ARCH_SOC_ID SMC call" into integration |
| cfb3f733 | 18-Mar-2020 |
Olivier Deprez <olivier.deprez@arm.com> |
Merge "FVP: In BL31/SP_MIN, map only the needed DRAM region statically" into integration |
| 7a20da43 | 17-Mar-2020 |
Manish Pandey <manish.pandey2@arm.com> |
Merge "board/rddaniel: add NSAID sources for TZC400 driver" into integration |
| 493545b3 | 13-Mar-2020 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
FVP: In BL31/SP_MIN, map only the needed DRAM region statically
Rather than creating entry in plat_arm_mmap array to map the entire DRAM region in BL31/SP_MIN, only map a smaller region holding HW_C
FVP: In BL31/SP_MIN, map only the needed DRAM region statically
Rather than creating entry in plat_arm_mmap array to map the entire DRAM region in BL31/SP_MIN, only map a smaller region holding HW_CONFIG DTB. Consequently, an increase in number of sub-translation tables(level-2 and level-3) i.e., MAX_XLAT_TABLES is necessary to map the new region in memory.
In order to accommodate the increased code size in BL31 i.e., PROGBITS, the max size of BL31 image is increased by 0x1000(4K).
Change-Id: I540b8ee550588e22a3a9fb218183d2ab8061c851 Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
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| 9aaae8e6 | 24-Jan-2020 |
Andre Przywara <andre.przywara@arm.com> |
rpi: docs: Update maintainers file to new RPi directory scheme
With the addition of the Raspberry Pi 4 port the directory structure changed a bit, also the new port didn't have a separate entry.
Ad
rpi: docs: Update maintainers file to new RPi directory scheme
With the addition of the Raspberry Pi 4 port the directory structure changed a bit, also the new port didn't have a separate entry.
Add a new entry for the RPi4 port and adjust the path names.
Signed-off-by: Andre Przywara <andre.przywara@arm.com> Change-Id: I04b60e729a19bb0cc3dd6ce6899ec6480356b1f1
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| 9cc3fa1b | 11-Mar-2020 |
Andre Przywara <andre.przywara@arm.com> |
rpi: console: Autodetect Mini-UART vs. PL011 configuration
The Raspberry Pi has two different UART devices pin-muxed to GPIO 14&15: One ARM PL011 one and the 8250 compatible "Mini-UART". A dtoverlay
rpi: console: Autodetect Mini-UART vs. PL011 configuration
The Raspberry Pi has two different UART devices pin-muxed to GPIO 14&15: One ARM PL011 one and the 8250 compatible "Mini-UART". A dtoverlay parameter in config.txt will tell the firmware to switch between the two: it will setup the right clocks and will configure the pinmuxes accordingly.
To autodetect the user's choice, we read the pinmux register and check its setting: ALT5 (0x2) means the Mini-UART is used, ALT0 (0x4) points to the PL011. Based on that we select the UART driver to initialise.
This will allow console output in any case.
Change-Id: I620d3ce68de6c6576599f2a405636020e1fd1376 Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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| 29e8c460 | 11-Mar-2020 |
Andre Przywara <andre.przywara@arm.com> |
rpi3: build: Include GPIO driver in all BL stages
So far the Raspberry Pi 3 build needs the GPIO driver just for BL2. Upcoming changes will require some GPIO code in BL1 and BL31 also, so move those
rpi3: build: Include GPIO driver in all BL stages
So far the Raspberry Pi 3 build needs the GPIO driver just for BL2. Upcoming changes will require some GPIO code in BL1 and BL31 also, so move those driver files into the common source section.
This does not affect BL31 code size at all, and bl1.bin just increases by 144 bytes, but doesn't affect the padded binary size at all.
Signed-off-by: Andre Przywara <andre.przywara@arm.com> Change-Id: I7639746dc241c1e69099d85d2671c65fa0108555
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| 5e6d821c | 10-Mar-2020 |
Andre Przywara <andre.przywara@arm.com> |
rpi: Allow using PL011 UART for RPi3/RPi4
The Broadcom 283x SoCs feature multiple UARTs: the mostly used "Mini-UART", which is an 8250 compatible IP, and at least one PL011. While the 8250 is usuall
rpi: Allow using PL011 UART for RPi3/RPi4
The Broadcom 283x SoCs feature multiple UARTs: the mostly used "Mini-UART", which is an 8250 compatible IP, and at least one PL011. While the 8250 is usually used for serial console purposes, it suffers from a design flaw, where its clock depends on the VPU clock, which can change at runtime. This will reliably mess up the baud rate. To avoid this problem, people might choose to use the PL011 UART for the serial console, which is pin-mux'ed to the very same GPIO pins. This can be done by adding "miniuart-bt" to the "dtoverlay=" line in config.txt.
To prepare for this situation, use the newly gained freedom of sharing one console_t pointer across different UART drivers, to introduce the option of choosing the PL011 for the console.
This is for now hard-coded to choose the Mini-UART by default. A follow-up patch will introduce automatic detection.
Signed-off-by: Andre Przywara <andre.przywara@arm.com> Change-Id: I8cf2522151e09ff4ff94a6d396aec6fc4b091a05
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| 795aefe5 | 10-Mar-2020 |
Andre Przywara <andre.przywara@arm.com> |
rpi3: console: Use same "clock-less" setup scheme as RPi4
In the wake of the upcoming unification of the console setup code between RPi3 and RPi4, extend the "clock-less" setup scheme to the RPi3. T
rpi3: console: Use same "clock-less" setup scheme as RPi4
In the wake of the upcoming unification of the console setup code between RPi3 and RPi4, extend the "clock-less" setup scheme to the RPi3. This avoid programming any clocks or baud rate registers, which makes the port more robust against GPU firmware changes.
Signed-off-by: Andre Przywara <andre.przywara@arm.com> Change-Id: Ida83a963bb18a878997e9cbd55f8ceac6a2e1c1f
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| 0d92745e | 11-Mar-2020 |
Andre Przywara <andre.przywara@arm.com> |
rpi3: gpio: Simplify GPIO setup
There is really no reason to use and pass around a struct when its only member is the (fixed) base address.
Remove the struct and just use the base address on its ow
rpi3: gpio: Simplify GPIO setup
There is really no reason to use and pass around a struct when its only member is the (fixed) base address.
Remove the struct and just use the base address on its own inside the GPIO driver. Then set the base address automatically.
This simplifies GPIO setup for users, which now don't need to deal with zeroing a struct and setting the base address anymore.
Change-Id: I3060f7859e3f8ef9a24cc8fb38307b5da943f127 Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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| 0e753437 | 22-Feb-2020 |
Manish V Badarkhe <Manish.Badarkhe@arm.com> |
Implement SMCCC_ARCH_SOC_ID SMC call
Implemented SMCCC_ARCH_SOC_ID call in order to get below SOC information:
1. SOC revision 2. SOC version
Implementation done using below SMCCC specification do
Implement SMCCC_ARCH_SOC_ID SMC call
Implemented SMCCC_ARCH_SOC_ID call in order to get below SOC information:
1. SOC revision 2. SOC version
Implementation done using below SMCCC specification document: https://developer.arm.com/docs/den0028/c
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com> Change-Id: Ie0595f1c345a6429a6fb4a7f05534a0ca9c9a48b
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| 98a69dfd | 16-Mar-2020 |
Igor Opaniuk <igor.opaniuk@gmail.com> |
plat: imx: imx8qm: apply clk/pinmux configuration for DEBUG_CONSOLE
Having DEBUG_CONSOLE enabled without enabling DEBUG_CONSOLE_A53 doesn't make sense (since UART pinmux/clock configuration is appli
plat: imx: imx8qm: apply clk/pinmux configuration for DEBUG_CONSOLE
Having DEBUG_CONSOLE enabled without enabling DEBUG_CONSOLE_A53 doesn't make sense (since UART pinmux/clock configuration is applied for UART only when DEBUG_CONSOLE_A53 is enabled).
Enable DEBUG_CONSOLE_A53 if DEBUG_CONSOLE is enabled.
Signed-off-by: Igor Opaniuk <igor.opaniuk@gmail.com> Change-Id: I8ca411d5544658b9bcc39e5340ec042c51088b96
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| fc1596b3 | 16-Mar-2020 |
Igor Opaniuk <igor.opaniuk@gmail.com> |
plat: imx: imx8qm: provide debug uart num as build param
This removes hardcoded iomux/clk/addr configuration for debug uart, provides possibility (as a workaround, till that information isn't provid
plat: imx: imx8qm: provide debug uart num as build param
This removes hardcoded iomux/clk/addr configuration for debug uart, provides possibility (as a workaround, till that information isn't provided via DT) to set this configuration during compile time via IMX_DEBUG_UART build flag.
Usage: $ make PLAT=imx8qm IMX_DEBUG_UART=1 bl31
Signed-off-by: Igor Opaniuk <igor.opaniuk@gmail.com> Change-Id: Ib5f5dd81ba0c8ad2b2dc5647ec75629072f511c5
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| 965c0781 | 16-Mar-2020 |
Igor Opaniuk <igor.opaniuk@gmail.com> |
plat: imx: imx8_iomux: fix shift-overflow errors
This fixes shift overflow errors, when compiled with CONSOLE_DEBUG support:
plat/imx/common/include/imx8_iomux.h:11:35: error: result of ‘1 << 31’ r
plat: imx: imx8_iomux: fix shift-overflow errors
This fixes shift overflow errors, when compiled with CONSOLE_DEBUG support:
plat/imx/common/include/imx8_iomux.h:11:35: error: result of ‘1 << 31’ requires 33 bits to represent, but ‘int’ only has 32 bits [-Werror=shift-overflow=]
Signed-off-by: Igor Opaniuk <igor.opaniuk@gmail.com> Change-Id: I0488e22c30314ba27caabc5c767164baa1e8004c
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| 5e9369e8 | 16-Mar-2020 |
Mark Dykes <mardyk01@review.trustedfirmware.org> |
Merge "fconf: Add namespace guidance inside documentation" into integration |
| a6de824f | 28-Feb-2020 |
Louis Mayencourt <louis.mayencourt@arm.com> |
fconf: Clean Arm IO
Merge the previously introduced arm_fconf_io_storage into arm_io_storage. This removes the duplicate io_policies and functions definition.
This patch: - replace arm_io_storage.c
fconf: Clean Arm IO
Merge the previously introduced arm_fconf_io_storage into arm_io_storage. This removes the duplicate io_policies and functions definition.
This patch: - replace arm_io_storage.c with the content of arm_fconf_io_storage.c - rename the USE_FCONF_BASED_IO option into ARM_IO_IN_DTB. - use the ARM_IO_IN_DTB option to compile out io_policies moved in dtb. - propagate DEFINES when parsing dts. - use ARM_IO_IN_DTB to include or not uuid nodes in fw_config dtb. - set the ARM_IO_IN_DTB to 0 by default for fvp. This ensure that the behavior of fvp stays the same as it was before the introduction of fconf.
Change-Id: Ia774a96d1d3a2bccad29f7ce2e2b4c21b26c080e Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
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| 3888c2d4 | 14-Mar-2020 |
Haojian Zhuang <haojian.zhuang@linaro.org> |
docs: remove uefi-tools in hikey and hikey960
Since uefi-tools isn't used any more in hikey and hikey960, update the documents.
Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org> Change-Id:
docs: remove uefi-tools in hikey and hikey960
Since uefi-tools isn't used any more in hikey and hikey960, update the documents.
Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org> Change-Id: I0843d27610e241d442e58b6cd71967998730a35d
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| bb37363b | 13-Mar-2020 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
Merge "SPMD: Add support for SPCI_ID_GET" into integration |
| 6b354cf3 | 13-Mar-2020 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
Merge "Add a .gitreview file for convenience" into integration |
| 2fc18a25 | 02-Mar-2020 |
Louis Mayencourt <louis.mayencourt@arm.com> |
plat/sgi: Bump bl1 RW limit
Increase bl1 RW limit to allow future development.
Change-Id: I3159b36dbaca798b4c4374c1415cd033d6586388 Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com> |
| 4c9ad0df | 13-Mar-2020 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
Merge "juno/sgm: Maximize space allocated to SCP_BL2" into integration |
| e820759f | 12-Mar-2020 |
Mark Dykes <mardyk01@review.trustedfirmware.org> |
Merge "Mention COT build option in trusted-board-boot-build.rst" into integration |
| bd2ad929 | 12-Mar-2020 |
Mark Dykes <mardyk01@review.trustedfirmware.org> |
Merge "Update cryptographic algorithms in TBBR doc" into integration |