xref: /rk3399_ARM-atf/plat/st/stm32mp1/stm32mp1_private.c (revision c0ea3b1b79aeb67495e1a5389e50c5a315ba8de0) 
1 /*
2  * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  */
6 
7 #include <assert.h>
8 
9 #include <libfdt.h>
10 
11 #include <platform_def.h>
12 
13 #include <drivers/st/stm32_iwdg.h>
14 #include <lib/xlat_tables/xlat_tables_v2.h>
15 
16 /* Internal layout of the 32bit OTP word board_id */
17 #define BOARD_ID_BOARD_NB_MASK		GENMASK(31, 16)
18 #define BOARD_ID_BOARD_NB_SHIFT		16
19 #define BOARD_ID_VARIANT_MASK		GENMASK(15, 12)
20 #define BOARD_ID_VARIANT_SHIFT		12
21 #define BOARD_ID_REVISION_MASK		GENMASK(11, 8)
22 #define BOARD_ID_REVISION_SHIFT		8
23 #define BOARD_ID_BOM_MASK		GENMASK(3, 0)
24 
25 #define BOARD_ID2NB(_id)		(((_id) & BOARD_ID_BOARD_NB_MASK) >> \
26 					 BOARD_ID_BOARD_NB_SHIFT)
27 #define BOARD_ID2VAR(_id)		(((_id) & BOARD_ID_VARIANT_MASK) >> \
28 					 BOARD_ID_VARIANT_SHIFT)
29 #define BOARD_ID2REV(_id)		(((_id) & BOARD_ID_REVISION_MASK) >> \
30 					 BOARD_ID_REVISION_SHIFT)
31 #define BOARD_ID2BOM(_id)		((_id) & BOARD_ID_BOM_MASK)
32 
33 #define MAP_SRAM	MAP_REGION_FLAT(STM32MP_SYSRAM_BASE, \
34 					STM32MP_SYSRAM_SIZE, \
35 					MT_MEMORY | \
36 					MT_RW | \
37 					MT_SECURE | \
38 					MT_EXECUTE_NEVER)
39 
40 #define MAP_DEVICE1	MAP_REGION_FLAT(STM32MP1_DEVICE1_BASE, \
41 					STM32MP1_DEVICE1_SIZE, \
42 					MT_DEVICE | \
43 					MT_RW | \
44 					MT_SECURE | \
45 					MT_EXECUTE_NEVER)
46 
47 #define MAP_DEVICE2	MAP_REGION_FLAT(STM32MP1_DEVICE2_BASE, \
48 					STM32MP1_DEVICE2_SIZE, \
49 					MT_DEVICE | \
50 					MT_RW | \
51 					MT_SECURE | \
52 					MT_EXECUTE_NEVER)
53 
54 #if defined(IMAGE_BL2)
55 static const mmap_region_t stm32mp1_mmap[] = {
56 	MAP_SRAM,
57 	MAP_DEVICE1,
58 	MAP_DEVICE2,
59 	{0}
60 };
61 #endif
62 #if defined(IMAGE_BL32)
63 static const mmap_region_t stm32mp1_mmap[] = {
64 	MAP_SRAM,
65 	MAP_DEVICE1,
66 	MAP_DEVICE2,
67 	{0}
68 };
69 #endif
70 
71 void configure_mmu(void)
72 {
73 	mmap_add(stm32mp1_mmap);
74 	init_xlat_tables();
75 
76 	enable_mmu_svc_mon(0);
77 }
78 
79 uintptr_t stm32_get_gpio_bank_base(unsigned int bank)
80 {
81 	if (bank == GPIO_BANK_Z) {
82 		return GPIOZ_BASE;
83 	}
84 
85 	assert(GPIO_BANK_A == 0 && bank <= GPIO_BANK_K);
86 
87 	return GPIOA_BASE + (bank * GPIO_BANK_OFFSET);
88 }
89 
90 uint32_t stm32_get_gpio_bank_offset(unsigned int bank)
91 {
92 	if (bank == GPIO_BANK_Z) {
93 		return 0;
94 	}
95 
96 	assert(GPIO_BANK_A == 0 && bank <= GPIO_BANK_K);
97 
98 	return bank * GPIO_BANK_OFFSET;
99 }
100 
101 unsigned long stm32_get_gpio_bank_clock(unsigned int bank)
102 {
103 	if (bank == GPIO_BANK_Z) {
104 		return GPIOZ;
105 	}
106 
107 	assert(GPIO_BANK_A == 0 && bank <= GPIO_BANK_K);
108 
109 	return GPIOA + (bank - GPIO_BANK_A);
110 }
111 
112 static int get_part_number(uint32_t *part_nb)
113 {
114 	uint32_t part_number;
115 	uint32_t dev_id;
116 
117 	if (stm32mp1_dbgmcu_get_chip_dev_id(&dev_id) < 0) {
118 		return -1;
119 	}
120 
121 	if (bsec_shadow_read_otp(&part_number, PART_NUMBER_OTP) != BSEC_OK) {
122 		ERROR("BSEC: PART_NUMBER_OTP Error\n");
123 		return -1;
124 	}
125 
126 	part_number = (part_number & PART_NUMBER_OTP_PART_MASK) >>
127 		PART_NUMBER_OTP_PART_SHIFT;
128 
129 	*part_nb = part_number | (dev_id << 16);
130 
131 	return 0;
132 }
133 
134 static int get_cpu_package(uint32_t *cpu_package)
135 {
136 	uint32_t package;
137 
138 	if (bsec_shadow_read_otp(&package, PACKAGE_OTP) != BSEC_OK) {
139 		ERROR("BSEC: PACKAGE_OTP Error\n");
140 		return -1;
141 	}
142 
143 	*cpu_package = (package & PACKAGE_OTP_PKG_MASK) >>
144 		PACKAGE_OTP_PKG_SHIFT;
145 
146 	return 0;
147 }
148 
149 void stm32mp_print_cpuinfo(void)
150 {
151 	const char *cpu_s, *cpu_r, *pkg;
152 	uint32_t part_number;
153 	uint32_t cpu_package;
154 	uint32_t chip_dev_id;
155 	int ret;
156 
157 	/* MPUs Part Numbers */
158 	ret = get_part_number(&part_number);
159 	if (ret < 0) {
160 		WARN("Cannot get part number\n");
161 		return;
162 	}
163 
164 	switch (part_number) {
165 	case STM32MP157C_PART_NB:
166 		cpu_s = "157C";
167 		break;
168 	case STM32MP157A_PART_NB:
169 		cpu_s = "157A";
170 		break;
171 	case STM32MP153C_PART_NB:
172 		cpu_s = "153C";
173 		break;
174 	case STM32MP153A_PART_NB:
175 		cpu_s = "153A";
176 		break;
177 	case STM32MP151C_PART_NB:
178 		cpu_s = "151C";
179 		break;
180 	case STM32MP151A_PART_NB:
181 		cpu_s = "151A";
182 		break;
183 	default:
184 		cpu_s = "????";
185 		break;
186 	}
187 
188 	/* Package */
189 	ret = get_cpu_package(&cpu_package);
190 	if (ret < 0) {
191 		WARN("Cannot get CPU package\n");
192 		return;
193 	}
194 
195 	switch (cpu_package) {
196 	case PKG_AA_LFBGA448:
197 		pkg = "AA";
198 		break;
199 	case PKG_AB_LFBGA354:
200 		pkg = "AB";
201 		break;
202 	case PKG_AC_TFBGA361:
203 		pkg = "AC";
204 		break;
205 	case PKG_AD_TFBGA257:
206 		pkg = "AD";
207 		break;
208 	default:
209 		pkg = "??";
210 		break;
211 	}
212 
213 	/* REVISION */
214 	ret = stm32mp1_dbgmcu_get_chip_version(&chip_dev_id);
215 	if (ret < 0) {
216 		WARN("Cannot get CPU version\n");
217 		return;
218 	}
219 
220 	switch (chip_dev_id) {
221 	case STM32MP1_REV_B:
222 		cpu_r = "B";
223 		break;
224 	default:
225 		cpu_r = "?";
226 		break;
227 	}
228 
229 	NOTICE("CPU: STM32MP%s%s Rev.%s\n", cpu_s, pkg, cpu_r);
230 }
231 
232 void stm32mp_print_boardinfo(void)
233 {
234 	uint32_t board_id;
235 	uint32_t board_otp;
236 	int bsec_node, bsec_board_id_node;
237 	void *fdt;
238 	const fdt32_t *cuint;
239 
240 	if (fdt_get_address(&fdt) == 0) {
241 		panic();
242 	}
243 
244 	bsec_node = fdt_node_offset_by_compatible(fdt, -1, DT_BSEC_COMPAT);
245 	if (bsec_node < 0) {
246 		return;
247 	}
248 
249 	bsec_board_id_node = fdt_subnode_offset(fdt, bsec_node, "board_id");
250 	if (bsec_board_id_node <= 0) {
251 		return;
252 	}
253 
254 	cuint = fdt_getprop(fdt, bsec_board_id_node, "reg", NULL);
255 	if (cuint == NULL) {
256 		panic();
257 	}
258 
259 	board_otp = fdt32_to_cpu(*cuint) / sizeof(uint32_t);
260 
261 	if (bsec_shadow_read_otp(&board_id, board_otp) != BSEC_OK) {
262 		ERROR("BSEC: PART_NUMBER_OTP Error\n");
263 		return;
264 	}
265 
266 	if (board_id != 0U) {
267 		char rev[2];
268 
269 		rev[0] = BOARD_ID2REV(board_id) - 1 + 'A';
270 		rev[1] = '\0';
271 		NOTICE("Board: MB%04x Var%d Rev.%s-%02d\n",
272 		       BOARD_ID2NB(board_id),
273 		       BOARD_ID2VAR(board_id),
274 		       rev,
275 		       BOARD_ID2BOM(board_id));
276 	}
277 }
278 
279 /* Return true when SoC provides a single Cortex-A7 core, and false otherwise */
280 bool stm32mp_is_single_core(void)
281 {
282 	uint32_t part_number;
283 	bool ret = false;
284 
285 	if (get_part_number(&part_number) < 0) {
286 		ERROR("Invalid part number, assume single core chip");
287 		return true;
288 	}
289 
290 	switch (part_number) {
291 	case STM32MP151A_PART_NB:
292 	case STM32MP151C_PART_NB:
293 		ret = true;
294 		break;
295 
296 	default:
297 		break;
298 	}
299 
300 	return ret;
301 }
302 
303 /* Return true when device is in closed state */
304 bool stm32mp_is_closed_device(void)
305 {
306 	uint32_t value;
307 
308 	if ((bsec_shadow_register(DATA0_OTP) != BSEC_OK) ||
309 	    (bsec_read_otp(&value, DATA0_OTP) != BSEC_OK)) {
310 		return true;
311 	}
312 
313 	return (value & DATA0_OTP_SECURED) == DATA0_OTP_SECURED;
314 }
315 
316 uint32_t stm32_iwdg_get_instance(uintptr_t base)
317 {
318 	switch (base) {
319 	case IWDG1_BASE:
320 		return IWDG1_INST;
321 	case IWDG2_BASE:
322 		return IWDG2_INST;
323 	default:
324 		panic();
325 	}
326 }
327 
328 uint32_t stm32_iwdg_get_otp_config(uint32_t iwdg_inst)
329 {
330 	uint32_t iwdg_cfg = 0U;
331 	uint32_t otp_value;
332 
333 #if defined(IMAGE_BL2)
334 	if (bsec_shadow_register(HW2_OTP) != BSEC_OK) {
335 		panic();
336 	}
337 #endif
338 
339 	if (bsec_read_otp(&otp_value, HW2_OTP) != BSEC_OK) {
340 		panic();
341 	}
342 
343 	if ((otp_value & BIT(iwdg_inst + HW2_OTP_IWDG_HW_POS)) != 0U) {
344 		iwdg_cfg |= IWDG_HW_ENABLED;
345 	}
346 
347 	if ((otp_value & BIT(iwdg_inst + HW2_OTP_IWDG_FZ_STOP_POS)) != 0U) {
348 		iwdg_cfg |= IWDG_DISABLE_ON_STOP;
349 	}
350 
351 	if ((otp_value & BIT(iwdg_inst + HW2_OTP_IWDG_FZ_STANDBY_POS)) != 0U) {
352 		iwdg_cfg |= IWDG_DISABLE_ON_STANDBY;
353 	}
354 
355 	return iwdg_cfg;
356 }
357 
358 #if defined(IMAGE_BL2)
359 uint32_t stm32_iwdg_shadow_update(uint32_t iwdg_inst, uint32_t flags)
360 {
361 	uint32_t otp;
362 	uint32_t result;
363 
364 	if (bsec_shadow_read_otp(&otp, HW2_OTP) != BSEC_OK) {
365 		panic();
366 	}
367 
368 	if ((flags & IWDG_DISABLE_ON_STOP) != 0U) {
369 		otp |= BIT(iwdg_inst + HW2_OTP_IWDG_FZ_STOP_POS);
370 	}
371 
372 	if ((flags & IWDG_DISABLE_ON_STANDBY) != 0U) {
373 		otp |= BIT(iwdg_inst + HW2_OTP_IWDG_FZ_STANDBY_POS);
374 	}
375 
376 	result = bsec_write_otp(otp, HW2_OTP);
377 	if (result != BSEC_OK) {
378 		return result;
379 	}
380 
381 	/* Sticky lock OTP_IWDG (read and write) */
382 	if (!bsec_write_sr_lock(HW2_OTP, 1U) ||
383 	    !bsec_write_sw_lock(HW2_OTP, 1U)) {
384 		return BSEC_LOCK_FAIL;
385 	}
386 
387 	return BSEC_OK;
388 }
389 #endif
390 
391 /* Get the non-secure DDR size */
392 uint32_t stm32mp_get_ddr_ns_size(void)
393 {
394 	static uint32_t ddr_ns_size;
395 	uint32_t ddr_size;
396 
397 	if (ddr_ns_size != 0U) {
398 		return ddr_ns_size;
399 	}
400 
401 	ddr_size = dt_get_ddr_size();
402 	if ((ddr_size <= (STM32MP_DDR_S_SIZE + STM32MP_DDR_SHMEM_SIZE)) ||
403 	    (ddr_size > STM32MP_DDR_MAX_SIZE)) {
404 		panic();
405 	}
406 
407 	ddr_ns_size = ddr_size - (STM32MP_DDR_S_SIZE + STM32MP_DDR_SHMEM_SIZE);
408 
409 	return ddr_ns_size;
410 }
411