Merge changes from topic "static_analysis" into integration

* changes:
io: io_stm32image: correct possible NULL pointer dereference
plat/st: correctly check pwr-regulators node
nand: stm32_fmc

Merge changes from topic "static_analysis" into integration

* changes:
io: io_stm32image: correct possible NULL pointer dereference
plat/st: correctly check pwr-regulators node
nand: stm32_fmc2_nand: correct xor_ecc.val assigned value
plat/st: correct static analysis tool warning
raw_nand: correct static analysis tool warning
spi: stm32_qspi: correct static analysis issues

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io: io_stm32image: correct possible NULL pointer dereference

This issue was found with cppcheck in our downstream code:
[drivers/st/io/io_stm32image.c:234] -> [drivers/st/io/io_stm32image.c:244]:
(

io: io_stm32image: correct possible NULL pointer dereference

This issue was found with cppcheck in our downstream code:
[drivers/st/io/io_stm32image.c:234] -> [drivers/st/io/io_stm32image.c:244]:
(warning) Either the condition 'buffer!=0U' is redundant or there is
possible null pointer dereference: local_buffer.

Change-Id: Ieb615b7e485dc93bbeeed4cd8bf845eb84c14ac9
Signed-off-by: Yann Gautier <yann.gautier@st.com>

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plat/st: correctly check pwr-regulators node

This warning was issued by cppcheck in our downstream code:
[plat/st/common/stm32mp_dt.c:629] -> [plat/st/common/stm32mp_dt.c:634]:
(warning) Identical

plat/st: correctly check pwr-regulators node

This warning was issued by cppcheck in our downstream code:
[plat/st/common/stm32mp_dt.c:629] -> [plat/st/common/stm32mp_dt.c:634]:
(warning) Identical condition 'node<0', second condition is always false

The second test has to check variable pwr_regulators_node.

Change-Id: I4a20c4a3ac0ef0639c2df36309d90a61c02b511f
Signed-off-by: Yann Gautier <yann.gautier@st.com>

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nand: stm32_fmc2_nand: correct xor_ecc.val assigned value

The variable is wrongly set to 0L, whereas it is an unsigned int, it should
then be 0U.

Change-Id: I0b164c0ea598ec8a503f1693da2f3789f59da23

nand: stm32_fmc2_nand: correct xor_ecc.val assigned value

The variable is wrongly set to 0L, whereas it is an unsigned int, it should
then be 0U.

Change-Id: I0b164c0ea598ec8a503f1693da2f3789f59da238
Signed-off-by: Yann Gautier <yann.gautier@st.com>

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plat/st: correct static analysis tool warning

Correct the following sparse warnings:
plat/st/common/stm32mp_dt.c:103:5: warning:
symbol 'fdt_get_node_parent_address_cells' was not declared.
Should

plat/st: correct static analysis tool warning

Correct the following sparse warnings:
plat/st/common/stm32mp_dt.c:103:5: warning:
symbol 'fdt_get_node_parent_address_cells' was not declared.
Should it be static?
plat/st/common/stm32mp_dt.c:123:5: warning:
symbol 'fdt_get_node_parent_size_cells' was not declared.
Should it be static?

As those 2 functions are only used by assert(), put them under
ENABLE_ASSERTIONS flag.

Change-Id: Iad721f12128df83a3de3f53e7920a9c1dce64c56
Signed-off-by: Yann Gautier <yann.gautier@st.com>

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raw_nand: correct static analysis tool warning

Correct the following warning given by sparse tool:
include/drivers/raw_nand.h:158:3: warning:
symbol '__packed' was not declared. Should it be static

raw_nand: correct static analysis tool warning

Correct the following warning given by sparse tool:
include/drivers/raw_nand.h:158:3: warning:
symbol '__packed' was not declared. Should it be static?

Change-Id: I03bd9a8aee5cdc5212ce5225be8033f1a6e92bd9
Signed-off-by: Yann Gautier <yann.gautier@st.com>

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spi: stm32_qspi: correct static analysis issues

Sparse issue:
drivers/st/spi/stm32_qspi.c:445:5:
warning: symbol 'stm32_qspi_init' was not declared. Should it be static?

Cppcheck issue:
[drivers/s

spi: stm32_qspi: correct static analysis issues

Sparse issue:
drivers/st/spi/stm32_qspi.c:445:5:
warning: symbol 'stm32_qspi_init' was not declared. Should it be static?

Cppcheck issue:
[drivers/st/spi/stm32_qspi.c:175] -> [drivers/st/spi/stm32_qspi.c:187]:
(style) Variable 'len' is reassigned a value before the old one has been
used.
[drivers/st/spi/stm32_qspi.c:178]:
(style) The scope of the variable 'timeout' can be reduced.

Change-Id: I575fb50766355a6717cbd193fc4a80ff1923014c
Signed-off-by: Yann Gautier <yann.gautier@st.com>

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Merge "allwinner: H6: Fix GPIO and CCU memory map addresses" into integration

plat: imx: imx8qx: provide debug uart num as build param

1. This removes hardcoded iomux/clk/addr configuration for debug uart,
provides possibility (as a workaround, till that information isn't
pro

plat: imx: imx8qx: provide debug uart num as build param

1. This removes hardcoded iomux/clk/addr configuration for debug uart,
provides possibility (as a workaround, till that information isn't
provided via DT) to set this configuration during compile time via
IMX_DEBUG_UART build flag.

Also for Colibri i.MX8QXP different pinmux configuration is applied
for UART3, FLEXCAN2_RX/TX pads are muxed to ADMA_UART3_RX/TX.

2. Having DEBUG_CONSOLE enabled without enabling DEBUG_CONSOLE_A35
doesn't make sense (since UART pinmux/clock configuration is applied
for UART only when DEBUG_CONSOLE_A35 is enabled. Check similar commit
for i.MX8QM 98a69dfd4a("plat: imx: imx8qm: apply clk/pinmux
configuration for DEBUG_CONSOLE")).

Usage:
$ make PLAT=imx8qx IMX_DEBUG_UART=3 DEBUG_CONSOLE=1 bl31

Signed-off-by: Igor Opaniuk <igor.opaniuk@gmail.com>
Change-Id: I5d04939b2e8ee1a5f4b2f3c6241977d3c6e91760

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Merge changes from topic "tegra-downstream-03192020" into integration

* changes:
Tegra194: move cluster and CPU counter to header file.
Tegra: gicv2: initialize target masks
spd: tlkd: support

Merge changes from topic "tegra-downstream-03192020" into integration

* changes:
Tegra194: move cluster and CPU counter to header file.
Tegra: gicv2: initialize target masks
spd: tlkd: support new TLK SMCs for RPMB service
Tegra210: trigger CPU0 hotplug power on using FC
Tegra: memctrl: cleanup streamid override registers
Tegra: memctrl_v2: remove support to secure TZSRAM
Tegra: include platform headers from individual makefiles
Tegra210: rename ENABLE_WDT_LEGACY_FIQ_HANDLING macro
Tegra194: SiP function ID to read SMMU_PER registers
Tegra: memctrl: map video memory as uncached
Tegra: remove support for USE_COHERENT_MEM
Tegra: remove circular dependency with common_def.h
Tegra: include missing stdbool.h
Tegra: remove support for SEPARATE_CODE_AND_RODATA=0

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spm: Add spci manifest binding document

The manifest binding document defines the expected properties and their formats
to represent a partition manifest in device tree.

Change-Id: I5eb250c7b89e0d8

spm: Add spci manifest binding document

The manifest binding document defines the expected properties and their formats
to represent a partition manifest in device tree.

Change-Id: I5eb250c7b89e0d828e1fcfce32b121e4081879ec
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>

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Merge "plat/arm/sgi: mark remote chip shared ram as non-cacheable" into integration

Merge changes I8ca411d5,Ib5f5dd81,I0488e22c into integration

* changes:
plat: imx: imx8qm: apply clk/pinmux configuration for DEBUG_CONSOLE
plat: imx: imx8qm: provide debug uart num as build par

Merge changes I8ca411d5,Ib5f5dd81,I0488e22c into integration

* changes:
plat: imx: imx8qm: apply clk/pinmux configuration for DEBUG_CONSOLE
plat: imx: imx8qm: provide debug uart num as build param
plat: imx: imx8_iomux: fix shift-overflow errors

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allwinner: H6: Fix GPIO and CCU memory map addresses

The base address for both the GPIO and the clock unit of the H6 memory map
have been typo-ed. Fix them to match the Linux DT and the manual.

The

allwinner: H6: Fix GPIO and CCU memory map addresses

The base address for both the GPIO and the clock unit of the H6 memory map
have been typo-ed. Fix them to match the Linux DT and the manual.

The H6 code use neither of them, so this doesn't change or fix anything
in the real world, but should be corrected anyway.

The issue was found and reported by Github user "armlabs".

Change-Id: Ic6fdfb732ce1cfc54cbb927718035624a06a9e08
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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Tegra: fixup GIC init from the 'on_finish' handler

Commit e9e19fb2fe684a740afc4820b3ee4cc38ad67d70 accidentally removed the
GIC init routine required to initialze the distributor on system resume.

Tegra: fixup GIC init from the 'on_finish' handler

Commit e9e19fb2fe684a740afc4820b3ee4cc38ad67d70 accidentally removed the
GIC init routine required to initialze the distributor on system resume.

This patch fixes this anomaly and initializes the distributor on system
resume.

Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: I3fdc694404faa509952f2d90b1f16541165e583e

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Tegra194: move cluster and CPU counter to header file.

MISRA rules request that the cluster and CPU counter be unsigned
values and have a suffix 'U'. If the define located in the makefile,
this cann

Tegra194: move cluster and CPU counter to header file.

MISRA rules request that the cluster and CPU counter be unsigned
values and have a suffix 'U'. If the define located in the makefile,
this cannot be done.

This patch moves the PLATFORM_CLUSTER_COUNT and PLATFORM_MAX_CPUS_PER_CLUSTER
macros to tegra_def.h as a result.

Change-Id: I9ef0beb29485729de204b4ffbb5241b039690e5a
Signed-off-by: Anthony Zhou <anzhou@nvidia.com>

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Tegra: gicv2: initialize target masks

This patch initializes the target masks in the GICv2 driver
data, for all PEs. This will allow platforms to set the PE
target for SPIs.

Change-Id: I7bf2ad79c04

Tegra: gicv2: initialize target masks

This patch initializes the target masks in the GICv2 driver
data, for all PEs. This will allow platforms to set the PE
target for SPIs.

Change-Id: I7bf2ad79c04c2555ab310acba17823fb157327a3
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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spd: tlkd: support new TLK SMCs for RPMB service

This patch adds support to handle following TLK SMCs:
{TLK_SET_BL_VERSION, TLK_LOCK_BL_INTERFACE, TLK_BL_RPMB_SERVICE}

These SMCs need to be support

spd: tlkd: support new TLK SMCs for RPMB service

This patch adds support to handle following TLK SMCs:
{TLK_SET_BL_VERSION, TLK_LOCK_BL_INTERFACE, TLK_BL_RPMB_SERVICE}

These SMCs need to be supported in ATF in order to forward them to
TLK. Otherwise, these functionalities won't work.

Brief:
TLK_SET_BL_VERSION: This SMC is issued by the bootloader to supply its
version to TLK. TLK can use this to prevent rollback attacks.

TLK_LOCK_BL_INTERFACE: This SMC is issued by bootloader before handing off
execution to the OS. This allows preventing sensitive SMCs being used
by the OS.

TLK_BL_RPMB_SERVICE: bootloader issues this SMC to sign or verify RPMB
frames.

Tested by: Tests TLK can receive the new SMCs issued by bootloader

Change-Id: I57c2d189a5f7a77cea26c3f8921866f2a6f0f944
Signed-off-by: Mustafa Yigit Bilgen <mbilgen@nvidia.com>

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Tegra210: trigger CPU0 hotplug power on using FC

Hotplug poweron is not working for boot CPU as it's being
triggerred using PMC and not with Flow Controller. This is
happening because "cpu_powergate

Tegra210: trigger CPU0 hotplug power on using FC

Hotplug poweron is not working for boot CPU as it's being
triggerred using PMC and not with Flow Controller. This is
happening because "cpu_powergate_mask" is only getting set
for non-boot CPU's as the boot CPU's first bootup follows
different code path. The patch is marking a CPU as ON within
"cpu_powergate_mask" when turning its power domain on
during power on. This will ensure only first bootup on all
CPU's is using PMC and subsequent hotplug poweron will be
using Flow Controller.

Change-Id: Ie9e86e6f9a777d41508a93d2ce286f31307932c2
Signed-off-by: sumitg <sumitg@nvidia.com>

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Tegra: memctrl: cleanup streamid override registers

Streamid override registers are passed to memctrl to program bypass
streamid for all the registers. There is no reason to bypass SMMU
for any of t

Tegra: memctrl: cleanup streamid override registers

Streamid override registers are passed to memctrl to program bypass
streamid for all the registers. There is no reason to bypass SMMU
for any of the client so need to remove register list and do not
set streamid_override_cfg.

Some Tegra186 platforms don't boot due to SDMMC failure so keep SDMMC
bypass as of now. Will revisit once these issues are fixed.

Change-Id: I3f67e2a0e1b53160e2218f3acace7da45532f934
Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com>

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Tegra: memctrl_v2: remove support to secure TZSRAM

This patch removes support to secure the on-chip TZSRAM memory for
Tegra186 and Tegra194 platforms as the previous bootloader does that
for them.

Tegra: memctrl_v2: remove support to secure TZSRAM

This patch removes support to secure the on-chip TZSRAM memory for
Tegra186 and Tegra194 platforms as the previous bootloader does that
for them.

Change-Id: I50c7b7f9694285fe31135ada09baed1cfedaaf07
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra: include platform headers from individual makefiles

This patch modifies PLAT_INCLUDES to include individual Tegra SoC
headers from the platform's makefile.

Change-Id: If5248667f4e58ac18727d37

Tegra: include platform headers from individual makefiles

This patch modifies PLAT_INCLUDES to include individual Tegra SoC
headers from the platform's makefile.

Change-Id: If5248667f4e58ac18727d37a18fbba8e53f2d7b5
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra210: rename ENABLE_WDT_LEGACY_FIQ_HANDLING macro

This patch renames 'ENABLE_WDT_LEGACY_FIQ_HANDLING' macro to
'ENABLE_TEGRA_WDT_LEGACY_FIQ_HANDLING', to indicate that this
is a Tegra feature.

Tegra210: rename ENABLE_WDT_LEGACY_FIQ_HANDLING macro

This patch renames 'ENABLE_WDT_LEGACY_FIQ_HANDLING' macro to
'ENABLE_TEGRA_WDT_LEGACY_FIQ_HANDLING', to indicate that this
is a Tegra feature.

Change-Id: I5c4431e662223ee80efbfd5ec2513f8b1cadfc50
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra194: SiP function ID to read SMMU_PER registers

This patch introduces SiP function ID, 0xC200FF00, to read SMMU_PER
error records from all supported SMMU blocks.

The register values are passed

Tegra194: SiP function ID to read SMMU_PER registers

This patch introduces SiP function ID, 0xC200FF00, to read SMMU_PER
error records from all supported SMMU blocks.

The register values are passed over to the client via CPU registers
X1 - X3, where

X1 = SMMU_PER[instance #1] | SMMU_PER[instance #0]
X2 = SMMU_PER[instance #3] | SMMU_PER[instance #2]
X3 = SMMU_PER[instance #5] | SMMU_PER[instance #4]

Change-Id: Id56263f558838ad05f6021f8432e618e99e190fc
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra: memctrl: map video memory as uncached

Memmap video memory as uncached normal memory by adding flag
'MT_NON_CACHEABLE' in mmap_add_dynamic_region().
This improves the time taken for clearing t

Tegra: memctrl: map video memory as uncached

Memmap video memory as uncached normal memory by adding flag
'MT_NON_CACHEABLE' in mmap_add_dynamic_region().
This improves the time taken for clearing the non-overlapping video
memory:

test conditions: 32MB memory size, EMC running at 1866MHz, t186
1) without MT_NON_CACHEABLE: 30ms ~ 40ms
<3>[ 133.852885] vpr-heap: update vpr base to 0x00000000c6000000, size=e000000
<3>[ 133.860471] _tegra_set_vpr_params[120]: begin
<3>[ 133.896481] _tegra_set_vpr_params[123]: end
<3>[ 133.908944] vpr-heap: update vpr base to 0x00000000c6000000, size=c000000
<3>[ 133.916397] _tegra_set_vpr_params[120]: begin
<3>[ 133.956369] _tegra_set_vpr_params[123]: end
<3>[ 133.970394] vpr-heap: update vpr base to 0x00000000c6000000, size=a000000
<3>[ 133.977934] _tegra_set_vpr_params[120]: begin
<3>[ 134.013874] _tegra_set_vpr_params[123]: end
<3>[ 134.025666] vpr-heap: update vpr base to 0x00000000c6000000, size=8000000
<3>[ 134.033512] _tegra_set_vpr_params[120]: begin
<3>[ 134.065996] _tegra_set_vpr_params[123]: end
<3>[ 134.075465] vpr-heap: update vpr base to 0x00000000c6000000, size=6000000
<3>[ 134.082923] _tegra_set_vpr_params[120]: begin
<3>[ 134.113119] _tegra_set_vpr_params[123]: end
<3>[ 134.123448] vpr-heap: update vpr base to 0x00000000c6000000, size=4000000
<3>[ 134.130790] _tegra_set_vpr_params[120]: begin
<3>[ 134.162523] _tegra_set_vpr_params[123]: end
<3>[ 134.172413] vpr-heap: update vpr base to 0x00000000c6000000, size=2000000
<3>[ 134.179772] _tegra_set_vpr_params[120]: begin
<3>[ 134.209142] _tegra_set_vpr_params[123]: end

2) with MT_NON_CACHEABLE: 10ms ~ 18ms
<3>[ 102.108702] vpr-heap: update vpr base to 0x00000000c6000000, size=e000000
<3>[ 102.116296] _tegra_set_vpr_params[120]: begin
<3>[ 102.134272] _tegra_set_vpr_params[123]: end
<3>[ 102.145839] vpr-heap: update vpr base to 0x00000000c6000000, size=c000000
<3>[ 102.153226] _tegra_set_vpr_params[120]: begin
<3>[ 102.164201] _tegra_set_vpr_params[123]: end
<3>[ 102.172275] vpr-heap: update vpr base to 0x00000000c6000000, size=a000000
<3>[ 102.179638] _tegra_set_vpr_params[120]: begin
<3>[ 102.190342] _tegra_set_vpr_params[123]: end
<3>[ 102.197524] vpr-heap: update vpr base to 0x00000000c6000000, size=8000000
<3>[ 102.205085] _tegra_set_vpr_params[120]: begin
<3>[ 102.216112] _tegra_set_vpr_params[123]: end
<3>[ 102.224080] vpr-heap: update vpr base to 0x00000000c6000000, size=6000000
<3>[ 102.231387] _tegra_set_vpr_params[120]: begin
<3>[ 102.241775] _tegra_set_vpr_params[123]: end
<3>[ 102.248825] vpr-heap: update vpr base to 0x00000000c6000000, size=4000000
<3>[ 102.256069] _tegra_set_vpr_params[120]: begin
<3>[ 102.266368] _tegra_set_vpr_params[123]: end
<3>[ 102.273400] vpr-heap: update vpr base to 0x00000000c6000000, size=2000000
<3>[ 102.280672] _tegra_set_vpr_params[120]: begin
<3>[ 102.290929] _tegra_set_vpr_params[123]: end

Change-Id: I5f604064ce7b8b73ea9ad5860156ae5e2c6cc42a
Signed-off-by: Ken Chang <kenc@nvidia.com>

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