1 /* 2 * Copyright (C) 2018-2019, STMicroelectronics - All Rights Reserved 3 * 4 * SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <errno.h> 9 #include <stdint.h> 10 #include <stdio.h> 11 12 #include <libfdt.h> 13 14 #include <platform_def.h> 15 16 #include <arch.h> 17 #include <arch_helpers.h> 18 #include <common/debug.h> 19 #include <common/fdt_wrappers.h> 20 #include <drivers/delay_timer.h> 21 #include <drivers/generic_delay_timer.h> 22 #include <drivers/st/stm32mp_clkfunc.h> 23 #include <drivers/st/stm32mp1_clk.h> 24 #include <drivers/st/stm32mp1_rcc.h> 25 #include <dt-bindings/clock/stm32mp1-clksrc.h> 26 #include <lib/mmio.h> 27 #include <lib/spinlock.h> 28 #include <lib/utils_def.h> 29 #include <plat/common/platform.h> 30 31 #define MAX_HSI_HZ 64000000 32 #define USB_PHY_48_MHZ 48000000 33 34 #define TIMEOUT_US_200MS U(200000) 35 #define TIMEOUT_US_1S U(1000000) 36 37 #define PLLRDY_TIMEOUT TIMEOUT_US_200MS 38 #define CLKSRC_TIMEOUT TIMEOUT_US_200MS 39 #define CLKDIV_TIMEOUT TIMEOUT_US_200MS 40 #define HSIDIV_TIMEOUT TIMEOUT_US_200MS 41 #define OSCRDY_TIMEOUT TIMEOUT_US_1S 42 43 const char *stm32mp_osc_node_label[NB_OSC] = { 44 [_LSI] = "clk-lsi", 45 [_LSE] = "clk-lse", 46 [_HSI] = "clk-hsi", 47 [_HSE] = "clk-hse", 48 [_CSI] = "clk-csi", 49 [_I2S_CKIN] = "i2s_ckin", 50 }; 51 52 enum stm32mp1_parent_id { 53 /* Oscillators are defined in enum stm32mp_osc_id */ 54 55 /* Other parent source */ 56 _HSI_KER = NB_OSC, 57 _HSE_KER, 58 _HSE_KER_DIV2, 59 _CSI_KER, 60 _PLL1_P, 61 _PLL1_Q, 62 _PLL1_R, 63 _PLL2_P, 64 _PLL2_Q, 65 _PLL2_R, 66 _PLL3_P, 67 _PLL3_Q, 68 _PLL3_R, 69 _PLL4_P, 70 _PLL4_Q, 71 _PLL4_R, 72 _ACLK, 73 _PCLK1, 74 _PCLK2, 75 _PCLK3, 76 _PCLK4, 77 _PCLK5, 78 _HCLK6, 79 _HCLK2, 80 _CK_PER, 81 _CK_MPU, 82 _CK_MCU, 83 _USB_PHY_48, 84 _PARENT_NB, 85 _UNKNOWN_ID = 0xff, 86 }; 87 88 /* Lists only the parent clock we are interested in */ 89 enum stm32mp1_parent_sel { 90 _I2C12_SEL, 91 _I2C35_SEL, 92 _STGEN_SEL, 93 _I2C46_SEL, 94 _SPI6_SEL, 95 _UART1_SEL, 96 _RNG1_SEL, 97 _UART6_SEL, 98 _UART24_SEL, 99 _UART35_SEL, 100 _UART78_SEL, 101 _SDMMC12_SEL, 102 _SDMMC3_SEL, 103 _QSPI_SEL, 104 _FMC_SEL, 105 _AXIS_SEL, 106 _MCUS_SEL, 107 _USBPHY_SEL, 108 _USBO_SEL, 109 _MPU_SEL, 110 _PER_SEL, 111 _PARENT_SEL_NB, 112 _UNKNOWN_SEL = 0xff, 113 }; 114 115 /* State the parent clock ID straight related to a clock */ 116 static const uint8_t parent_id_clock_id[_PARENT_NB] = { 117 [_HSE] = CK_HSE, 118 [_HSI] = CK_HSI, 119 [_CSI] = CK_CSI, 120 [_LSE] = CK_LSE, 121 [_LSI] = CK_LSI, 122 [_I2S_CKIN] = _UNKNOWN_ID, 123 [_USB_PHY_48] = _UNKNOWN_ID, 124 [_HSI_KER] = CK_HSI, 125 [_HSE_KER] = CK_HSE, 126 [_HSE_KER_DIV2] = CK_HSE_DIV2, 127 [_CSI_KER] = CK_CSI, 128 [_PLL1_P] = PLL1_P, 129 [_PLL1_Q] = PLL1_Q, 130 [_PLL1_R] = PLL1_R, 131 [_PLL2_P] = PLL2_P, 132 [_PLL2_Q] = PLL2_Q, 133 [_PLL2_R] = PLL2_R, 134 [_PLL3_P] = PLL3_P, 135 [_PLL3_Q] = PLL3_Q, 136 [_PLL3_R] = PLL3_R, 137 [_PLL4_P] = PLL4_P, 138 [_PLL4_Q] = PLL4_Q, 139 [_PLL4_R] = PLL4_R, 140 [_ACLK] = CK_AXI, 141 [_PCLK1] = CK_AXI, 142 [_PCLK2] = CK_AXI, 143 [_PCLK3] = CK_AXI, 144 [_PCLK4] = CK_AXI, 145 [_PCLK5] = CK_AXI, 146 [_CK_PER] = CK_PER, 147 [_CK_MPU] = CK_MPU, 148 [_CK_MCU] = CK_MCU, 149 }; 150 151 static unsigned int clock_id2parent_id(unsigned long id) 152 { 153 unsigned int n; 154 155 for (n = 0U; n < ARRAY_SIZE(parent_id_clock_id); n++) { 156 if (parent_id_clock_id[n] == id) { 157 return n; 158 } 159 } 160 161 return _UNKNOWN_ID; 162 } 163 164 enum stm32mp1_pll_id { 165 _PLL1, 166 _PLL2, 167 _PLL3, 168 _PLL4, 169 _PLL_NB 170 }; 171 172 enum stm32mp1_div_id { 173 _DIV_P, 174 _DIV_Q, 175 _DIV_R, 176 _DIV_NB, 177 }; 178 179 enum stm32mp1_clksrc_id { 180 CLKSRC_MPU, 181 CLKSRC_AXI, 182 CLKSRC_MCU, 183 CLKSRC_PLL12, 184 CLKSRC_PLL3, 185 CLKSRC_PLL4, 186 CLKSRC_RTC, 187 CLKSRC_MCO1, 188 CLKSRC_MCO2, 189 CLKSRC_NB 190 }; 191 192 enum stm32mp1_clkdiv_id { 193 CLKDIV_MPU, 194 CLKDIV_AXI, 195 CLKDIV_MCU, 196 CLKDIV_APB1, 197 CLKDIV_APB2, 198 CLKDIV_APB3, 199 CLKDIV_APB4, 200 CLKDIV_APB5, 201 CLKDIV_RTC, 202 CLKDIV_MCO1, 203 CLKDIV_MCO2, 204 CLKDIV_NB 205 }; 206 207 enum stm32mp1_pllcfg { 208 PLLCFG_M, 209 PLLCFG_N, 210 PLLCFG_P, 211 PLLCFG_Q, 212 PLLCFG_R, 213 PLLCFG_O, 214 PLLCFG_NB 215 }; 216 217 enum stm32mp1_pllcsg { 218 PLLCSG_MOD_PER, 219 PLLCSG_INC_STEP, 220 PLLCSG_SSCG_MODE, 221 PLLCSG_NB 222 }; 223 224 enum stm32mp1_plltype { 225 PLL_800, 226 PLL_1600, 227 PLL_TYPE_NB 228 }; 229 230 struct stm32mp1_pll { 231 uint8_t refclk_min; 232 uint8_t refclk_max; 233 uint8_t divn_max; 234 }; 235 236 struct stm32mp1_clk_gate { 237 uint16_t offset; 238 uint8_t bit; 239 uint8_t index; 240 uint8_t set_clr; 241 uint8_t sel; /* Relates to enum stm32mp1_parent_sel */ 242 uint8_t fixed; /* Relates to enum stm32mp1_parent_id */ 243 }; 244 245 struct stm32mp1_clk_sel { 246 uint16_t offset; 247 uint8_t src; 248 uint8_t msk; 249 uint8_t nb_parent; 250 const uint8_t *parent; 251 }; 252 253 #define REFCLK_SIZE 4 254 struct stm32mp1_clk_pll { 255 enum stm32mp1_plltype plltype; 256 uint16_t rckxselr; 257 uint16_t pllxcfgr1; 258 uint16_t pllxcfgr2; 259 uint16_t pllxfracr; 260 uint16_t pllxcr; 261 uint16_t pllxcsgr; 262 enum stm32mp_osc_id refclk[REFCLK_SIZE]; 263 }; 264 265 /* Clocks with selectable source and non set/clr register access */ 266 #define _CLK_SELEC(off, b, idx, s) \ 267 { \ 268 .offset = (off), \ 269 .bit = (b), \ 270 .index = (idx), \ 271 .set_clr = 0, \ 272 .sel = (s), \ 273 .fixed = _UNKNOWN_ID, \ 274 } 275 276 /* Clocks with fixed source and non set/clr register access */ 277 #define _CLK_FIXED(off, b, idx, f) \ 278 { \ 279 .offset = (off), \ 280 .bit = (b), \ 281 .index = (idx), \ 282 .set_clr = 0, \ 283 .sel = _UNKNOWN_SEL, \ 284 .fixed = (f), \ 285 } 286 287 /* Clocks with selectable source and set/clr register access */ 288 #define _CLK_SC_SELEC(off, b, idx, s) \ 289 { \ 290 .offset = (off), \ 291 .bit = (b), \ 292 .index = (idx), \ 293 .set_clr = 1, \ 294 .sel = (s), \ 295 .fixed = _UNKNOWN_ID, \ 296 } 297 298 /* Clocks with fixed source and set/clr register access */ 299 #define _CLK_SC_FIXED(off, b, idx, f) \ 300 { \ 301 .offset = (off), \ 302 .bit = (b), \ 303 .index = (idx), \ 304 .set_clr = 1, \ 305 .sel = _UNKNOWN_SEL, \ 306 .fixed = (f), \ 307 } 308 309 #define _CLK_PARENT_SEL(_label, _rcc_selr, _parents) \ 310 [_ ## _label ## _SEL] = { \ 311 .offset = _rcc_selr, \ 312 .src = _rcc_selr ## _ ## _label ## SRC_SHIFT, \ 313 .msk = (_rcc_selr ## _ ## _label ## SRC_MASK) >> \ 314 (_rcc_selr ## _ ## _label ## SRC_SHIFT), \ 315 .parent = (_parents), \ 316 .nb_parent = ARRAY_SIZE(_parents) \ 317 } 318 319 #define _CLK_PLL(idx, type, off1, off2, off3, \ 320 off4, off5, off6, \ 321 p1, p2, p3, p4) \ 322 [(idx)] = { \ 323 .plltype = (type), \ 324 .rckxselr = (off1), \ 325 .pllxcfgr1 = (off2), \ 326 .pllxcfgr2 = (off3), \ 327 .pllxfracr = (off4), \ 328 .pllxcr = (off5), \ 329 .pllxcsgr = (off6), \ 330 .refclk[0] = (p1), \ 331 .refclk[1] = (p2), \ 332 .refclk[2] = (p3), \ 333 .refclk[3] = (p4), \ 334 } 335 336 #define NB_GATES ARRAY_SIZE(stm32mp1_clk_gate) 337 338 static const struct stm32mp1_clk_gate stm32mp1_clk_gate[] = { 339 _CLK_FIXED(RCC_DDRITFCR, 0, DDRC1, _ACLK), 340 _CLK_FIXED(RCC_DDRITFCR, 1, DDRC1LP, _ACLK), 341 _CLK_FIXED(RCC_DDRITFCR, 2, DDRC2, _ACLK), 342 _CLK_FIXED(RCC_DDRITFCR, 3, DDRC2LP, _ACLK), 343 _CLK_FIXED(RCC_DDRITFCR, 4, DDRPHYC, _PLL2_R), 344 _CLK_FIXED(RCC_DDRITFCR, 5, DDRPHYCLP, _PLL2_R), 345 _CLK_FIXED(RCC_DDRITFCR, 6, DDRCAPB, _PCLK4), 346 _CLK_FIXED(RCC_DDRITFCR, 7, DDRCAPBLP, _PCLK4), 347 _CLK_FIXED(RCC_DDRITFCR, 8, AXIDCG, _ACLK), 348 _CLK_FIXED(RCC_DDRITFCR, 9, DDRPHYCAPB, _PCLK4), 349 _CLK_FIXED(RCC_DDRITFCR, 10, DDRPHYCAPBLP, _PCLK4), 350 351 _CLK_SC_FIXED(RCC_MP_APB1ENSETR, 6, TIM12_K, _PCLK1), 352 _CLK_SC_SELEC(RCC_MP_APB1ENSETR, 14, USART2_K, _UART24_SEL), 353 _CLK_SC_SELEC(RCC_MP_APB1ENSETR, 15, USART3_K, _UART35_SEL), 354 _CLK_SC_SELEC(RCC_MP_APB1ENSETR, 16, UART4_K, _UART24_SEL), 355 _CLK_SC_SELEC(RCC_MP_APB1ENSETR, 17, UART5_K, _UART35_SEL), 356 _CLK_SC_SELEC(RCC_MP_APB1ENSETR, 18, UART7_K, _UART78_SEL), 357 _CLK_SC_SELEC(RCC_MP_APB1ENSETR, 19, UART8_K, _UART78_SEL), 358 _CLK_SC_SELEC(RCC_MP_APB1ENSETR, 21, I2C1_K, _I2C12_SEL), 359 _CLK_SC_SELEC(RCC_MP_APB1ENSETR, 22, I2C2_K, _I2C12_SEL), 360 _CLK_SC_SELEC(RCC_MP_APB1ENSETR, 23, I2C3_K, _I2C35_SEL), 361 _CLK_SC_SELEC(RCC_MP_APB1ENSETR, 24, I2C5_K, _I2C35_SEL), 362 363 _CLK_SC_FIXED(RCC_MP_APB2ENSETR, 2, TIM15_K, _PCLK2), 364 _CLK_SC_SELEC(RCC_MP_APB2ENSETR, 13, USART6_K, _UART6_SEL), 365 366 _CLK_SC_FIXED(RCC_MP_APB3ENSETR, 11, SYSCFG, _UNKNOWN_ID), 367 368 _CLK_SC_SELEC(RCC_MP_APB4ENSETR, 8, DDRPERFM, _UNKNOWN_SEL), 369 _CLK_SC_SELEC(RCC_MP_APB4ENSETR, 15, IWDG2, _UNKNOWN_SEL), 370 _CLK_SC_SELEC(RCC_MP_APB4ENSETR, 16, USBPHY_K, _USBPHY_SEL), 371 372 _CLK_SC_SELEC(RCC_MP_APB5ENSETR, 0, SPI6_K, _SPI6_SEL), 373 _CLK_SC_SELEC(RCC_MP_APB5ENSETR, 2, I2C4_K, _I2C46_SEL), 374 _CLK_SC_SELEC(RCC_MP_APB5ENSETR, 3, I2C6_K, _I2C46_SEL), 375 _CLK_SC_SELEC(RCC_MP_APB5ENSETR, 4, USART1_K, _UART1_SEL), 376 _CLK_SC_FIXED(RCC_MP_APB5ENSETR, 8, RTCAPB, _PCLK5), 377 _CLK_SC_FIXED(RCC_MP_APB5ENSETR, 11, TZC1, _PCLK5), 378 _CLK_SC_FIXED(RCC_MP_APB5ENSETR, 12, TZC2, _PCLK5), 379 _CLK_SC_FIXED(RCC_MP_APB5ENSETR, 13, TZPC, _PCLK5), 380 _CLK_SC_FIXED(RCC_MP_APB5ENSETR, 15, IWDG1, _PCLK5), 381 _CLK_SC_FIXED(RCC_MP_APB5ENSETR, 16, BSEC, _PCLK5), 382 _CLK_SC_SELEC(RCC_MP_APB5ENSETR, 20, STGEN_K, _STGEN_SEL), 383 384 _CLK_SC_SELEC(RCC_MP_AHB2ENSETR, 8, USBO_K, _USBO_SEL), 385 _CLK_SC_SELEC(RCC_MP_AHB2ENSETR, 16, SDMMC3_K, _SDMMC3_SEL), 386 387 _CLK_SC_SELEC(RCC_MP_AHB4ENSETR, 0, GPIOA, _UNKNOWN_SEL), 388 _CLK_SC_SELEC(RCC_MP_AHB4ENSETR, 1, GPIOB, _UNKNOWN_SEL), 389 _CLK_SC_SELEC(RCC_MP_AHB4ENSETR, 2, GPIOC, _UNKNOWN_SEL), 390 _CLK_SC_SELEC(RCC_MP_AHB4ENSETR, 3, GPIOD, _UNKNOWN_SEL), 391 _CLK_SC_SELEC(RCC_MP_AHB4ENSETR, 4, GPIOE, _UNKNOWN_SEL), 392 _CLK_SC_SELEC(RCC_MP_AHB4ENSETR, 5, GPIOF, _UNKNOWN_SEL), 393 _CLK_SC_SELEC(RCC_MP_AHB4ENSETR, 6, GPIOG, _UNKNOWN_SEL), 394 _CLK_SC_SELEC(RCC_MP_AHB4ENSETR, 7, GPIOH, _UNKNOWN_SEL), 395 _CLK_SC_SELEC(RCC_MP_AHB4ENSETR, 8, GPIOI, _UNKNOWN_SEL), 396 _CLK_SC_SELEC(RCC_MP_AHB4ENSETR, 9, GPIOJ, _UNKNOWN_SEL), 397 _CLK_SC_SELEC(RCC_MP_AHB4ENSETR, 10, GPIOK, _UNKNOWN_SEL), 398 399 _CLK_SC_FIXED(RCC_MP_AHB5ENSETR, 0, GPIOZ, _PCLK5), 400 _CLK_SC_FIXED(RCC_MP_AHB5ENSETR, 4, CRYP1, _PCLK5), 401 _CLK_SC_FIXED(RCC_MP_AHB5ENSETR, 5, HASH1, _PCLK5), 402 _CLK_SC_SELEC(RCC_MP_AHB5ENSETR, 6, RNG1_K, _RNG1_SEL), 403 _CLK_SC_FIXED(RCC_MP_AHB5ENSETR, 8, BKPSRAM, _PCLK5), 404 405 _CLK_SC_SELEC(RCC_MP_AHB6ENSETR, 12, FMC_K, _FMC_SEL), 406 _CLK_SC_SELEC(RCC_MP_AHB6ENSETR, 14, QSPI_K, _QSPI_SEL), 407 _CLK_SC_SELEC(RCC_MP_AHB6ENSETR, 16, SDMMC1_K, _SDMMC12_SEL), 408 _CLK_SC_SELEC(RCC_MP_AHB6ENSETR, 17, SDMMC2_K, _SDMMC12_SEL), 409 _CLK_SC_SELEC(RCC_MP_AHB6ENSETR, 24, USBH, _UNKNOWN_SEL), 410 411 _CLK_SELEC(RCC_DBGCFGR, 8, CK_DBG, _UNKNOWN_SEL), 412 }; 413 414 static const uint8_t i2c12_parents[] = { 415 _PCLK1, _PLL4_R, _HSI_KER, _CSI_KER 416 }; 417 418 static const uint8_t i2c35_parents[] = { 419 _PCLK1, _PLL4_R, _HSI_KER, _CSI_KER 420 }; 421 422 static const uint8_t stgen_parents[] = { 423 _HSI_KER, _HSE_KER 424 }; 425 426 static const uint8_t i2c46_parents[] = { 427 _PCLK5, _PLL3_Q, _HSI_KER, _CSI_KER 428 }; 429 430 static const uint8_t spi6_parents[] = { 431 _PCLK5, _PLL4_Q, _HSI_KER, _CSI_KER, _HSE_KER, _PLL3_Q 432 }; 433 434 static const uint8_t usart1_parents[] = { 435 _PCLK5, _PLL3_Q, _HSI_KER, _CSI_KER, _PLL4_Q, _HSE_KER 436 }; 437 438 static const uint8_t rng1_parents[] = { 439 _CSI, _PLL4_R, _LSE, _LSI 440 }; 441 442 static const uint8_t uart6_parents[] = { 443 _PCLK2, _PLL4_Q, _HSI_KER, _CSI_KER, _HSE_KER 444 }; 445 446 static const uint8_t uart234578_parents[] = { 447 _PCLK1, _PLL4_Q, _HSI_KER, _CSI_KER, _HSE_KER 448 }; 449 450 static const uint8_t sdmmc12_parents[] = { 451 _HCLK6, _PLL3_R, _PLL4_P, _HSI_KER 452 }; 453 454 static const uint8_t sdmmc3_parents[] = { 455 _HCLK2, _PLL3_R, _PLL4_P, _HSI_KER 456 }; 457 458 static const uint8_t qspi_parents[] = { 459 _ACLK, _PLL3_R, _PLL4_P, _CK_PER 460 }; 461 462 static const uint8_t fmc_parents[] = { 463 _ACLK, _PLL3_R, _PLL4_P, _CK_PER 464 }; 465 466 static const uint8_t ass_parents[] = { 467 _HSI, _HSE, _PLL2 468 }; 469 470 static const uint8_t mss_parents[] = { 471 _HSI, _HSE, _CSI, _PLL3 472 }; 473 474 static const uint8_t usbphy_parents[] = { 475 _HSE_KER, _PLL4_R, _HSE_KER_DIV2 476 }; 477 478 static const uint8_t usbo_parents[] = { 479 _PLL4_R, _USB_PHY_48 480 }; 481 482 static const uint8_t mpu_parents[] = { 483 _HSI, _HSE, _PLL1_P, _PLL1_P /* specific div */ 484 }; 485 486 static const uint8_t per_parents[] = { 487 _HSI, _HSE, _CSI, 488 }; 489 490 static const struct stm32mp1_clk_sel stm32mp1_clk_sel[_PARENT_SEL_NB] = { 491 _CLK_PARENT_SEL(I2C12, RCC_I2C12CKSELR, i2c12_parents), 492 _CLK_PARENT_SEL(I2C35, RCC_I2C35CKSELR, i2c35_parents), 493 _CLK_PARENT_SEL(STGEN, RCC_STGENCKSELR, stgen_parents), 494 _CLK_PARENT_SEL(I2C46, RCC_I2C46CKSELR, i2c46_parents), 495 _CLK_PARENT_SEL(SPI6, RCC_SPI6CKSELR, spi6_parents), 496 _CLK_PARENT_SEL(UART1, RCC_UART1CKSELR, usart1_parents), 497 _CLK_PARENT_SEL(RNG1, RCC_RNG1CKSELR, rng1_parents), 498 _CLK_PARENT_SEL(MPU, RCC_MPCKSELR, mpu_parents), 499 _CLK_PARENT_SEL(PER, RCC_CPERCKSELR, per_parents), 500 _CLK_PARENT_SEL(UART6, RCC_UART6CKSELR, uart6_parents), 501 _CLK_PARENT_SEL(UART24, RCC_UART24CKSELR, uart234578_parents), 502 _CLK_PARENT_SEL(UART35, RCC_UART35CKSELR, uart234578_parents), 503 _CLK_PARENT_SEL(UART78, RCC_UART78CKSELR, uart234578_parents), 504 _CLK_PARENT_SEL(SDMMC12, RCC_SDMMC12CKSELR, sdmmc12_parents), 505 _CLK_PARENT_SEL(SDMMC3, RCC_SDMMC3CKSELR, sdmmc3_parents), 506 _CLK_PARENT_SEL(QSPI, RCC_QSPICKSELR, qspi_parents), 507 _CLK_PARENT_SEL(FMC, RCC_FMCCKSELR, fmc_parents), 508 _CLK_PARENT_SEL(AXIS, RCC_ASSCKSELR, ass_parents), 509 _CLK_PARENT_SEL(MCUS, RCC_MSSCKSELR, mss_parents), 510 _CLK_PARENT_SEL(USBPHY, RCC_USBCKSELR, usbphy_parents), 511 _CLK_PARENT_SEL(USBO, RCC_USBCKSELR, usbo_parents), 512 }; 513 514 /* Define characteristic of PLL according type */ 515 #define DIVN_MIN 24 516 static const struct stm32mp1_pll stm32mp1_pll[PLL_TYPE_NB] = { 517 [PLL_800] = { 518 .refclk_min = 4, 519 .refclk_max = 16, 520 .divn_max = 99, 521 }, 522 [PLL_1600] = { 523 .refclk_min = 8, 524 .refclk_max = 16, 525 .divn_max = 199, 526 }, 527 }; 528 529 /* PLLNCFGR2 register divider by output */ 530 static const uint8_t pllncfgr2[_DIV_NB] = { 531 [_DIV_P] = RCC_PLLNCFGR2_DIVP_SHIFT, 532 [_DIV_Q] = RCC_PLLNCFGR2_DIVQ_SHIFT, 533 [_DIV_R] = RCC_PLLNCFGR2_DIVR_SHIFT, 534 }; 535 536 static const struct stm32mp1_clk_pll stm32mp1_clk_pll[_PLL_NB] = { 537 _CLK_PLL(_PLL1, PLL_1600, 538 RCC_RCK12SELR, RCC_PLL1CFGR1, RCC_PLL1CFGR2, 539 RCC_PLL1FRACR, RCC_PLL1CR, RCC_PLL1CSGR, 540 _HSI, _HSE, _UNKNOWN_OSC_ID, _UNKNOWN_OSC_ID), 541 _CLK_PLL(_PLL2, PLL_1600, 542 RCC_RCK12SELR, RCC_PLL2CFGR1, RCC_PLL2CFGR2, 543 RCC_PLL2FRACR, RCC_PLL2CR, RCC_PLL2CSGR, 544 _HSI, _HSE, _UNKNOWN_OSC_ID, _UNKNOWN_OSC_ID), 545 _CLK_PLL(_PLL3, PLL_800, 546 RCC_RCK3SELR, RCC_PLL3CFGR1, RCC_PLL3CFGR2, 547 RCC_PLL3FRACR, RCC_PLL3CR, RCC_PLL3CSGR, 548 _HSI, _HSE, _CSI, _UNKNOWN_OSC_ID), 549 _CLK_PLL(_PLL4, PLL_800, 550 RCC_RCK4SELR, RCC_PLL4CFGR1, RCC_PLL4CFGR2, 551 RCC_PLL4FRACR, RCC_PLL4CR, RCC_PLL4CSGR, 552 _HSI, _HSE, _CSI, _I2S_CKIN), 553 }; 554 555 /* Prescaler table lookups for clock computation */ 556 /* div = /1 /2 /4 /8 / 16 /64 /128 /512 */ 557 static const uint8_t stm32mp1_mcu_div[16] = { 558 0, 1, 2, 3, 4, 6, 7, 8, 9, 9, 9, 9, 9, 9, 9, 9 559 }; 560 561 /* div = /1 /2 /4 /8 /16 : same divider for PMU and APBX */ 562 #define stm32mp1_mpu_div stm32mp1_mpu_apbx_div 563 #define stm32mp1_apbx_div stm32mp1_mpu_apbx_div 564 static const uint8_t stm32mp1_mpu_apbx_div[8] = { 565 0, 1, 2, 3, 4, 4, 4, 4 566 }; 567 568 /* div = /1 /2 /3 /4 */ 569 static const uint8_t stm32mp1_axi_div[8] = { 570 1, 2, 3, 4, 4, 4, 4, 4 571 }; 572 573 /* RCC clock device driver private */ 574 static unsigned long stm32mp1_osc[NB_OSC]; 575 static struct spinlock reg_lock; 576 static unsigned int gate_refcounts[NB_GATES]; 577 static struct spinlock refcount_lock; 578 579 static const struct stm32mp1_clk_gate *gate_ref(unsigned int idx) 580 { 581 return &stm32mp1_clk_gate[idx]; 582 } 583 584 static const struct stm32mp1_clk_sel *clk_sel_ref(unsigned int idx) 585 { 586 return &stm32mp1_clk_sel[idx]; 587 } 588 589 static const struct stm32mp1_clk_pll *pll_ref(unsigned int idx) 590 { 591 return &stm32mp1_clk_pll[idx]; 592 } 593 594 static void stm32mp1_clk_lock(struct spinlock *lock) 595 { 596 if (stm32mp_lock_available()) { 597 /* Assume interrupts are masked */ 598 spin_lock(lock); 599 } 600 } 601 602 static void stm32mp1_clk_unlock(struct spinlock *lock) 603 { 604 if (stm32mp_lock_available()) { 605 spin_unlock(lock); 606 } 607 } 608 609 bool stm32mp1_rcc_is_secure(void) 610 { 611 uintptr_t rcc_base = stm32mp_rcc_base(); 612 613 return (mmio_read_32(rcc_base + RCC_TZCR) & RCC_TZCR_TZEN) != 0; 614 } 615 616 bool stm32mp1_rcc_is_mckprot(void) 617 { 618 uintptr_t rcc_base = stm32mp_rcc_base(); 619 620 return (mmio_read_32(rcc_base + RCC_TZCR) & RCC_TZCR_MCKPROT) != 0; 621 } 622 623 void stm32mp1_clk_rcc_regs_lock(void) 624 { 625 stm32mp1_clk_lock(®_lock); 626 } 627 628 void stm32mp1_clk_rcc_regs_unlock(void) 629 { 630 stm32mp1_clk_unlock(®_lock); 631 } 632 633 static unsigned long stm32mp1_clk_get_fixed(enum stm32mp_osc_id idx) 634 { 635 if (idx >= NB_OSC) { 636 return 0; 637 } 638 639 return stm32mp1_osc[idx]; 640 } 641 642 static int stm32mp1_clk_get_gated_id(unsigned long id) 643 { 644 unsigned int i; 645 646 for (i = 0U; i < NB_GATES; i++) { 647 if (gate_ref(i)->index == id) { 648 return i; 649 } 650 } 651 652 ERROR("%s: clk id %d not found\n", __func__, (uint32_t)id); 653 654 return -EINVAL; 655 } 656 657 static enum stm32mp1_parent_sel stm32mp1_clk_get_sel(int i) 658 { 659 return (enum stm32mp1_parent_sel)(gate_ref(i)->sel); 660 } 661 662 static enum stm32mp1_parent_id stm32mp1_clk_get_fixed_parent(int i) 663 { 664 return (enum stm32mp1_parent_id)(gate_ref(i)->fixed); 665 } 666 667 static int stm32mp1_clk_get_parent(unsigned long id) 668 { 669 const struct stm32mp1_clk_sel *sel; 670 uint32_t p_sel; 671 int i; 672 enum stm32mp1_parent_id p; 673 enum stm32mp1_parent_sel s; 674 uintptr_t rcc_base = stm32mp_rcc_base(); 675 676 /* Few non gateable clock have a static parent ID, find them */ 677 i = (int)clock_id2parent_id(id); 678 if (i != _UNKNOWN_ID) { 679 return i; 680 } 681 682 i = stm32mp1_clk_get_gated_id(id); 683 if (i < 0) { 684 panic(); 685 } 686 687 p = stm32mp1_clk_get_fixed_parent(i); 688 if (p < _PARENT_NB) { 689 return (int)p; 690 } 691 692 s = stm32mp1_clk_get_sel(i); 693 if (s == _UNKNOWN_SEL) { 694 return -EINVAL; 695 } 696 if (s >= _PARENT_SEL_NB) { 697 panic(); 698 } 699 700 sel = clk_sel_ref(s); 701 p_sel = (mmio_read_32(rcc_base + sel->offset) & 702 (sel->msk << sel->src)) >> sel->src; 703 if (p_sel < sel->nb_parent) { 704 return (int)sel->parent[p_sel]; 705 } 706 707 return -EINVAL; 708 } 709 710 static unsigned long stm32mp1_pll_get_fref(const struct stm32mp1_clk_pll *pll) 711 { 712 uint32_t selr = mmio_read_32(stm32mp_rcc_base() + pll->rckxselr); 713 uint32_t src = selr & RCC_SELR_REFCLK_SRC_MASK; 714 715 return stm32mp1_clk_get_fixed(pll->refclk[src]); 716 } 717 718 /* 719 * pll_get_fvco() : return the VCO or (VCO / 2) frequency for the requested PLL 720 * - PLL1 & PLL2 => return VCO / 2 with Fpll_y_ck = FVCO / 2 * (DIVy + 1) 721 * - PLL3 & PLL4 => return VCO with Fpll_y_ck = FVCO / (DIVy + 1) 722 * => in all cases Fpll_y_ck = pll_get_fvco() / (DIVy + 1) 723 */ 724 static unsigned long stm32mp1_pll_get_fvco(const struct stm32mp1_clk_pll *pll) 725 { 726 unsigned long refclk, fvco; 727 uint32_t cfgr1, fracr, divm, divn; 728 uintptr_t rcc_base = stm32mp_rcc_base(); 729 730 cfgr1 = mmio_read_32(rcc_base + pll->pllxcfgr1); 731 fracr = mmio_read_32(rcc_base + pll->pllxfracr); 732 733 divm = (cfgr1 & (RCC_PLLNCFGR1_DIVM_MASK)) >> RCC_PLLNCFGR1_DIVM_SHIFT; 734 divn = cfgr1 & RCC_PLLNCFGR1_DIVN_MASK; 735 736 refclk = stm32mp1_pll_get_fref(pll); 737 738 /* 739 * With FRACV : 740 * Fvco = Fck_ref * ((DIVN + 1) + FRACV / 2^13) / (DIVM + 1) 741 * Without FRACV 742 * Fvco = Fck_ref * ((DIVN + 1) / (DIVM + 1) 743 */ 744 if ((fracr & RCC_PLLNFRACR_FRACLE) != 0U) { 745 uint32_t fracv = (fracr & RCC_PLLNFRACR_FRACV_MASK) >> 746 RCC_PLLNFRACR_FRACV_SHIFT; 747 unsigned long long numerator, denominator; 748 749 numerator = (((unsigned long long)divn + 1U) << 13) + fracv; 750 numerator = refclk * numerator; 751 denominator = ((unsigned long long)divm + 1U) << 13; 752 fvco = (unsigned long)(numerator / denominator); 753 } else { 754 fvco = (unsigned long)(refclk * (divn + 1U) / (divm + 1U)); 755 } 756 757 return fvco; 758 } 759 760 static unsigned long stm32mp1_read_pll_freq(enum stm32mp1_pll_id pll_id, 761 enum stm32mp1_div_id div_id) 762 { 763 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id); 764 unsigned long dfout; 765 uint32_t cfgr2, divy; 766 767 if (div_id >= _DIV_NB) { 768 return 0; 769 } 770 771 cfgr2 = mmio_read_32(stm32mp_rcc_base() + pll->pllxcfgr2); 772 divy = (cfgr2 >> pllncfgr2[div_id]) & RCC_PLLNCFGR2_DIVX_MASK; 773 774 dfout = stm32mp1_pll_get_fvco(pll) / (divy + 1U); 775 776 return dfout; 777 } 778 779 static unsigned long get_clock_rate(int p) 780 { 781 uint32_t reg, clkdiv; 782 unsigned long clock = 0; 783 uintptr_t rcc_base = stm32mp_rcc_base(); 784 785 switch (p) { 786 case _CK_MPU: 787 /* MPU sub system */ 788 reg = mmio_read_32(rcc_base + RCC_MPCKSELR); 789 switch (reg & RCC_SELR_SRC_MASK) { 790 case RCC_MPCKSELR_HSI: 791 clock = stm32mp1_clk_get_fixed(_HSI); 792 break; 793 case RCC_MPCKSELR_HSE: 794 clock = stm32mp1_clk_get_fixed(_HSE); 795 break; 796 case RCC_MPCKSELR_PLL: 797 clock = stm32mp1_read_pll_freq(_PLL1, _DIV_P); 798 break; 799 case RCC_MPCKSELR_PLL_MPUDIV: 800 clock = stm32mp1_read_pll_freq(_PLL1, _DIV_P); 801 802 reg = mmio_read_32(rcc_base + RCC_MPCKDIVR); 803 clkdiv = reg & RCC_MPUDIV_MASK; 804 if (clkdiv != 0U) { 805 clock /= stm32mp1_mpu_div[clkdiv]; 806 } 807 break; 808 default: 809 break; 810 } 811 break; 812 /* AXI sub system */ 813 case _ACLK: 814 case _HCLK2: 815 case _HCLK6: 816 case _PCLK4: 817 case _PCLK5: 818 reg = mmio_read_32(rcc_base + RCC_ASSCKSELR); 819 switch (reg & RCC_SELR_SRC_MASK) { 820 case RCC_ASSCKSELR_HSI: 821 clock = stm32mp1_clk_get_fixed(_HSI); 822 break; 823 case RCC_ASSCKSELR_HSE: 824 clock = stm32mp1_clk_get_fixed(_HSE); 825 break; 826 case RCC_ASSCKSELR_PLL: 827 clock = stm32mp1_read_pll_freq(_PLL2, _DIV_P); 828 break; 829 default: 830 break; 831 } 832 833 /* System clock divider */ 834 reg = mmio_read_32(rcc_base + RCC_AXIDIVR); 835 clock /= stm32mp1_axi_div[reg & RCC_AXIDIV_MASK]; 836 837 switch (p) { 838 case _PCLK4: 839 reg = mmio_read_32(rcc_base + RCC_APB4DIVR); 840 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK]; 841 break; 842 case _PCLK5: 843 reg = mmio_read_32(rcc_base + RCC_APB5DIVR); 844 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK]; 845 break; 846 default: 847 break; 848 } 849 break; 850 /* MCU sub system */ 851 case _CK_MCU: 852 case _PCLK1: 853 case _PCLK2: 854 case _PCLK3: 855 reg = mmio_read_32(rcc_base + RCC_MSSCKSELR); 856 switch (reg & RCC_SELR_SRC_MASK) { 857 case RCC_MSSCKSELR_HSI: 858 clock = stm32mp1_clk_get_fixed(_HSI); 859 break; 860 case RCC_MSSCKSELR_HSE: 861 clock = stm32mp1_clk_get_fixed(_HSE); 862 break; 863 case RCC_MSSCKSELR_CSI: 864 clock = stm32mp1_clk_get_fixed(_CSI); 865 break; 866 case RCC_MSSCKSELR_PLL: 867 clock = stm32mp1_read_pll_freq(_PLL3, _DIV_P); 868 break; 869 default: 870 break; 871 } 872 873 /* MCU clock divider */ 874 reg = mmio_read_32(rcc_base + RCC_MCUDIVR); 875 clock >>= stm32mp1_mcu_div[reg & RCC_MCUDIV_MASK]; 876 877 switch (p) { 878 case _PCLK1: 879 reg = mmio_read_32(rcc_base + RCC_APB1DIVR); 880 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK]; 881 break; 882 case _PCLK2: 883 reg = mmio_read_32(rcc_base + RCC_APB2DIVR); 884 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK]; 885 break; 886 case _PCLK3: 887 reg = mmio_read_32(rcc_base + RCC_APB3DIVR); 888 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK]; 889 break; 890 case _CK_MCU: 891 default: 892 break; 893 } 894 break; 895 case _CK_PER: 896 reg = mmio_read_32(rcc_base + RCC_CPERCKSELR); 897 switch (reg & RCC_SELR_SRC_MASK) { 898 case RCC_CPERCKSELR_HSI: 899 clock = stm32mp1_clk_get_fixed(_HSI); 900 break; 901 case RCC_CPERCKSELR_HSE: 902 clock = stm32mp1_clk_get_fixed(_HSE); 903 break; 904 case RCC_CPERCKSELR_CSI: 905 clock = stm32mp1_clk_get_fixed(_CSI); 906 break; 907 default: 908 break; 909 } 910 break; 911 case _HSI: 912 case _HSI_KER: 913 clock = stm32mp1_clk_get_fixed(_HSI); 914 break; 915 case _CSI: 916 case _CSI_KER: 917 clock = stm32mp1_clk_get_fixed(_CSI); 918 break; 919 case _HSE: 920 case _HSE_KER: 921 clock = stm32mp1_clk_get_fixed(_HSE); 922 break; 923 case _HSE_KER_DIV2: 924 clock = stm32mp1_clk_get_fixed(_HSE) >> 1; 925 break; 926 case _LSI: 927 clock = stm32mp1_clk_get_fixed(_LSI); 928 break; 929 case _LSE: 930 clock = stm32mp1_clk_get_fixed(_LSE); 931 break; 932 /* PLL */ 933 case _PLL1_P: 934 clock = stm32mp1_read_pll_freq(_PLL1, _DIV_P); 935 break; 936 case _PLL1_Q: 937 clock = stm32mp1_read_pll_freq(_PLL1, _DIV_Q); 938 break; 939 case _PLL1_R: 940 clock = stm32mp1_read_pll_freq(_PLL1, _DIV_R); 941 break; 942 case _PLL2_P: 943 clock = stm32mp1_read_pll_freq(_PLL2, _DIV_P); 944 break; 945 case _PLL2_Q: 946 clock = stm32mp1_read_pll_freq(_PLL2, _DIV_Q); 947 break; 948 case _PLL2_R: 949 clock = stm32mp1_read_pll_freq(_PLL2, _DIV_R); 950 break; 951 case _PLL3_P: 952 clock = stm32mp1_read_pll_freq(_PLL3, _DIV_P); 953 break; 954 case _PLL3_Q: 955 clock = stm32mp1_read_pll_freq(_PLL3, _DIV_Q); 956 break; 957 case _PLL3_R: 958 clock = stm32mp1_read_pll_freq(_PLL3, _DIV_R); 959 break; 960 case _PLL4_P: 961 clock = stm32mp1_read_pll_freq(_PLL4, _DIV_P); 962 break; 963 case _PLL4_Q: 964 clock = stm32mp1_read_pll_freq(_PLL4, _DIV_Q); 965 break; 966 case _PLL4_R: 967 clock = stm32mp1_read_pll_freq(_PLL4, _DIV_R); 968 break; 969 /* Other */ 970 case _USB_PHY_48: 971 clock = USB_PHY_48_MHZ; 972 break; 973 default: 974 break; 975 } 976 977 return clock; 978 } 979 980 static void __clk_enable(struct stm32mp1_clk_gate const *gate) 981 { 982 uintptr_t rcc_base = stm32mp_rcc_base(); 983 984 if (gate->set_clr != 0U) { 985 mmio_write_32(rcc_base + gate->offset, BIT(gate->bit)); 986 } else { 987 mmio_setbits_32(rcc_base + gate->offset, BIT(gate->bit)); 988 } 989 990 VERBOSE("Clock %d has been enabled", gate->index); 991 } 992 993 static void __clk_disable(struct stm32mp1_clk_gate const *gate) 994 { 995 uintptr_t rcc_base = stm32mp_rcc_base(); 996 997 if (gate->set_clr != 0U) { 998 mmio_write_32(rcc_base + gate->offset + RCC_MP_ENCLRR_OFFSET, 999 BIT(gate->bit)); 1000 } else { 1001 mmio_clrbits_32(rcc_base + gate->offset, BIT(gate->bit)); 1002 } 1003 1004 VERBOSE("Clock %d has been disabled", gate->index); 1005 } 1006 1007 static bool __clk_is_enabled(struct stm32mp1_clk_gate const *gate) 1008 { 1009 uintptr_t rcc_base = stm32mp_rcc_base(); 1010 1011 return mmio_read_32(rcc_base + gate->offset) & BIT(gate->bit); 1012 } 1013 1014 unsigned int stm32mp1_clk_get_refcount(unsigned long id) 1015 { 1016 int i = stm32mp1_clk_get_gated_id(id); 1017 1018 if (i < 0) { 1019 panic(); 1020 } 1021 1022 return gate_refcounts[i]; 1023 } 1024 1025 void __stm32mp1_clk_enable(unsigned long id, bool secure) 1026 { 1027 const struct stm32mp1_clk_gate *gate; 1028 int i = stm32mp1_clk_get_gated_id(id); 1029 unsigned int *refcnt; 1030 1031 if (i < 0) { 1032 ERROR("Clock %d can't be enabled\n", (uint32_t)id); 1033 panic(); 1034 } 1035 1036 gate = gate_ref(i); 1037 refcnt = &gate_refcounts[i]; 1038 1039 stm32mp1_clk_lock(&refcount_lock); 1040 1041 if (stm32mp_incr_shrefcnt(refcnt, secure) != 0) { 1042 __clk_enable(gate); 1043 } 1044 1045 stm32mp1_clk_unlock(&refcount_lock); 1046 } 1047 1048 void __stm32mp1_clk_disable(unsigned long id, bool secure) 1049 { 1050 const struct stm32mp1_clk_gate *gate; 1051 int i = stm32mp1_clk_get_gated_id(id); 1052 unsigned int *refcnt; 1053 1054 if (i < 0) { 1055 ERROR("Clock %d can't be disabled\n", (uint32_t)id); 1056 panic(); 1057 } 1058 1059 gate = gate_ref(i); 1060 refcnt = &gate_refcounts[i]; 1061 1062 stm32mp1_clk_lock(&refcount_lock); 1063 1064 if (stm32mp_decr_shrefcnt(refcnt, secure) != 0) { 1065 __clk_disable(gate); 1066 } 1067 1068 stm32mp1_clk_unlock(&refcount_lock); 1069 } 1070 1071 void stm32mp_clk_enable(unsigned long id) 1072 { 1073 __stm32mp1_clk_enable(id, true); 1074 } 1075 1076 void stm32mp_clk_disable(unsigned long id) 1077 { 1078 __stm32mp1_clk_disable(id, true); 1079 } 1080 1081 bool stm32mp_clk_is_enabled(unsigned long id) 1082 { 1083 int i = stm32mp1_clk_get_gated_id(id); 1084 1085 if (i < 0) { 1086 panic(); 1087 } 1088 1089 return __clk_is_enabled(gate_ref(i)); 1090 } 1091 1092 unsigned long stm32mp_clk_get_rate(unsigned long id) 1093 { 1094 int p = stm32mp1_clk_get_parent(id); 1095 1096 if (p < 0) { 1097 return 0; 1098 } 1099 1100 return get_clock_rate(p); 1101 } 1102 1103 static void stm32mp1_ls_osc_set(bool enable, uint32_t offset, uint32_t mask_on) 1104 { 1105 uintptr_t address = stm32mp_rcc_base() + offset; 1106 1107 if (enable) { 1108 mmio_setbits_32(address, mask_on); 1109 } else { 1110 mmio_clrbits_32(address, mask_on); 1111 } 1112 } 1113 1114 static void stm32mp1_hs_ocs_set(bool enable, uint32_t mask_on) 1115 { 1116 uint32_t offset = enable ? RCC_OCENSETR : RCC_OCENCLRR; 1117 uintptr_t address = stm32mp_rcc_base() + offset; 1118 1119 mmio_write_32(address, mask_on); 1120 } 1121 1122 static int stm32mp1_osc_wait(bool enable, uint32_t offset, uint32_t mask_rdy) 1123 { 1124 uint64_t timeout; 1125 uint32_t mask_test; 1126 uintptr_t address = stm32mp_rcc_base() + offset; 1127 1128 if (enable) { 1129 mask_test = mask_rdy; 1130 } else { 1131 mask_test = 0; 1132 } 1133 1134 timeout = timeout_init_us(OSCRDY_TIMEOUT); 1135 while ((mmio_read_32(address) & mask_rdy) != mask_test) { 1136 if (timeout_elapsed(timeout)) { 1137 ERROR("OSC %x @ %lx timeout for enable=%d : 0x%x\n", 1138 mask_rdy, address, enable, mmio_read_32(address)); 1139 return -ETIMEDOUT; 1140 } 1141 } 1142 1143 return 0; 1144 } 1145 1146 static void stm32mp1_lse_enable(bool bypass, bool digbyp, uint32_t lsedrv) 1147 { 1148 uint32_t value; 1149 uintptr_t rcc_base = stm32mp_rcc_base(); 1150 1151 if (digbyp) { 1152 mmio_setbits_32(rcc_base + RCC_BDCR, RCC_BDCR_DIGBYP); 1153 } 1154 1155 if (bypass || digbyp) { 1156 mmio_setbits_32(rcc_base + RCC_BDCR, RCC_BDCR_LSEBYP); 1157 } 1158 1159 /* 1160 * Warning: not recommended to switch directly from "high drive" 1161 * to "medium low drive", and vice-versa. 1162 */ 1163 value = (mmio_read_32(rcc_base + RCC_BDCR) & RCC_BDCR_LSEDRV_MASK) >> 1164 RCC_BDCR_LSEDRV_SHIFT; 1165 1166 while (value != lsedrv) { 1167 if (value > lsedrv) { 1168 value--; 1169 } else { 1170 value++; 1171 } 1172 1173 mmio_clrsetbits_32(rcc_base + RCC_BDCR, 1174 RCC_BDCR_LSEDRV_MASK, 1175 value << RCC_BDCR_LSEDRV_SHIFT); 1176 } 1177 1178 stm32mp1_ls_osc_set(true, RCC_BDCR, RCC_BDCR_LSEON); 1179 } 1180 1181 static void stm32mp1_lse_wait(void) 1182 { 1183 if (stm32mp1_osc_wait(true, RCC_BDCR, RCC_BDCR_LSERDY) != 0) { 1184 VERBOSE("%s: failed\n", __func__); 1185 } 1186 } 1187 1188 static void stm32mp1_lsi_set(bool enable) 1189 { 1190 stm32mp1_ls_osc_set(enable, RCC_RDLSICR, RCC_RDLSICR_LSION); 1191 1192 if (stm32mp1_osc_wait(enable, RCC_RDLSICR, RCC_RDLSICR_LSIRDY) != 0) { 1193 VERBOSE("%s: failed\n", __func__); 1194 } 1195 } 1196 1197 static void stm32mp1_hse_enable(bool bypass, bool digbyp, bool css) 1198 { 1199 uintptr_t rcc_base = stm32mp_rcc_base(); 1200 1201 if (digbyp) { 1202 mmio_write_32(rcc_base + RCC_OCENSETR, RCC_OCENR_DIGBYP); 1203 } 1204 1205 if (bypass || digbyp) { 1206 mmio_write_32(rcc_base + RCC_OCENSETR, RCC_OCENR_HSEBYP); 1207 } 1208 1209 stm32mp1_hs_ocs_set(true, RCC_OCENR_HSEON); 1210 if (stm32mp1_osc_wait(true, RCC_OCRDYR, RCC_OCRDYR_HSERDY) != 0) { 1211 VERBOSE("%s: failed\n", __func__); 1212 } 1213 1214 if (css) { 1215 mmio_write_32(rcc_base + RCC_OCENSETR, RCC_OCENR_HSECSSON); 1216 } 1217 } 1218 1219 static void stm32mp1_csi_set(bool enable) 1220 { 1221 stm32mp1_hs_ocs_set(enable, RCC_OCENR_CSION); 1222 if (stm32mp1_osc_wait(enable, RCC_OCRDYR, RCC_OCRDYR_CSIRDY) != 0) { 1223 VERBOSE("%s: failed\n", __func__); 1224 } 1225 } 1226 1227 static void stm32mp1_hsi_set(bool enable) 1228 { 1229 stm32mp1_hs_ocs_set(enable, RCC_OCENR_HSION); 1230 if (stm32mp1_osc_wait(enable, RCC_OCRDYR, RCC_OCRDYR_HSIRDY) != 0) { 1231 VERBOSE("%s: failed\n", __func__); 1232 } 1233 } 1234 1235 static int stm32mp1_set_hsidiv(uint8_t hsidiv) 1236 { 1237 uint64_t timeout; 1238 uintptr_t rcc_base = stm32mp_rcc_base(); 1239 uintptr_t address = rcc_base + RCC_OCRDYR; 1240 1241 mmio_clrsetbits_32(rcc_base + RCC_HSICFGR, 1242 RCC_HSICFGR_HSIDIV_MASK, 1243 RCC_HSICFGR_HSIDIV_MASK & (uint32_t)hsidiv); 1244 1245 timeout = timeout_init_us(HSIDIV_TIMEOUT); 1246 while ((mmio_read_32(address) & RCC_OCRDYR_HSIDIVRDY) == 0U) { 1247 if (timeout_elapsed(timeout)) { 1248 ERROR("HSIDIV failed @ 0x%lx: 0x%x\n", 1249 address, mmio_read_32(address)); 1250 return -ETIMEDOUT; 1251 } 1252 } 1253 1254 return 0; 1255 } 1256 1257 static int stm32mp1_hsidiv(unsigned long hsifreq) 1258 { 1259 uint8_t hsidiv; 1260 uint32_t hsidivfreq = MAX_HSI_HZ; 1261 1262 for (hsidiv = 0; hsidiv < 4U; hsidiv++) { 1263 if (hsidivfreq == hsifreq) { 1264 break; 1265 } 1266 1267 hsidivfreq /= 2U; 1268 } 1269 1270 if (hsidiv == 4U) { 1271 ERROR("Invalid clk-hsi frequency\n"); 1272 return -1; 1273 } 1274 1275 if (hsidiv != 0U) { 1276 return stm32mp1_set_hsidiv(hsidiv); 1277 } 1278 1279 return 0; 1280 } 1281 1282 static bool stm32mp1_check_pll_conf(enum stm32mp1_pll_id pll_id, 1283 unsigned int clksrc, 1284 uint32_t *pllcfg, int plloff) 1285 { 1286 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id); 1287 uintptr_t rcc_base = stm32mp_rcc_base(); 1288 uintptr_t pllxcr = rcc_base + pll->pllxcr; 1289 enum stm32mp1_plltype type = pll->plltype; 1290 uintptr_t clksrc_address = rcc_base + (clksrc >> 4); 1291 unsigned long refclk; 1292 uint32_t ifrge = 0U; 1293 uint32_t src, value, fracv = 0; 1294 void *fdt; 1295 1296 /* Check PLL output */ 1297 if (mmio_read_32(pllxcr) != RCC_PLLNCR_PLLON) { 1298 return false; 1299 } 1300 1301 /* Check current clksrc */ 1302 src = mmio_read_32(clksrc_address) & RCC_SELR_SRC_MASK; 1303 if (src != (clksrc & RCC_SELR_SRC_MASK)) { 1304 return false; 1305 } 1306 1307 /* Check Div */ 1308 src = mmio_read_32(rcc_base + pll->rckxselr) & RCC_SELR_REFCLK_SRC_MASK; 1309 1310 refclk = stm32mp1_clk_get_fixed(pll->refclk[src]) / 1311 (pllcfg[PLLCFG_M] + 1U); 1312 1313 if ((refclk < (stm32mp1_pll[type].refclk_min * 1000000U)) || 1314 (refclk > (stm32mp1_pll[type].refclk_max * 1000000U))) { 1315 return false; 1316 } 1317 1318 if ((type == PLL_800) && (refclk >= 8000000U)) { 1319 ifrge = 1U; 1320 } 1321 1322 value = (pllcfg[PLLCFG_N] << RCC_PLLNCFGR1_DIVN_SHIFT) & 1323 RCC_PLLNCFGR1_DIVN_MASK; 1324 value |= (pllcfg[PLLCFG_M] << RCC_PLLNCFGR1_DIVM_SHIFT) & 1325 RCC_PLLNCFGR1_DIVM_MASK; 1326 value |= (ifrge << RCC_PLLNCFGR1_IFRGE_SHIFT) & 1327 RCC_PLLNCFGR1_IFRGE_MASK; 1328 if (mmio_read_32(rcc_base + pll->pllxcfgr1) != value) { 1329 return false; 1330 } 1331 1332 /* Fractional configuration */ 1333 if (fdt_get_address(&fdt) == 1) { 1334 fracv = fdt_read_uint32_default(fdt, plloff, "frac", 0); 1335 } 1336 1337 value = fracv << RCC_PLLNFRACR_FRACV_SHIFT; 1338 value |= RCC_PLLNFRACR_FRACLE; 1339 if (mmio_read_32(rcc_base + pll->pllxfracr) != value) { 1340 return false; 1341 } 1342 1343 /* Output config */ 1344 value = (pllcfg[PLLCFG_P] << RCC_PLLNCFGR2_DIVP_SHIFT) & 1345 RCC_PLLNCFGR2_DIVP_MASK; 1346 value |= (pllcfg[PLLCFG_Q] << RCC_PLLNCFGR2_DIVQ_SHIFT) & 1347 RCC_PLLNCFGR2_DIVQ_MASK; 1348 value |= (pllcfg[PLLCFG_R] << RCC_PLLNCFGR2_DIVR_SHIFT) & 1349 RCC_PLLNCFGR2_DIVR_MASK; 1350 if (mmio_read_32(rcc_base + pll->pllxcfgr2) != value) { 1351 return false; 1352 } 1353 1354 return true; 1355 } 1356 1357 static void stm32mp1_pll_start(enum stm32mp1_pll_id pll_id) 1358 { 1359 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id); 1360 uintptr_t pllxcr = stm32mp_rcc_base() + pll->pllxcr; 1361 1362 /* Preserve RCC_PLLNCR_SSCG_CTRL value */ 1363 mmio_clrsetbits_32(pllxcr, 1364 RCC_PLLNCR_DIVPEN | RCC_PLLNCR_DIVQEN | 1365 RCC_PLLNCR_DIVREN, 1366 RCC_PLLNCR_PLLON); 1367 } 1368 1369 static int stm32mp1_pll_output(enum stm32mp1_pll_id pll_id, uint32_t output) 1370 { 1371 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id); 1372 uintptr_t pllxcr = stm32mp_rcc_base() + pll->pllxcr; 1373 uint64_t timeout = timeout_init_us(PLLRDY_TIMEOUT); 1374 1375 /* Wait PLL lock */ 1376 while ((mmio_read_32(pllxcr) & RCC_PLLNCR_PLLRDY) == 0U) { 1377 if (timeout_elapsed(timeout)) { 1378 ERROR("PLL%d start failed @ 0x%lx: 0x%x\n", 1379 pll_id, pllxcr, mmio_read_32(pllxcr)); 1380 return -ETIMEDOUT; 1381 } 1382 } 1383 1384 /* Start the requested output */ 1385 mmio_setbits_32(pllxcr, output << RCC_PLLNCR_DIVEN_SHIFT); 1386 1387 return 0; 1388 } 1389 1390 static int stm32mp1_pll_stop(enum stm32mp1_pll_id pll_id) 1391 { 1392 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id); 1393 uintptr_t pllxcr = stm32mp_rcc_base() + pll->pllxcr; 1394 uint64_t timeout; 1395 1396 /* Stop all output */ 1397 mmio_clrbits_32(pllxcr, RCC_PLLNCR_DIVPEN | RCC_PLLNCR_DIVQEN | 1398 RCC_PLLNCR_DIVREN); 1399 1400 /* Stop PLL */ 1401 mmio_clrbits_32(pllxcr, RCC_PLLNCR_PLLON); 1402 1403 timeout = timeout_init_us(PLLRDY_TIMEOUT); 1404 /* Wait PLL stopped */ 1405 while ((mmio_read_32(pllxcr) & RCC_PLLNCR_PLLRDY) != 0U) { 1406 if (timeout_elapsed(timeout)) { 1407 ERROR("PLL%d stop failed @ 0x%lx: 0x%x\n", 1408 pll_id, pllxcr, mmio_read_32(pllxcr)); 1409 return -ETIMEDOUT; 1410 } 1411 } 1412 1413 return 0; 1414 } 1415 1416 static void stm32mp1_pll_config_output(enum stm32mp1_pll_id pll_id, 1417 uint32_t *pllcfg) 1418 { 1419 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id); 1420 uintptr_t rcc_base = stm32mp_rcc_base(); 1421 uint32_t value; 1422 1423 value = (pllcfg[PLLCFG_P] << RCC_PLLNCFGR2_DIVP_SHIFT) & 1424 RCC_PLLNCFGR2_DIVP_MASK; 1425 value |= (pllcfg[PLLCFG_Q] << RCC_PLLNCFGR2_DIVQ_SHIFT) & 1426 RCC_PLLNCFGR2_DIVQ_MASK; 1427 value |= (pllcfg[PLLCFG_R] << RCC_PLLNCFGR2_DIVR_SHIFT) & 1428 RCC_PLLNCFGR2_DIVR_MASK; 1429 mmio_write_32(rcc_base + pll->pllxcfgr2, value); 1430 } 1431 1432 static int stm32mp1_pll_config(enum stm32mp1_pll_id pll_id, 1433 uint32_t *pllcfg, uint32_t fracv) 1434 { 1435 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id); 1436 uintptr_t rcc_base = stm32mp_rcc_base(); 1437 enum stm32mp1_plltype type = pll->plltype; 1438 unsigned long refclk; 1439 uint32_t ifrge = 0; 1440 uint32_t src, value; 1441 1442 src = mmio_read_32(rcc_base + pll->rckxselr) & 1443 RCC_SELR_REFCLK_SRC_MASK; 1444 1445 refclk = stm32mp1_clk_get_fixed(pll->refclk[src]) / 1446 (pllcfg[PLLCFG_M] + 1U); 1447 1448 if ((refclk < (stm32mp1_pll[type].refclk_min * 1000000U)) || 1449 (refclk > (stm32mp1_pll[type].refclk_max * 1000000U))) { 1450 return -EINVAL; 1451 } 1452 1453 if ((type == PLL_800) && (refclk >= 8000000U)) { 1454 ifrge = 1U; 1455 } 1456 1457 value = (pllcfg[PLLCFG_N] << RCC_PLLNCFGR1_DIVN_SHIFT) & 1458 RCC_PLLNCFGR1_DIVN_MASK; 1459 value |= (pllcfg[PLLCFG_M] << RCC_PLLNCFGR1_DIVM_SHIFT) & 1460 RCC_PLLNCFGR1_DIVM_MASK; 1461 value |= (ifrge << RCC_PLLNCFGR1_IFRGE_SHIFT) & 1462 RCC_PLLNCFGR1_IFRGE_MASK; 1463 mmio_write_32(rcc_base + pll->pllxcfgr1, value); 1464 1465 /* Fractional configuration */ 1466 value = 0; 1467 mmio_write_32(rcc_base + pll->pllxfracr, value); 1468 1469 value = fracv << RCC_PLLNFRACR_FRACV_SHIFT; 1470 mmio_write_32(rcc_base + pll->pllxfracr, value); 1471 1472 value |= RCC_PLLNFRACR_FRACLE; 1473 mmio_write_32(rcc_base + pll->pllxfracr, value); 1474 1475 stm32mp1_pll_config_output(pll_id, pllcfg); 1476 1477 return 0; 1478 } 1479 1480 static void stm32mp1_pll_csg(enum stm32mp1_pll_id pll_id, uint32_t *csg) 1481 { 1482 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id); 1483 uint32_t pllxcsg = 0; 1484 1485 pllxcsg |= (csg[PLLCSG_MOD_PER] << RCC_PLLNCSGR_MOD_PER_SHIFT) & 1486 RCC_PLLNCSGR_MOD_PER_MASK; 1487 1488 pllxcsg |= (csg[PLLCSG_INC_STEP] << RCC_PLLNCSGR_INC_STEP_SHIFT) & 1489 RCC_PLLNCSGR_INC_STEP_MASK; 1490 1491 pllxcsg |= (csg[PLLCSG_SSCG_MODE] << RCC_PLLNCSGR_SSCG_MODE_SHIFT) & 1492 RCC_PLLNCSGR_SSCG_MODE_MASK; 1493 1494 mmio_write_32(stm32mp_rcc_base() + pll->pllxcsgr, pllxcsg); 1495 1496 mmio_setbits_32(stm32mp_rcc_base() + pll->pllxcr, 1497 RCC_PLLNCR_SSCG_CTRL); 1498 } 1499 1500 static int stm32mp1_set_clksrc(unsigned int clksrc) 1501 { 1502 uintptr_t clksrc_address = stm32mp_rcc_base() + (clksrc >> 4); 1503 uint64_t timeout; 1504 1505 mmio_clrsetbits_32(clksrc_address, RCC_SELR_SRC_MASK, 1506 clksrc & RCC_SELR_SRC_MASK); 1507 1508 timeout = timeout_init_us(CLKSRC_TIMEOUT); 1509 while ((mmio_read_32(clksrc_address) & RCC_SELR_SRCRDY) == 0U) { 1510 if (timeout_elapsed(timeout)) { 1511 ERROR("CLKSRC %x start failed @ 0x%lx: 0x%x\n", clksrc, 1512 clksrc_address, mmio_read_32(clksrc_address)); 1513 return -ETIMEDOUT; 1514 } 1515 } 1516 1517 return 0; 1518 } 1519 1520 static int stm32mp1_set_clkdiv(unsigned int clkdiv, uintptr_t address) 1521 { 1522 uint64_t timeout; 1523 1524 mmio_clrsetbits_32(address, RCC_DIVR_DIV_MASK, 1525 clkdiv & RCC_DIVR_DIV_MASK); 1526 1527 timeout = timeout_init_us(CLKDIV_TIMEOUT); 1528 while ((mmio_read_32(address) & RCC_DIVR_DIVRDY) == 0U) { 1529 if (timeout_elapsed(timeout)) { 1530 ERROR("CLKDIV %x start failed @ 0x%lx: 0x%x\n", 1531 clkdiv, address, mmio_read_32(address)); 1532 return -ETIMEDOUT; 1533 } 1534 } 1535 1536 return 0; 1537 } 1538 1539 static void stm32mp1_mco_csg(uint32_t clksrc, uint32_t clkdiv) 1540 { 1541 uintptr_t clksrc_address = stm32mp_rcc_base() + (clksrc >> 4); 1542 1543 /* 1544 * Binding clksrc : 1545 * bit15-4 offset 1546 * bit3: disable 1547 * bit2-0: MCOSEL[2:0] 1548 */ 1549 if ((clksrc & 0x8U) != 0U) { 1550 mmio_clrbits_32(clksrc_address, RCC_MCOCFG_MCOON); 1551 } else { 1552 mmio_clrsetbits_32(clksrc_address, 1553 RCC_MCOCFG_MCOSRC_MASK, 1554 clksrc & RCC_MCOCFG_MCOSRC_MASK); 1555 mmio_clrsetbits_32(clksrc_address, 1556 RCC_MCOCFG_MCODIV_MASK, 1557 clkdiv << RCC_MCOCFG_MCODIV_SHIFT); 1558 mmio_setbits_32(clksrc_address, RCC_MCOCFG_MCOON); 1559 } 1560 } 1561 1562 static void stm32mp1_set_rtcsrc(unsigned int clksrc, bool lse_css) 1563 { 1564 uintptr_t address = stm32mp_rcc_base() + RCC_BDCR; 1565 1566 if (((mmio_read_32(address) & RCC_BDCR_RTCCKEN) == 0U) || 1567 (clksrc != (uint32_t)CLK_RTC_DISABLED)) { 1568 mmio_clrsetbits_32(address, 1569 RCC_BDCR_RTCSRC_MASK, 1570 clksrc << RCC_BDCR_RTCSRC_SHIFT); 1571 1572 mmio_setbits_32(address, RCC_BDCR_RTCCKEN); 1573 } 1574 1575 if (lse_css) { 1576 mmio_setbits_32(address, RCC_BDCR_LSECSSON); 1577 } 1578 } 1579 1580 static void stm32mp1_stgen_config(void) 1581 { 1582 uintptr_t stgen; 1583 uint32_t cntfid0; 1584 unsigned long rate; 1585 unsigned long long counter; 1586 1587 stgen = fdt_get_stgen_base(); 1588 cntfid0 = mmio_read_32(stgen + CNTFID_OFF); 1589 rate = get_clock_rate(stm32mp1_clk_get_parent(STGEN_K)); 1590 1591 if (cntfid0 == rate) { 1592 return; 1593 } 1594 1595 mmio_clrbits_32(stgen + CNTCR_OFF, CNTCR_EN); 1596 counter = (unsigned long long)mmio_read_32(stgen + CNTCVL_OFF); 1597 counter |= ((unsigned long long)mmio_read_32(stgen + CNTCVU_OFF)) << 32; 1598 counter = (counter * rate / cntfid0); 1599 1600 mmio_write_32(stgen + CNTCVL_OFF, (uint32_t)counter); 1601 mmio_write_32(stgen + CNTCVU_OFF, (uint32_t)(counter >> 32)); 1602 mmio_write_32(stgen + CNTFID_OFF, rate); 1603 mmio_setbits_32(stgen + CNTCR_OFF, CNTCR_EN); 1604 1605 write_cntfrq((u_register_t)rate); 1606 1607 /* Need to update timer with new frequency */ 1608 generic_delay_timer_init(); 1609 } 1610 1611 void stm32mp1_stgen_increment(unsigned long long offset_in_ms) 1612 { 1613 uintptr_t stgen; 1614 unsigned long long cnt; 1615 1616 stgen = fdt_get_stgen_base(); 1617 1618 cnt = ((unsigned long long)mmio_read_32(stgen + CNTCVU_OFF) << 32) | 1619 mmio_read_32(stgen + CNTCVL_OFF); 1620 1621 cnt += (offset_in_ms * mmio_read_32(stgen + CNTFID_OFF)) / 1000U; 1622 1623 mmio_clrbits_32(stgen + CNTCR_OFF, CNTCR_EN); 1624 mmio_write_32(stgen + CNTCVL_OFF, (uint32_t)cnt); 1625 mmio_write_32(stgen + CNTCVU_OFF, (uint32_t)(cnt >> 32)); 1626 mmio_setbits_32(stgen + CNTCR_OFF, CNTCR_EN); 1627 } 1628 1629 static void stm32mp1_pkcs_config(uint32_t pkcs) 1630 { 1631 uintptr_t address = stm32mp_rcc_base() + ((pkcs >> 4) & 0xFFFU); 1632 uint32_t value = pkcs & 0xFU; 1633 uint32_t mask = 0xFU; 1634 1635 if ((pkcs & BIT(31)) != 0U) { 1636 mask <<= 4; 1637 value <<= 4; 1638 } 1639 1640 mmio_clrsetbits_32(address, mask, value); 1641 } 1642 1643 int stm32mp1_clk_init(void) 1644 { 1645 uintptr_t rcc_base = stm32mp_rcc_base(); 1646 unsigned int clksrc[CLKSRC_NB]; 1647 unsigned int clkdiv[CLKDIV_NB]; 1648 unsigned int pllcfg[_PLL_NB][PLLCFG_NB]; 1649 int plloff[_PLL_NB]; 1650 int ret, len; 1651 enum stm32mp1_pll_id i; 1652 bool lse_css = false; 1653 bool pll3_preserve = false; 1654 bool pll4_preserve = false; 1655 bool pll4_bootrom = false; 1656 const fdt32_t *pkcs_cell; 1657 void *fdt; 1658 1659 if (fdt_get_address(&fdt) == 0) { 1660 return false; 1661 } 1662 1663 /* Check status field to disable security */ 1664 if (!fdt_get_rcc_secure_status()) { 1665 mmio_write_32(rcc_base + RCC_TZCR, 0); 1666 } 1667 1668 ret = fdt_rcc_read_uint32_array("st,clksrc", (uint32_t)CLKSRC_NB, 1669 clksrc); 1670 if (ret < 0) { 1671 return -FDT_ERR_NOTFOUND; 1672 } 1673 1674 ret = fdt_rcc_read_uint32_array("st,clkdiv", (uint32_t)CLKDIV_NB, 1675 clkdiv); 1676 if (ret < 0) { 1677 return -FDT_ERR_NOTFOUND; 1678 } 1679 1680 for (i = (enum stm32mp1_pll_id)0; i < _PLL_NB; i++) { 1681 char name[12]; 1682 1683 snprintf(name, sizeof(name), "st,pll@%d", i); 1684 plloff[i] = fdt_rcc_subnode_offset(name); 1685 1686 if (!fdt_check_node(plloff[i])) { 1687 continue; 1688 } 1689 1690 ret = fdt_read_uint32_array(fdt, plloff[i], "cfg", 1691 (int)PLLCFG_NB, pllcfg[i]); 1692 if (ret < 0) { 1693 return -FDT_ERR_NOTFOUND; 1694 } 1695 } 1696 1697 stm32mp1_mco_csg(clksrc[CLKSRC_MCO1], clkdiv[CLKDIV_MCO1]); 1698 stm32mp1_mco_csg(clksrc[CLKSRC_MCO2], clkdiv[CLKDIV_MCO2]); 1699 1700 /* 1701 * Switch ON oscillator found in device-tree. 1702 * Note: HSI already ON after BootROM stage. 1703 */ 1704 if (stm32mp1_osc[_LSI] != 0U) { 1705 stm32mp1_lsi_set(true); 1706 } 1707 if (stm32mp1_osc[_LSE] != 0U) { 1708 bool bypass, digbyp; 1709 uint32_t lsedrv; 1710 1711 bypass = fdt_osc_read_bool(_LSE, "st,bypass"); 1712 digbyp = fdt_osc_read_bool(_LSE, "st,digbypass"); 1713 lse_css = fdt_osc_read_bool(_LSE, "st,css"); 1714 lsedrv = fdt_osc_read_uint32_default(_LSE, "st,drive", 1715 LSEDRV_MEDIUM_HIGH); 1716 stm32mp1_lse_enable(bypass, digbyp, lsedrv); 1717 } 1718 if (stm32mp1_osc[_HSE] != 0U) { 1719 bool bypass, digbyp, css; 1720 1721 bypass = fdt_osc_read_bool(_HSE, "st,bypass"); 1722 digbyp = fdt_osc_read_bool(_HSE, "st,digbypass"); 1723 css = fdt_osc_read_bool(_HSE, "st,css"); 1724 stm32mp1_hse_enable(bypass, digbyp, css); 1725 } 1726 /* 1727 * CSI is mandatory for automatic I/O compensation (SYSCFG_CMPCR) 1728 * => switch on CSI even if node is not present in device tree 1729 */ 1730 stm32mp1_csi_set(true); 1731 1732 /* Come back to HSI */ 1733 ret = stm32mp1_set_clksrc(CLK_MPU_HSI); 1734 if (ret != 0) { 1735 return ret; 1736 } 1737 ret = stm32mp1_set_clksrc(CLK_AXI_HSI); 1738 if (ret != 0) { 1739 return ret; 1740 } 1741 ret = stm32mp1_set_clksrc(CLK_MCU_HSI); 1742 if (ret != 0) { 1743 return ret; 1744 } 1745 1746 if ((mmio_read_32(rcc_base + RCC_MP_RSTSCLRR) & 1747 RCC_MP_RSTSCLRR_MPUP0RSTF) != 0) { 1748 pll3_preserve = stm32mp1_check_pll_conf(_PLL3, 1749 clksrc[CLKSRC_PLL3], 1750 pllcfg[_PLL3], 1751 plloff[_PLL3]); 1752 pll4_preserve = stm32mp1_check_pll_conf(_PLL4, 1753 clksrc[CLKSRC_PLL4], 1754 pllcfg[_PLL4], 1755 plloff[_PLL4]); 1756 } 1757 1758 for (i = (enum stm32mp1_pll_id)0; i < _PLL_NB; i++) { 1759 if (((i == _PLL3) && pll3_preserve) || 1760 ((i == _PLL4) && pll4_preserve)) { 1761 continue; 1762 } 1763 1764 ret = stm32mp1_pll_stop(i); 1765 if (ret != 0) { 1766 return ret; 1767 } 1768 } 1769 1770 /* Configure HSIDIV */ 1771 if (stm32mp1_osc[_HSI] != 0U) { 1772 ret = stm32mp1_hsidiv(stm32mp1_osc[_HSI]); 1773 if (ret != 0) { 1774 return ret; 1775 } 1776 stm32mp1_stgen_config(); 1777 } 1778 1779 /* Select DIV */ 1780 /* No ready bit when MPUSRC != CLK_MPU_PLL1P_DIV, MPUDIV is disabled */ 1781 mmio_write_32(rcc_base + RCC_MPCKDIVR, 1782 clkdiv[CLKDIV_MPU] & RCC_DIVR_DIV_MASK); 1783 ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_AXI], rcc_base + RCC_AXIDIVR); 1784 if (ret != 0) { 1785 return ret; 1786 } 1787 ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_APB4], rcc_base + RCC_APB4DIVR); 1788 if (ret != 0) { 1789 return ret; 1790 } 1791 ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_APB5], rcc_base + RCC_APB5DIVR); 1792 if (ret != 0) { 1793 return ret; 1794 } 1795 ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_MCU], rcc_base + RCC_MCUDIVR); 1796 if (ret != 0) { 1797 return ret; 1798 } 1799 ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_APB1], rcc_base + RCC_APB1DIVR); 1800 if (ret != 0) { 1801 return ret; 1802 } 1803 ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_APB2], rcc_base + RCC_APB2DIVR); 1804 if (ret != 0) { 1805 return ret; 1806 } 1807 ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_APB3], rcc_base + RCC_APB3DIVR); 1808 if (ret != 0) { 1809 return ret; 1810 } 1811 1812 /* No ready bit for RTC */ 1813 mmio_write_32(rcc_base + RCC_RTCDIVR, 1814 clkdiv[CLKDIV_RTC] & RCC_DIVR_DIV_MASK); 1815 1816 /* Configure PLLs source */ 1817 ret = stm32mp1_set_clksrc(clksrc[CLKSRC_PLL12]); 1818 if (ret != 0) { 1819 return ret; 1820 } 1821 1822 if (!pll3_preserve) { 1823 ret = stm32mp1_set_clksrc(clksrc[CLKSRC_PLL3]); 1824 if (ret != 0) { 1825 return ret; 1826 } 1827 } 1828 1829 if (!pll4_preserve) { 1830 ret = stm32mp1_set_clksrc(clksrc[CLKSRC_PLL4]); 1831 if (ret != 0) { 1832 return ret; 1833 } 1834 } 1835 1836 /* Configure and start PLLs */ 1837 for (i = (enum stm32mp1_pll_id)0; i < _PLL_NB; i++) { 1838 uint32_t fracv; 1839 uint32_t csg[PLLCSG_NB]; 1840 1841 if (((i == _PLL3) && pll3_preserve) || 1842 ((i == _PLL4) && pll4_preserve && !pll4_bootrom)) { 1843 continue; 1844 } 1845 1846 if (!fdt_check_node(plloff[i])) { 1847 continue; 1848 } 1849 1850 if ((i == _PLL4) && pll4_bootrom) { 1851 /* Set output divider if not done by the Bootrom */ 1852 stm32mp1_pll_config_output(i, pllcfg[i]); 1853 continue; 1854 } 1855 1856 fracv = fdt_read_uint32_default(fdt, plloff[i], "frac", 0); 1857 1858 ret = stm32mp1_pll_config(i, pllcfg[i], fracv); 1859 if (ret != 0) { 1860 return ret; 1861 } 1862 ret = fdt_read_uint32_array(fdt, plloff[i], "csg", 1863 (uint32_t)PLLCSG_NB, csg); 1864 if (ret == 0) { 1865 stm32mp1_pll_csg(i, csg); 1866 } else if (ret != -FDT_ERR_NOTFOUND) { 1867 return ret; 1868 } 1869 1870 stm32mp1_pll_start(i); 1871 } 1872 /* Wait and start PLLs ouptut when ready */ 1873 for (i = (enum stm32mp1_pll_id)0; i < _PLL_NB; i++) { 1874 if (!fdt_check_node(plloff[i])) { 1875 continue; 1876 } 1877 1878 ret = stm32mp1_pll_output(i, pllcfg[i][PLLCFG_O]); 1879 if (ret != 0) { 1880 return ret; 1881 } 1882 } 1883 /* Wait LSE ready before to use it */ 1884 if (stm32mp1_osc[_LSE] != 0U) { 1885 stm32mp1_lse_wait(); 1886 } 1887 1888 /* Configure with expected clock source */ 1889 ret = stm32mp1_set_clksrc(clksrc[CLKSRC_MPU]); 1890 if (ret != 0) { 1891 return ret; 1892 } 1893 ret = stm32mp1_set_clksrc(clksrc[CLKSRC_AXI]); 1894 if (ret != 0) { 1895 return ret; 1896 } 1897 ret = stm32mp1_set_clksrc(clksrc[CLKSRC_MCU]); 1898 if (ret != 0) { 1899 return ret; 1900 } 1901 stm32mp1_set_rtcsrc(clksrc[CLKSRC_RTC], lse_css); 1902 1903 /* Configure PKCK */ 1904 pkcs_cell = fdt_rcc_read_prop("st,pkcs", &len); 1905 if (pkcs_cell != NULL) { 1906 bool ckper_disabled = false; 1907 uint32_t j; 1908 1909 for (j = 0; j < ((uint32_t)len / sizeof(uint32_t)); j++) { 1910 uint32_t pkcs = fdt32_to_cpu(pkcs_cell[j]); 1911 1912 if (pkcs == (uint32_t)CLK_CKPER_DISABLED) { 1913 ckper_disabled = true; 1914 continue; 1915 } 1916 stm32mp1_pkcs_config(pkcs); 1917 } 1918 1919 /* 1920 * CKPER is source for some peripheral clocks 1921 * (FMC-NAND / QPSI-NOR) and switching source is allowed 1922 * only if previous clock is still ON 1923 * => deactivated CKPER only after switching clock 1924 */ 1925 if (ckper_disabled) { 1926 stm32mp1_pkcs_config(CLK_CKPER_DISABLED); 1927 } 1928 } 1929 1930 /* Switch OFF HSI if not found in device-tree */ 1931 if (stm32mp1_osc[_HSI] == 0U) { 1932 stm32mp1_hsi_set(false); 1933 } 1934 stm32mp1_stgen_config(); 1935 1936 /* Software Self-Refresh mode (SSR) during DDR initilialization */ 1937 mmio_clrsetbits_32(rcc_base + RCC_DDRITFCR, 1938 RCC_DDRITFCR_DDRCKMOD_MASK, 1939 RCC_DDRITFCR_DDRCKMOD_SSR << 1940 RCC_DDRITFCR_DDRCKMOD_SHIFT); 1941 1942 return 0; 1943 } 1944 1945 static void stm32mp1_osc_clk_init(const char *name, 1946 enum stm32mp_osc_id index) 1947 { 1948 uint32_t frequency; 1949 1950 if (fdt_osc_read_freq(name, &frequency) == 0) { 1951 stm32mp1_osc[index] = frequency; 1952 } 1953 } 1954 1955 static void stm32mp1_osc_init(void) 1956 { 1957 enum stm32mp_osc_id i; 1958 1959 for (i = (enum stm32mp_osc_id)0 ; i < NB_OSC; i++) { 1960 stm32mp1_osc_clk_init(stm32mp_osc_node_label[i], i); 1961 } 1962 } 1963 1964 static void sync_earlyboot_clocks_state(void) 1965 { 1966 if (!stm32mp_is_single_core()) { 1967 stm32mp1_clk_enable_secure(RTCAPB); 1968 } 1969 } 1970 1971 int stm32mp1_clk_probe(void) 1972 { 1973 stm32mp1_osc_init(); 1974 1975 sync_earlyboot_clocks_state(); 1976 1977 return 0; 1978 } 1979