xref: /rk3399_ARM-atf/plat/st/stm32mp1/stm32mp1_private.c (revision dff9fe92a4ff7b009cd9221375faeee424027921) 
1 /*
2  * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  */
6 
7 #include <assert.h>
8 
9 #include <libfdt.h>
10 
11 #include <platform_def.h>
12 
13 #include <drivers/st/stm32_iwdg.h>
14 #include <lib/xlat_tables/xlat_tables_v2.h>
15 
16 /* Internal layout of the 32bit OTP word board_id */
17 #define BOARD_ID_BOARD_NB_MASK		GENMASK(31, 16)
18 #define BOARD_ID_BOARD_NB_SHIFT		16
19 #define BOARD_ID_VARIANT_MASK		GENMASK(15, 12)
20 #define BOARD_ID_VARIANT_SHIFT		12
21 #define BOARD_ID_REVISION_MASK		GENMASK(11, 8)
22 #define BOARD_ID_REVISION_SHIFT		8
23 #define BOARD_ID_BOM_MASK		GENMASK(3, 0)
24 
25 #define BOARD_ID2NB(_id)		(((_id) & BOARD_ID_BOARD_NB_MASK) >> \
26 					 BOARD_ID_BOARD_NB_SHIFT)
27 #define BOARD_ID2VAR(_id)		(((_id) & BOARD_ID_VARIANT_MASK) >> \
28 					 BOARD_ID_VARIANT_SHIFT)
29 #define BOARD_ID2REV(_id)		(((_id) & BOARD_ID_REVISION_MASK) >> \
30 					 BOARD_ID_REVISION_SHIFT)
31 #define BOARD_ID2BOM(_id)		((_id) & BOARD_ID_BOM_MASK)
32 
33 #define MAP_SRAM	MAP_REGION_FLAT(STM32MP_SYSRAM_BASE, \
34 					STM32MP_SYSRAM_SIZE, \
35 					MT_MEMORY | \
36 					MT_RW | \
37 					MT_SECURE | \
38 					MT_EXECUTE_NEVER)
39 
40 #define MAP_DEVICE1	MAP_REGION_FLAT(STM32MP1_DEVICE1_BASE, \
41 					STM32MP1_DEVICE1_SIZE, \
42 					MT_DEVICE | \
43 					MT_RW | \
44 					MT_SECURE | \
45 					MT_EXECUTE_NEVER)
46 
47 #define MAP_DEVICE2	MAP_REGION_FLAT(STM32MP1_DEVICE2_BASE, \
48 					STM32MP1_DEVICE2_SIZE, \
49 					MT_DEVICE | \
50 					MT_RW | \
51 					MT_SECURE | \
52 					MT_EXECUTE_NEVER)
53 
54 #if defined(IMAGE_BL2)
55 static const mmap_region_t stm32mp1_mmap[] = {
56 	MAP_SRAM,
57 	MAP_DEVICE1,
58 	MAP_DEVICE2,
59 	{0}
60 };
61 #endif
62 #if defined(IMAGE_BL32)
63 static const mmap_region_t stm32mp1_mmap[] = {
64 	MAP_SRAM,
65 	MAP_DEVICE1,
66 	MAP_DEVICE2,
67 	{0}
68 };
69 #endif
70 
71 void configure_mmu(void)
72 {
73 	mmap_add(stm32mp1_mmap);
74 	init_xlat_tables();
75 
76 	enable_mmu_svc_mon(0);
77 }
78 
79 uintptr_t stm32_get_gpio_bank_base(unsigned int bank)
80 {
81 	if (bank == GPIO_BANK_Z) {
82 		return GPIOZ_BASE;
83 	}
84 
85 	assert(GPIO_BANK_A == 0 && bank <= GPIO_BANK_K);
86 
87 	return GPIOA_BASE + (bank * GPIO_BANK_OFFSET);
88 }
89 
90 uint32_t stm32_get_gpio_bank_offset(unsigned int bank)
91 {
92 	if (bank == GPIO_BANK_Z) {
93 		return 0;
94 	}
95 
96 	assert(GPIO_BANK_A == 0 && bank <= GPIO_BANK_K);
97 
98 	return bank * GPIO_BANK_OFFSET;
99 }
100 
101 unsigned long stm32_get_gpio_bank_clock(unsigned int bank)
102 {
103 	if (bank == GPIO_BANK_Z) {
104 		return GPIOZ;
105 	}
106 
107 	assert(GPIO_BANK_A == 0 && bank <= GPIO_BANK_K);
108 
109 	return GPIOA + (bank - GPIO_BANK_A);
110 }
111 
112 int stm32_get_gpio_bank_pinctrl_node(void *fdt, unsigned int bank)
113 {
114 	switch (bank) {
115 	case GPIO_BANK_A:
116 	case GPIO_BANK_B:
117 	case GPIO_BANK_C:
118 	case GPIO_BANK_D:
119 	case GPIO_BANK_E:
120 	case GPIO_BANK_F:
121 	case GPIO_BANK_G:
122 	case GPIO_BANK_H:
123 	case GPIO_BANK_I:
124 	case GPIO_BANK_J:
125 	case GPIO_BANK_K:
126 		return fdt_path_offset(fdt, "/soc/pin-controller");
127 	case GPIO_BANK_Z:
128 		return fdt_path_offset(fdt, "/soc/pin-controller-z");
129 	default:
130 		panic();
131 	}
132 }
133 
134 static int get_part_number(uint32_t *part_nb)
135 {
136 	uint32_t part_number;
137 	uint32_t dev_id;
138 
139 	if (stm32mp1_dbgmcu_get_chip_dev_id(&dev_id) < 0) {
140 		return -1;
141 	}
142 
143 	if (bsec_shadow_read_otp(&part_number, PART_NUMBER_OTP) != BSEC_OK) {
144 		ERROR("BSEC: PART_NUMBER_OTP Error\n");
145 		return -1;
146 	}
147 
148 	part_number = (part_number & PART_NUMBER_OTP_PART_MASK) >>
149 		PART_NUMBER_OTP_PART_SHIFT;
150 
151 	*part_nb = part_number | (dev_id << 16);
152 
153 	return 0;
154 }
155 
156 static int get_cpu_package(uint32_t *cpu_package)
157 {
158 	uint32_t package;
159 
160 	if (bsec_shadow_read_otp(&package, PACKAGE_OTP) != BSEC_OK) {
161 		ERROR("BSEC: PACKAGE_OTP Error\n");
162 		return -1;
163 	}
164 
165 	*cpu_package = (package & PACKAGE_OTP_PKG_MASK) >>
166 		PACKAGE_OTP_PKG_SHIFT;
167 
168 	return 0;
169 }
170 
171 void stm32mp_print_cpuinfo(void)
172 {
173 	const char *cpu_s, *cpu_r, *pkg;
174 	uint32_t part_number;
175 	uint32_t cpu_package;
176 	uint32_t chip_dev_id;
177 	int ret;
178 
179 	/* MPUs Part Numbers */
180 	ret = get_part_number(&part_number);
181 	if (ret < 0) {
182 		WARN("Cannot get part number\n");
183 		return;
184 	}
185 
186 	switch (part_number) {
187 	case STM32MP157C_PART_NB:
188 		cpu_s = "157C";
189 		break;
190 	case STM32MP157A_PART_NB:
191 		cpu_s = "157A";
192 		break;
193 	case STM32MP153C_PART_NB:
194 		cpu_s = "153C";
195 		break;
196 	case STM32MP153A_PART_NB:
197 		cpu_s = "153A";
198 		break;
199 	case STM32MP151C_PART_NB:
200 		cpu_s = "151C";
201 		break;
202 	case STM32MP151A_PART_NB:
203 		cpu_s = "151A";
204 		break;
205 	default:
206 		cpu_s = "????";
207 		break;
208 	}
209 
210 	/* Package */
211 	ret = get_cpu_package(&cpu_package);
212 	if (ret < 0) {
213 		WARN("Cannot get CPU package\n");
214 		return;
215 	}
216 
217 	switch (cpu_package) {
218 	case PKG_AA_LFBGA448:
219 		pkg = "AA";
220 		break;
221 	case PKG_AB_LFBGA354:
222 		pkg = "AB";
223 		break;
224 	case PKG_AC_TFBGA361:
225 		pkg = "AC";
226 		break;
227 	case PKG_AD_TFBGA257:
228 		pkg = "AD";
229 		break;
230 	default:
231 		pkg = "??";
232 		break;
233 	}
234 
235 	/* REVISION */
236 	ret = stm32mp1_dbgmcu_get_chip_version(&chip_dev_id);
237 	if (ret < 0) {
238 		WARN("Cannot get CPU version\n");
239 		return;
240 	}
241 
242 	switch (chip_dev_id) {
243 	case STM32MP1_REV_B:
244 		cpu_r = "B";
245 		break;
246 	default:
247 		cpu_r = "?";
248 		break;
249 	}
250 
251 	NOTICE("CPU: STM32MP%s%s Rev.%s\n", cpu_s, pkg, cpu_r);
252 }
253 
254 void stm32mp_print_boardinfo(void)
255 {
256 	uint32_t board_id;
257 	uint32_t board_otp;
258 	int bsec_node, bsec_board_id_node;
259 	void *fdt;
260 	const fdt32_t *cuint;
261 
262 	if (fdt_get_address(&fdt) == 0) {
263 		panic();
264 	}
265 
266 	bsec_node = fdt_node_offset_by_compatible(fdt, -1, DT_BSEC_COMPAT);
267 	if (bsec_node < 0) {
268 		return;
269 	}
270 
271 	bsec_board_id_node = fdt_subnode_offset(fdt, bsec_node, "board_id");
272 	if (bsec_board_id_node <= 0) {
273 		return;
274 	}
275 
276 	cuint = fdt_getprop(fdt, bsec_board_id_node, "reg", NULL);
277 	if (cuint == NULL) {
278 		panic();
279 	}
280 
281 	board_otp = fdt32_to_cpu(*cuint) / sizeof(uint32_t);
282 
283 	if (bsec_shadow_read_otp(&board_id, board_otp) != BSEC_OK) {
284 		ERROR("BSEC: PART_NUMBER_OTP Error\n");
285 		return;
286 	}
287 
288 	if (board_id != 0U) {
289 		char rev[2];
290 
291 		rev[0] = BOARD_ID2REV(board_id) - 1 + 'A';
292 		rev[1] = '\0';
293 		NOTICE("Board: MB%04x Var%d Rev.%s-%02d\n",
294 		       BOARD_ID2NB(board_id),
295 		       BOARD_ID2VAR(board_id),
296 		       rev,
297 		       BOARD_ID2BOM(board_id));
298 	}
299 }
300 
301 /* Return true when SoC provides a single Cortex-A7 core, and false otherwise */
302 bool stm32mp_is_single_core(void)
303 {
304 	uint32_t part_number;
305 	bool ret = false;
306 
307 	if (get_part_number(&part_number) < 0) {
308 		ERROR("Invalid part number, assume single core chip");
309 		return true;
310 	}
311 
312 	switch (part_number) {
313 	case STM32MP151A_PART_NB:
314 	case STM32MP151C_PART_NB:
315 		ret = true;
316 		break;
317 
318 	default:
319 		break;
320 	}
321 
322 	return ret;
323 }
324 
325 /* Return true when device is in closed state */
326 bool stm32mp_is_closed_device(void)
327 {
328 	uint32_t value;
329 
330 	if ((bsec_shadow_register(DATA0_OTP) != BSEC_OK) ||
331 	    (bsec_read_otp(&value, DATA0_OTP) != BSEC_OK)) {
332 		return true;
333 	}
334 
335 	return (value & DATA0_OTP_SECURED) == DATA0_OTP_SECURED;
336 }
337 
338 uint32_t stm32_iwdg_get_instance(uintptr_t base)
339 {
340 	switch (base) {
341 	case IWDG1_BASE:
342 		return IWDG1_INST;
343 	case IWDG2_BASE:
344 		return IWDG2_INST;
345 	default:
346 		panic();
347 	}
348 }
349 
350 uint32_t stm32_iwdg_get_otp_config(uint32_t iwdg_inst)
351 {
352 	uint32_t iwdg_cfg = 0U;
353 	uint32_t otp_value;
354 
355 #if defined(IMAGE_BL2)
356 	if (bsec_shadow_register(HW2_OTP) != BSEC_OK) {
357 		panic();
358 	}
359 #endif
360 
361 	if (bsec_read_otp(&otp_value, HW2_OTP) != BSEC_OK) {
362 		panic();
363 	}
364 
365 	if ((otp_value & BIT(iwdg_inst + HW2_OTP_IWDG_HW_POS)) != 0U) {
366 		iwdg_cfg |= IWDG_HW_ENABLED;
367 	}
368 
369 	if ((otp_value & BIT(iwdg_inst + HW2_OTP_IWDG_FZ_STOP_POS)) != 0U) {
370 		iwdg_cfg |= IWDG_DISABLE_ON_STOP;
371 	}
372 
373 	if ((otp_value & BIT(iwdg_inst + HW2_OTP_IWDG_FZ_STANDBY_POS)) != 0U) {
374 		iwdg_cfg |= IWDG_DISABLE_ON_STANDBY;
375 	}
376 
377 	return iwdg_cfg;
378 }
379 
380 #if defined(IMAGE_BL2)
381 uint32_t stm32_iwdg_shadow_update(uint32_t iwdg_inst, uint32_t flags)
382 {
383 	uint32_t otp;
384 	uint32_t result;
385 
386 	if (bsec_shadow_read_otp(&otp, HW2_OTP) != BSEC_OK) {
387 		panic();
388 	}
389 
390 	if ((flags & IWDG_DISABLE_ON_STOP) != 0U) {
391 		otp |= BIT(iwdg_inst + HW2_OTP_IWDG_FZ_STOP_POS);
392 	}
393 
394 	if ((flags & IWDG_DISABLE_ON_STANDBY) != 0U) {
395 		otp |= BIT(iwdg_inst + HW2_OTP_IWDG_FZ_STANDBY_POS);
396 	}
397 
398 	result = bsec_write_otp(otp, HW2_OTP);
399 	if (result != BSEC_OK) {
400 		return result;
401 	}
402 
403 	/* Sticky lock OTP_IWDG (read and write) */
404 	if (!bsec_write_sr_lock(HW2_OTP, 1U) ||
405 	    !bsec_write_sw_lock(HW2_OTP, 1U)) {
406 		return BSEC_LOCK_FAIL;
407 	}
408 
409 	return BSEC_OK;
410 }
411 #endif
412 
413 /* Get the non-secure DDR size */
414 uint32_t stm32mp_get_ddr_ns_size(void)
415 {
416 	static uint32_t ddr_ns_size;
417 	uint32_t ddr_size;
418 
419 	if (ddr_ns_size != 0U) {
420 		return ddr_ns_size;
421 	}
422 
423 	ddr_size = dt_get_ddr_size();
424 	if ((ddr_size <= (STM32MP_DDR_S_SIZE + STM32MP_DDR_SHMEM_SIZE)) ||
425 	    (ddr_size > STM32MP_DDR_MAX_SIZE)) {
426 		panic();
427 	}
428 
429 	ddr_ns_size = ddr_size - (STM32MP_DDR_S_SIZE + STM32MP_DDR_SHMEM_SIZE);
430 
431 	return ddr_ns_size;
432 }
433