refactor(ff-a): move structure definitions

Move ffa_partition_info_get definitions from EL3 SPMC private header
files to common header files. The structures are common to FF-A and are
useful for the

refactor(ff-a): move structure definitions

Move ffa_partition_info_get definitions from EL3 SPMC private header
files to common header files. The structures are common to FF-A and are
useful for the EL3 SPMD logical partitions.

Signed-off-by: Raghu Krishnamurthy <raghu.ncstate@gmail.com>
Change-Id: I19de3f6cb3351afa873022da1397a475a84e3d8b

show more ...

feat(spmd): el3 direct message API

This patch implements an API that is exposed to SPMD logical partitions
that can be used to send direct messages to a secure partition.
It also adds required code

feat(spmd): el3 direct message API

This patch implements an API that is exposed to SPMD logical partitions
that can be used to send direct messages to a secure partition.
It also adds required code in the SPMD smc handler to complete the
direct response appropriately.

Change-Id: I2d0e38415f13ad4fd28f8984d565036b7d3a9e71
Signed-off-by: Raghu Krishnamurthy <raghu.ncstate@gmail.com>

show more ...

Merge changes I2f4961fe,I0039c724,Iaa3076c1,Ic19973a8 into integration

* changes:
feat(bl32): print entry point before exiting SP_MIN
fix(bl32): avoid clearing argument registers in RESET_TO_SP_

Merge changes I2f4961fe,I0039c724,Iaa3076c1,Ic19973a8 into integration

* changes:
feat(bl32): print entry point before exiting SP_MIN
fix(bl32): avoid clearing argument registers in RESET_TO_SP_MIN case
fix(bl32): always include arm_arch_svc in SP_MIN
fix(services): disable workaround discovery on aarch32 for now

show more ...

fix(services): disable workaround discovery on aarch32 for now

The Arm Architecture Service (arm_arch_svc) is required for SP_MIN on
AArch32 because the PSCI_FEATURES call implementation in TF-A alw

fix(services): disable workaround discovery on aarch32 for now

The Arm Architecture Service (arm_arch_svc) is required for SP_MIN on
AArch32 because the PSCI_FEATURES call implementation in TF-A always
indicates support for SMCCC_VERSION. However, currently it cannot be
built for AArch32 because all the workaround check functions
(check_wa_cve_2017_5715(), check_smccc_arch_wa3_applies(), ...)
are not implemented for AArch32.

While this should be ideally fixed at some point, disable the
SMCCC_ARCH_WORKAROUND implementations for AArch32 for now so at least
the rest of the calls can be built correctly. This still helps overall
because implementing SMCCC_VERSION is mandatory while the workaround
calls are optional.

Change-Id: Ic19973a8e4d50a97f274d4461794c117b337396b
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>

show more ...

fix(cpus): workaround for Neoverse N2 erratum 2779511

Neoverse N2 erratum 2779511 is a Cat B erratum that applies to
all revisions <=r0p2 and is fixed in r0p3. The workaround is to
set bit[47] of CP

fix(cpus): workaround for Neoverse N2 erratum 2779511

Neoverse N2 erratum 2779511 is a Cat B erratum that applies to
all revisions <=r0p2 and is fixed in r0p3. The workaround is to
set bit[47] of CPUACTLR3_EL1

SDEN documentation:
https://developer.arm.com/documentation/SDEN1982442/latest

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: Iaa0e30de8473ecb1df1fcca3a45904aac2e419b3

show more ...

fix(cpus): workaround for Neoverse N2 erratum 2743014

Neoverse N2 erratum 2743014 is a Cat B erratum that applies to
all revisions <=r0p2 and is fixed in r0p3. The workaround is to
set CPUACTLR5_EL1

fix(cpus): workaround for Neoverse N2 erratum 2743014

Neoverse N2 erratum 2743014 is a Cat B erratum that applies to
all revisions <=r0p2 and is fixed in r0p3. The workaround is to
set CPUACTLR5_EL1[56:55] to 2'b01.

SDEN documentation:
https://developer.arm.com/documentation/SDEN1982442/latest

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: Ie7e1be5dea9d1f74738f9fed0fb58bfd41763192

show more ...

feat(spmd): add spmd logical partitions

Add header file to help with creation of SPMD logical partitions. Also
update linker files to create sections to record SPMD logical partitions
declared. This

feat(spmd): add spmd logical partitions

Add header file to help with creation of SPMD logical partitions. Also
update linker files to create sections to record SPMD logical partitions
declared. This follows the same pattern as the EL3 SPMC's logical
partitions. This patch also adds initialization of SPMD logical
partitions when the SPMD comes up.
ENABLE_SPMD_LP is a build flag that is used to enable support for
SPMD logical partitions.
Note that the approach chosen is to keep SPMD and SPMC logical
partition support separate, as opposed to extend the existing SPMC
logical partition support since the code would need to have a number of
ifdefs and the interactions with various build options such as
SPMC_AT_EL3 needs to be accounted for, which would make code more
complicated.

Signed-off-by: Raghu Krishnamurthy <raghu.ncstate@gmail.com>
Change-Id: I9642ddbf6ea26dd3f4a283baec598d61c07e3661

show more ...

Merge "fix(el3-spmc): fix incorrect CASSERT" into integration

Merge "fix(cpus): workaround for Neoverse V2 erratum 2801372" into integration

fix(el3-spmc): fix incorrect CASSERT

Check that the size of desc->emad_count is 4, not that sizeof(int) is
nonzero. Also improve a comment.

Change-Id: I8bf69b637158ddffe2d08aed3d9879a4d7fd3514
Sig

fix(el3-spmc): fix incorrect CASSERT

Check that the size of desc->emad_count is 4, not that sizeof(int) is
nonzero. Also improve a comment.

Change-Id: I8bf69b637158ddffe2d08aed3d9879a4d7fd3514
Signed-off-by: Demi Marie Obenour <demiobenour@gmail.com>

show more ...

refactor(cm): set MDCR_EL3/CPTR_EL3 bits in respective feat_init_el3() only

These bits (MDCR_EL3.{NSTB, NSTBE, TTRF, TPM}, CPTR_EL3.TTA) only affect
EL2 (and lower) execution. Each feat_init_el3() i

refactor(cm): set MDCR_EL3/CPTR_EL3 bits in respective feat_init_el3() only

These bits (MDCR_EL3.{NSTB, NSTBE, TTRF, TPM}, CPTR_EL3.TTA) only affect
EL2 (and lower) execution. Each feat_init_el3() is called long before
any lower EL has had a chance to execute, so setting the bits at reset
is redundant. Removing them from reset code also improves readability of
the immutable EL3 state.

Preserve the original intention for the TTA bit of "enabled for NS and
disabled everywhere else" (inferred from commit messages d4582d3088 and
2031d6166a and the comment). This is because CPTR_EL3 will be contexted
and so everyone will eventually get whatever NS has anyway.

Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: I3d24b45d3ea80882c8e450b2d9db9d5531facec1

show more ...

fix(cpus): workaround for Neoverse V2 erratum 2801372

Neoverse V2 erratum 2801372 is a Cat B erratum that applies to
all revisions <=r0p1 and is fixed in r0p2. The workaround is to
insert a dsb befo

fix(cpus): workaround for Neoverse V2 erratum 2801372

Neoverse V2 erratum 2801372 is a Cat B erratum that applies to
all revisions <=r0p1 and is fixed in r0p2. The workaround is to
insert a dsb before the isb in the power down sequence.

This errata is explained in SDEN 2332927 available at:
https://developer.arm.com/documentation/SDEN2332927

Change-Id: I8716b9785a67270a72ae329dc49a2f2239dfabff
Signed-off-by: Moritz Fischer <moritzf@google.com>

show more ...

fix(spmd): perform G0 interrupt acknowledge and deactivation

Prior to delegating handling of Group0 secure interrupt to platform
handler, SPMD framework must acknowledge the highest pending interrup

fix(spmd): perform G0 interrupt acknowledge and deactivation

Prior to delegating handling of Group0 secure interrupt to platform
handler, SPMD framework must acknowledge the highest pending interrupt.
Moreover, once the platform has handled the interrupt successfully,
SPMD must deactivate the interrupt.

The rationale behind this decision is SPMD framework is well suited to
perform interrupt management at GIC boundary while the platform handler
is well equipped to deal with the device interface related to the
interrupt.

This patch also fixes a bug in the error code returned upon invocation
of FFA_EL3_INTR_HANDLE from normal world.

Change-Id: If8fef51899e25f966038cc01ec58c84ee25e88eb
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>

show more ...

feat(pmu): introduce pmuv3 lib/extensions folder

The enablement code for the PMU is scattered and difficult to track
down. Factor out the feature into its own lib/extensions folder and
consolidate t

feat(pmu): introduce pmuv3 lib/extensions folder

The enablement code for the PMU is scattered and difficult to track
down. Factor out the feature into its own lib/extensions folder and
consolidate the implementation. Treat it is as an architecturally
mandatory feature as it is currently.

Additionally, do some cleanup on AArch64. Setting overflow bits in
PMCR_EL0 is irrelevant for firmware so don't do it. Then delay the PMU
initialisation until the context management stage which simplifies the
early environment assembly. One side effect is that the PMU might count
before this happens so reset all counters to 0 to prevent any leakage.

Finally, add an enable to manage_extensions_realm() as realm world uses
the pmu. This introduces the HPMN fixup to realm world.

Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: Ie13a8625820ecc5fbfa467dc6ca18025bf6a9cd3

show more ...

Merge changes from topic "ffa_el3_spmc_fixes" into integration

* changes:
fix(tsp): fix destination ID in direct request
fix(el3-spm): fix LSP direct message response
fix(el3-spm): improve dir

Merge changes from topic "ffa_el3_spmc_fixes" into integration

* changes:
fix(tsp): fix destination ID in direct request
fix(el3-spm): fix LSP direct message response
fix(el3-spm): improve direct messaging validation

show more ...

fix(el3-spm): improve direct messaging validation

Perform additional validation of the source and destination
IDs of direct messages.
Additionally track the sender of a direct request to allow
valid

fix(el3-spm): improve direct messaging validation

Perform additional validation of the source and destination
IDs of direct messages.
Additionally track the sender of a direct request to allow
validating the target of the corresponding direct response.

Signed-off-by: Marc Bonnici <marc.bonnici@arm.com>
Change-Id: I8d39d53a02b8333246f1500c79ba04f149459c16

show more ...

refactor(el3-spmc): add comments and cleanup code

No functional change intended.

Change-Id: I08300ec4cb2e11d26c4a108769919d0c474292ff
Signed-off-by: Demi Marie Obenour <demiobenour@gmail.com>

refactor(el3-spmc): avoid extra loop

Using one loop for the duplicate partition ID check is both simpler and
faster.

Change-Id: I0f6fa9ceb1aadf4383fa9be16605c39ad8643a43
Signed-off-by: Demi Marie O

refactor(el3-spmc): avoid extra loop

Using one loop for the duplicate partition ID check is both simpler and
faster.

Change-Id: I0f6fa9ceb1aadf4383fa9be16605c39ad8643a43
Signed-off-by: Demi Marie Obenour <demiobenour@gmail.com>

show more ...

fix(el3-spmc): validate memory address alignment

This ensures that addresses shared using FF-A are 4K aligned, as
required by the specification.

Change-Id: I8f0a659a095fdb9391398757141d613ac9bf9b42

fix(el3-spmc): validate memory address alignment

This ensures that addresses shared using FF-A are 4K aligned, as
required by the specification.

Change-Id: I8f0a659a095fdb9391398757141d613ac9bf9b42
Signed-off-by: Demi Marie Obenour <demiobenour@gmail.com>

show more ...

Merge changes Ic58f4966,Ib7b438b8,I400f0f1f into integration

* changes:
refactor(el3-spmc): add comments
refactor(el3-spmc): move checks after loop
refactor(el3-spmc): validate alignment earli

Merge changes Ic58f4966,Ib7b438b8,I400f0f1f into integration

* changes:
refactor(el3-spmc): add comments
refactor(el3-spmc): move checks after loop
refactor(el3-spmc): validate alignment earlier

show more ...

fix(spmd): relax use of EHF with SPMC at S-EL2

Follow up to [1] and [2], for systems implementing the SPMC at S-EL2,
it is necessary to leave the option for handling Group0 interrupts
(while the nor

fix(spmd): relax use of EHF with SPMC at S-EL2

Follow up to [1] and [2], for systems implementing the SPMC at S-EL2,
it is necessary to leave the option for handling Group0 interrupts
(while the normal world runs) through the EHF by the use of the
EL3_EXCEPTION_HANDLING option.
Specifically for RAS, the handling through EHF is still required because
the platform function provided by the SPMD doesn't provide the facility
to link back to the RAS handling framework.

[1] https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/16047
[2] https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/19897

Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: Idf8741887904a286fb3f5ab2d754afd2fc78d3b0

show more ...

refactor(el3-spmc): add comments

Change-Id: Ic58f4966159cafa83eec8e6b18a96b0a8b2ce781
Signed-off-by: Demi Marie Obenour <demiobenour@gmail.com>

refactor(el3-spmc): move checks after loop

This makes the code cleaner. No functional change intended.

Change-Id: Ib7b438b830e8e3b7ac6e30d688f5172cbaa58121
Signed-off-by: Demi Marie Obenour <demio

refactor(el3-spmc): move checks after loop

This makes the code cleaner. No functional change intended.

Change-Id: Ib7b438b830e8e3b7ac6e30d688f5172cbaa58121
Signed-off-by: Demi Marie Obenour <demiobenour@gmail.com>

show more ...

refactor(el3-spmc): validate alignment earlier

Future changes will cause spmc_shmem_obj_get_comp_mrd to panic instead
of returning NULL, so be sure that comp_mrd_offset has been validated
already.

refactor(el3-spmc): validate alignment earlier

Future changes will cause spmc_shmem_obj_get_comp_mrd to panic instead
of returning NULL, so be sure that comp_mrd_offset has been validated
already. The existing code checks for 8-byte alignment, but comments in
el3_spmc_ffa_memory.h indicate that 16-byte alignment is expected, so
require 16-byte alignment.

Change-Id: I400f0f1f163522cb5ea77d4811c91e8b7e655c18
Signed-off-by: Demi Marie Obenour <demiobenour@gmail.com>

show more ...

refactor(el3-spmc): add emad_advance()

This will be needed later.

Change-Id: I396b5e1410268d98cf6bf00cd553a5d01123847c
Signed-off-by: Demi Marie Obenour <demiobenour@gmail.com>