feat(arm): enable Linux boot from fip as BL33

Disable the reliance of ARM_LINUX_KERNEL_AS_BL33 on PRELOADED_BL33_BASE
so that a Linux Kernel can be loaded and booted from the fip as BL33.

Change-Id

feat(arm): enable Linux boot from fip as BL33

Disable the reliance of ARM_LINUX_KERNEL_AS_BL33 on PRELOADED_BL33_BASE
so that a Linux Kernel can be loaded and booted from the fip as BL33.

Change-Id: I0437eec852cf17e0ed37a7ff77fcc4e66b1cea7a
Signed-off-by: Salman Nabi <salman.nabi@arm.com>

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feat(arm): add initrd props to dtb at build time

Add initrd properties to the device tree blob at build time, giving
users the ability to run a linux kernel and successfully boot it to
the terminal.

feat(arm): add initrd props to dtb at build time

Add initrd properties to the device tree blob at build time, giving
users the ability to run a linux kernel and successfully boot it to
the terminal. Users can boot a linux kernel in a normal flow as well
as in RESET_TO_BL31. This function is an extension of the build time
option "ARM_LINUX_KERNEL_AS_BL33=1".

The build time options INITRD_SIZE or INITRD_PATH will trigger the
insertion of initrd properties in to the DTB. If both options are
provided then the INITRD_SIZE will take precedence.

The available options are:
INITRD_SIZE: Provide the initrd size in dec or hex (hex format must
precede with '0x'.
Example: INITRD_SIZE=0x1000000

INITRD_PATH: Provide an initrd path for the build time to find its
exact size.

INITRD_BASE: A required build time option that sets the initrd base
address in hex format. A default value can be set by the platform.
Example: INITRD_BASE=0x90000000

Change-Id: Ief8de5f00c453509bcc6e978e0a95d768f1f509c
Signed-off-by: Salman Nabi <salman.nabi@arm.com>

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Merge "feat(mt8196): fix MT8196 gpio driver" into integration

fix(el3-runtime): replace CTX_ESR_EL3 with CTX_DOUBLE_FAULT_ESR

ESR_EL3 value is updated when an exception is taken to EL3 and its value
does not change until a new exception is taken to EL3. We nee

fix(el3-runtime): replace CTX_ESR_EL3 with CTX_DOUBLE_FAULT_ESR

ESR_EL3 value is updated when an exception is taken to EL3 and its value
does not change until a new exception is taken to EL3. We need to save
ESR in context memory only when we expect nested exception in EL3.

The scenarios where we would expect nested EL3 execution are related
with FFH_SUPPORT, namely
1.Handling pending async EAs at EL3 boundry
- It uses CTX_SAVED_ESR_EL3 to preserve origins esr_el3
2.Double fault handling
- Introduce an explicit storage (CTX_DOUBLE_FAULT_ESR) for esr_el3
to take care of DobuleFault.

As the ESR context has been removed, read the register directly instead
of its context value in RD platform.

Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: I7720c5f03903f894a77413a235e3cc05c86f9c17

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Merge changes from topic "mb/drtm" into integration

* changes:
feat(drtm): retrieve DLME image authentication features
feat(drtm): log No-Action Event in Event Log for DRTM measurements
feat(f

Merge changes from topic "mb/drtm" into integration

* changes:
feat(drtm): retrieve DLME image authentication features
feat(drtm): log No-Action Event in Event Log for DRTM measurements
feat(fvp): add stub function to retrieve DLME image auth features
feat(drtm): introduce plat API for DLME authentication features
feat(drtm): ensure event types aligns with DRTM specification v1.1
fix(drtm): add missing DLME data regions for min size requirement
feat(fvp): add stub platform function to get ACPI table region size
feat(drtm): add platform API to retrieve ACPI tables region size

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Merge changes from topic "gr/build_fix_spmd" into integration

* changes:
fix(rdv3): handle invalid build combination
fix(build): handle invalid spd build options

Merge changes I5aabe415,Ief6fb4fc into integration

* changes:
feat(stm32mp15-fdts): add SP_MIN versions of DT files
feat(st): use dedicated version of DT for SP_MIN

fix(rdv3): handle invalid build combination

`CTX_INCLUDE_SVE_REGS` should not be enabled when building with
SPD=spmd and SPMD_SPM_AT_SEL2=1 both been used.

Unfortunately a check at top level makefi

fix(rdv3): handle invalid build combination

`CTX_INCLUDE_SVE_REGS` should not be enabled when building with
SPD=spmd and SPMD_SPM_AT_SEL2=1 both been used.

Unfortunately a check at top level makefile ignored this, now its been
fixed at top level makefile. Ensure correct combination are handled,
otherwise it will lead to build failures.

Change-Id: Ib84fc0096c92d9b3d56366c0e1d77b6d83098221
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

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Merge changes Ie8c83c92,I9cca19fd into integration

* changes:
feat(stm32mp2): disable PIE by default on STM32MP2 platform
refactor(stm32mp2): remove useless STM32MP_SEC_SYSRAM_SIZE

Merge "feat(romlib): add PSA Crypto ROMLIB support" into integration

feat(stm32mp2): disable PIE by default on STM32MP2 platform

Allow to disable ENABLE_PIE on STM32MP2. BL31 is loaded at the beginning
of SYSRAM whatever the options set. Set ENABLE_PIE to 0 by defaul

feat(stm32mp2): disable PIE by default on STM32MP2 platform

Allow to disable ENABLE_PIE on STM32MP2. BL31 is loaded at the beginning
of SYSRAM whatever the options set. Set ENABLE_PIE to 0 by default.
This should allow us to reduce BL31 and BL2 size.

Change-Id: Ie8c83c9205e81301eb1fdcf24b94216172586630
Signed-off-by: Maxime Méré <maxime.mere@foss.st.com>

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feat(mt8196): fix MT8196 gpio driver

- Add GPIO_BASE in mtgpio.c
- Modify gpio register address

Signed-off-by: Cathy Xu <ot_cathy.xu@mediatek.com>
Change-Id: I648473fa373d208fa29c7069637974e097b75b

feat(mt8196): fix MT8196 gpio driver

- Add GPIO_BASE in mtgpio.c
- Modify gpio register address

Signed-off-by: Cathy Xu <ot_cathy.xu@mediatek.com>
Change-Id: I648473fa373d208fa29c7069637974e097b75b26

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feat(romlib): add PSA Crypto ROMLIB support

Adding PSA Crypto MBedTLS specific jump table to allow use of ROMLIB, to
be included when PSA_CRYPTO=1 and enabled.

Signed-off-by: Lauren Wehrmeister <la

feat(romlib): add PSA Crypto ROMLIB support

Adding PSA Crypto MBedTLS specific jump table to allow use of ROMLIB, to
be included when PSA_CRYPTO=1 and enabled.

Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
Change-Id: Iff7f0e3c5cba6b89f1732f6c80d3060498e3675d

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refactor(stm32mp2): remove useless STM32MP_SEC_SYSRAM_SIZE

The macro STM32MP_SEC_SYSRAM_SIZE only redefine STM32MP_SYSRAM_SIZE.
Directly use the latter one and remove the STM32MP_SEC_SYSRAM_SIZE.

S

refactor(stm32mp2): remove useless STM32MP_SEC_SYSRAM_SIZE

The macro STM32MP_SEC_SYSRAM_SIZE only redefine STM32MP_SYSRAM_SIZE.
Directly use the latter one and remove the STM32MP_SEC_SYSRAM_SIZE.

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I9cca19fda7294be3f31ec74293ce122037541d12

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feat(st): use dedicated version of DT for SP_MIN

If an STM32MP15 board is compiled for SP_MIN, and a specific DT file
ending with "-sp_min.dts" exist, then this file will be used to generate
BL2 and

feat(st): use dedicated version of DT for SP_MIN

If an STM32MP15 board is compiled for SP_MIN, and a specific DT file
ending with "-sp_min.dts" exist, then this file will be used to generate
BL2 and BL32 DT.

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: Ief6fb4fcf302d07f958a0e2764b149759127f21f

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chore: rename arcadia to Cortex-A320

Cortex-A320 has been announced, rename arcadia to Cortex-A320.

Ref:
https://newsroom.arm.com/blog/introducing-arm-cortex-a320-cpu
https://www.arm.com/products/s

chore: rename arcadia to Cortex-A320

Cortex-A320 has been announced, rename arcadia to Cortex-A320.

Ref:
https://newsroom.arm.com/blog/introducing-arm-cortex-a320-cpu
https://www.arm.com/products/silicon-ip-cpu/cortex-a/cortex-a320

Change-Id: Ifb3743d43dca3d8caaf1e7416715ccca4fdf195f
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

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feat(fvp): add stub function to retrieve DLME image auth features

DLME image authentication features are currently not supported on FVP.
This patch introduces a stub function in fvp_drtm_stub.c as a

feat(fvp): add stub function to retrieve DLME image auth features

DLME image authentication features are currently not supported on FVP.
This patch introduces a stub function in fvp_drtm_stub.c as a
placeholder for retrieving DLME image authentication features.

Change-Id: I6d274834245774c5442d67ee93fcd641f3a9cd1a
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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feat(fvp): add stub platform function to get ACPI table region size

Introduces a stub platform function for FVP to retrieve the ACPI table
region size.

Change-Id: Icbf1ae0cb89c393502de2c2f4f66df6b5

feat(fvp): add stub platform function to get ACPI table region size

Introduces a stub platform function for FVP to retrieve the ACPI table
region size.

Change-Id: Icbf1ae0cb89c393502de2c2f4f66df6b510e6b81
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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Merge "feat(rk3576): support rk3576" into integration

perf(psci): get PMF timestamps with no cache flushes if possible

Whenever we have HW_ASSISTED_COHERENCY, caches are enabled early and we
let the cores do the cache maintenance on our behalf. This is

perf(psci): get PMF timestamps with no cache flushes if possible

Whenever we have HW_ASSISTED_COHERENCY, caches are enabled early and we
let the cores do the cache maintenance on our behalf. This is true for
the PSCI stat timestamp capture and used to be the case. However, a
model bug required us to do the cache maintenance manually. That has
been fixed so we can revert back.

Change-Id: Id315a8fea500fb5e2433d3786b2be5a9084300a7
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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perf(amu): greatly simplify AMU context management

The current code is incredibly resilient to updates to the spec and
has worked quite well so far. However, recent implementations expose a
weakness

perf(amu): greatly simplify AMU context management

The current code is incredibly resilient to updates to the spec and
has worked quite well so far. However, recent implementations expose a
weakness in that this is rather slow. A large part of it is written in
assembly, making it opaque to the compiler for optimisations. The
future proofness requires reading registers that are effectively
`volatile`, making it even harder for the compiler, as well as adding
lots of implicit barriers, making it hard for the microarchitecutre to
optimise as well.

We can make a few assumptions, checked by a few well placed asserts, and
remove a lot of this burden. For a start, at the moment there are 4
group 0 counters with static assignments. Contexting them is a trivial
affair that doesn't need a loop. Similarly, there can only be up to 16
group 1 counters. Contexting them is a bit harder, but we can do with a
single branch with a falling through switch. If/when both of these
change, we have a pair of asserts and the feature detection mechanism to
guard us against pretending that we support something we don't.

We can drop contexting of the offset registers. They are fully
accessible by EL2 and as such are its responsibility to preserve on
powerdown.

Another small thing we can do, is pass the core_pos into the hook.
The caller already knows which core we're running on, we don't need to
call this non-trivial function again.

Finally, knowing this, we don't really need the auxiliary AMUs to be
described by the device tree. Linux doesn't care at the moment, and any
information we need for EL3 can be neatly placed in a simple array.

All of this, combined with lifting the actual saving out of assembly,
reduces the instructions to save the context from 180 to 40, including a
lot fewer branches. The code is also much shorter and easier to read.

Also propagate to aarch32 so that the two don't diverge too much.

Change-Id: Ib62e6e9ba5be7fb9fb8965c8eee148d5598a5361
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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perf(mpmm): greatly simplify MPMM enablement

MPMM is a core-specific microarchitectural feature. It has been present
in every Arm core since the Cortex-A510 and has been implemented in
exactly the s

perf(mpmm): greatly simplify MPMM enablement

MPMM is a core-specific microarchitectural feature. It has been present
in every Arm core since the Cortex-A510 and has been implemented in
exactly the same way. Despite that, it is enabled more like an
architectural feature with a top level enable flag. This utilised the
identical implementation.

This duality has left MPMM in an awkward place, where its enablement
should be generic, like an architectural feature, but since it is not,
it should also be core-specific if it ever changes. One choice to do
this has been through the device tree.

This has worked just fine so far, however, recent implementations expose
a weakness in that this is rather slow - the device tree has to be read,
there's a long call stack of functions with many branches, and system
registers are read. In the hot path of PSCI CPU powerdown, this has a
significant and measurable impact. Besides it being a rather large
amount of code that is difficult to understand.

Since MPMM is a microarchitectural feature, its correct placement is in
the reset function. The essence of the current enablement is to write
CPUPPMCR_EL3.MPMM_EN if CPUPPMCR_EL3.MPMMPINCTL == 0. Replacing the C
enablement with an assembly macro in each CPU's reset function achieves
the same effect with just a single close branch and a grand total of 6
instructions (versus the old 2 branches and 32 instructions).

Having done this, the device tree entry becomes redundant. Should a core
that doesn't support MPMM arise, this can cleanly be handled in the
reset function. As such, the whole ENABLE_MPMM_FCONF and platform hooks
mechanisms become obsolete and are removed.

Change-Id: I1d0475b21a1625bb3519f513ba109284f973ffdf
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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Merge changes from topic "bk/errata_speed" into integration

* changes:
refactor(cpus): declare runtime errata correctly
perf(cpus): make reset errata do fewer branches
perf(cpus): inline the i

Merge changes from topic "bk/errata_speed" into integration

* changes:
refactor(cpus): declare runtime errata correctly
perf(cpus): make reset errata do fewer branches
perf(cpus): inline the init_cpu_data_ptr function
perf(cpus): inline the reset function
perf(cpus): inline the cpu_get_rev_var call
perf(cpus): inline cpu_rev_var checks
refactor(cpus): register DSU errata with the errata framework's wrappers
refactor(cpus): convert checker functions to standard helpers
refactor(cpus): convert the Cortex-A65 to use the errata framework
fix(cpus): declare reset errata correctly

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Merge "feat(intel): add FDT support for Altera products" into integration

feat(intel): add FDT support for Altera products

Support FDT for Agilex5 platform
1. Created wrapper file socfpga_dt.c
2. Added in Agilex5 dts file
3. Implemented fdt_check_header
4. Implemented gic

feat(intel): add FDT support for Altera products

Support FDT for Agilex5 platform
1. Created wrapper file socfpga_dt.c
2. Added in Agilex5 dts file
3. Implemented fdt_check_header
4. Implemented gic configuration
5. Implemented dram configuration

Remove init of FDT as Agilex5 has no plan to roll
out FDT at the moment.

Change-Id: If3990ed9524c6da5b3cb8966b63bc4a95d01fcda
Signed-off-by: Jit Loon Lim <jit.loon.lim@altera.com>

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