Merge pull request #632 from rockchip-linux/support-for-gpio-driver-v2

rockchip/rk3399: Support the gpio driver and configure

rockchip: support system off function for rk3399

if define power off gpio, BL31 will do system power off through
gpio control.

rockchip: support reset SoC through gpio for rk3399

If define a reset gpio, BL31 will use gpio to reset SOC,
otherwise use CRU reset.

rockchip: add reset or power off gpio configuration for rk3399

We add plat parameter structs to support BL2 to pass variable-length,
variable-type parameters to BL31. The parameters are structured a

rockchip: add reset or power off gpio configuration for rk3399

We add plat parameter structs to support BL2 to pass variable-length,
variable-type parameters to BL31. The parameters are structured as a
link list. During bl31 setup time, we travse the list to process each
parameter. throuth this way, we can get the reset or power off gpio
parameter, and do hardware control in BL31. This structure also can
pass other parameter to BL31 in future.

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rockchip: support rk3399 gpio driver

There are 5 groups of GPIO (GPIO0~GPIO4), totally have 122 GPIOs
on rk3399 platform.
The pull direction(pullup or pulldown) for all of GPIOs are
software-program

rockchip: support rk3399 gpio driver

There are 5 groups of GPIO (GPIO0~GPIO4), totally have 122 GPIOs
on rk3399 platform.
The pull direction(pullup or pulldown) for all of GPIOs are
software-programmable.
At the moment, we add the gpio basic driver since reset or power off
the devices from gpio configuration for BL31.

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zynqmp: PSCI: Wait for FW completing wake requests

Powering up cores didn't wait for the PMUFW to complete the request,
which could result in cores failing to power up in Linux.

Reported-by: Kotesw

zynqmp: PSCI: Wait for FW completing wake requests

Powering up cores didn't wait for the PMUFW to complete the request,
which could result in cores failing to power up in Linux.

Reported-by: Koteswararao Nayudu <kotin@xilinx.com>
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>

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Add CCN support to FVP platform port

This patch adds support to select CCN driver for FVP during build.
A new build option `FVP_INTERCONNECT_DRIVER` is added to allow
selection between the CCI and C

Add CCN support to FVP platform port

This patch adds support to select CCN driver for FVP during build.
A new build option `FVP_INTERCONNECT_DRIVER` is added to allow
selection between the CCI and CCN driver. Currently only the CCN-502
variant is supported on FVP.

The common ARM CCN platform helper file now verifies the cluster
count declared by platform is equal to the number of root node
masters exported by the ARM Standard platform.

Change-Id: I71d7b4785f8925ed499c153b2e9b9925fcefd57a

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zynqmp: Ignore the revision field of the IDCODE

The revision field may change between silicon revisions without changing
the mapping to a part. This avoids errors like:
ERROR: Incorrect XILINX IDC

zynqmp: Ignore the revision field of the IDCODE

The revision field may change between silicon revisions without changing
the mapping to a part. This avoids errors like:
ERROR: Incorrect XILINX IDCODE 0x14738093, maskid 0x4600093
NOTICE: ATF running on XCZUUNKN/EP108 v3/RTL5.1 at 0xfffe5000
on parts with a newer revision.

Reported-by: Love Kumar <love.kumar@xilinx.com>
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Acked-by: Alistair Francis <alistair.francis@xilinx.com>
Tested-by: Love Kumar <love.kumar@xilinx.com>

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zynqmp: Add bakery_lock to protect APU_PWRCTRL register access

Access to APU_PWRCTRL register is protected during suspend/wakeup pocedure
in order to save valid state. If more than one CPU is access

zynqmp: Add bakery_lock to protect APU_PWRCTRL register access

Access to APU_PWRCTRL register is protected during suspend/wakeup pocedure
in order to save valid state. If more than one CPU is accessing this register
it can be left in corrupted state during read-modify-write process.

Signed-off-by: Stefan Krsmanovic <stefan.krsmanovic@aggios.com>
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>

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zynqmp: Put pm_secure_lock in coherent memory region

DEFINE_BAKERY_LOCK() macro is used to put lock in coherent memory region.
ARM Trusted Firmware design guide, chapter 11 states that bakery_lock d

zynqmp: Put pm_secure_lock in coherent memory region

DEFINE_BAKERY_LOCK() macro is used to put lock in coherent memory region.
ARM Trusted Firmware design guide, chapter 11 states that bakery_lock data
structures should be allocated in coherent memory region because it is
accessed by multiple CPUs with mismatched shareability, cacheability and
memory attributes.

Signed-off-by: Stefan Krsmanovic <stefan.krsmanovic@aggios.com>
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>

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zynqmp: pm: Implement pm_register_notifier PM API function

Signed-off-by: Anes Hadziahmetagic <anes.hadziahmetagic@aggios.com>
Signed-off-by: Filip Drazic <filip.drazic@aggios.com>
Signed-off-by: So

zynqmp: pm: Implement pm_register_notifier PM API function

Signed-off-by: Anes Hadziahmetagic <anes.hadziahmetagic@aggios.com>
Signed-off-by: Filip Drazic <filip.drazic@aggios.com>
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>

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zynqmp: pm: Implemented 'get_op_characteristic' PM API call

Signed-off-by: Anes Hadziahmetagic <anes.hadziahmetagic@aggios.com>
Signed-off-by: Filip Drazic <filip.drazic@aggios.com>
Signed-off-by: S

zynqmp: pm: Implemented 'get_op_characteristic' PM API call

Signed-off-by: Anes Hadziahmetagic <anes.hadziahmetagic@aggios.com>
Signed-off-by: Filip Drazic <filip.drazic@aggios.com>
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>

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zynqmp: pm: Removed double declaration of pm_ipi_send functions

Functions pm_ipi_send and pm_ipi_send_sync are declared in pm_ipi.h

Signed-off-by: Filip Drazic <filip.drazic@aggios.com>
Signed-off-

zynqmp: pm: Removed double declaration of pm_ipi_send functions

Functions pm_ipi_send and pm_ipi_send_sync are declared in pm_ipi.h

Signed-off-by: Filip Drazic <filip.drazic@aggios.com>
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>

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zynqmp: Reduce mapped memory area

The GIC area is specified larger than it needs to be and can be reduced.
Which allows reducing the structures required for the translation tables
as well.
This resu

zynqmp: Reduce mapped memory area

The GIC area is specified larger than it needs to be and can be reduced.
Which allows reducing the structures required for the translation tables
as well.
This results in a reduction of memory footprint of ca. 4k.

Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Acked-by: Michal Simek <michal.simek@xilinx.com>

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Replace Rockchip delay timer by generic one

Use the generic delay timer instead of having a specific platform
file for configuring it.

Change-Id: Ifa68b9c97cd96ae1190cee74d22d729af95e4537

Replace MediaTek delay timer by generic one

Use the generic delay timer instead of having a specific platform
file for configuring it.

Change-Id: If6b8f60bc04230f4b85b2bcc1b670fc65461214e

Replace SP804 timer by generic delay timer on FVP

Added a build flag to select the generic delay timer on FVP instead
of the SP804 timer. By default, the generic one will be selected. The
user guide

Replace SP804 timer by generic delay timer on FVP

Added a build flag to select the generic delay timer on FVP instead
of the SP804 timer. By default, the generic one will be selected. The
user guide has been updated.

Change-Id: Ica34425c6d4ed95a187b529c612f6d3b26b78bc6

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Implement plat_get_syscnt_freq2 on platforms

Replaced plat_get_syscnt_freq by plat_get_syscnt_freq2 on all
upstream platforms.

Change-Id: I3248f3f65a16dc5e9720012a05c35b9e3ba6abbe

Add 32 bit version of plat_get_syscnt_freq

Added plat_get_syscnt_freq2, which is a 32 bit variant of the 64 bit
plat_get_syscnt_freq. The old one has been flagged as deprecated.
Common code has been

Add 32 bit version of plat_get_syscnt_freq

Added plat_get_syscnt_freq2, which is a 32 bit variant of the 64 bit
plat_get_syscnt_freq. The old one has been flagged as deprecated.
Common code has been updated to use this new version. Porting guide
has been updated.

Change-Id: I9e913544926c418970972bfe7d81ee88b4da837e

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Merge pull request #622 from mtk09422/hw-crypt-v3

Hw crypt v3

MT8173: Add Sip function for MTK HW crypt driver

Change-Id: Idc40cc6243e532567ec4334ae37d97c003c90bfa
Signed-off-by: Yi Zheng <yi.zheng@mediatek.com>

mt8173: Reorganize plat SiP functions

Due to the changes in Mediatek platform common code, we need to move
plat related SiP functions to plat folder.

Change-Id: I6b14b988235205a5858b4bf49043bc79d05

mt8173: Reorganize plat SiP functions

Due to the changes in Mediatek platform common code, we need to move
plat related SiP functions to plat folder.

Change-Id: I6b14b988235205a5858b4bf49043bc79d0512b06
Signed-off-by: Jimmy Huang <jimmy.huang@mediatek.com>

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Rockchip: Add some debug assertions in the PMU driver

This patch adds some debug assertions ensuring that array indices
are within the bounds of the array.

Change-Id: I96ee81d14834c1e92cdfb7e60b499

Rockchip: Add some debug assertions in the PMU driver

This patch adds some debug assertions ensuring that array indices
are within the bounds of the array.

Change-Id: I96ee81d14834c1e92cdfb7e60b49995cdacfd93a

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Merge pull request #618 from rockchip-linux/fixes-for-suspend/resume

rockchip: support the suspend/resume for rk3399

Merge pull request #617 from leon-chen-mtk/refactor_common_1

Refactor MediaTek platform common code