xref: /rk3399_ARM-atf/plat/mediatek/common/mtk_plat_common.c (revision 2edaa749f06d2708194003df7bc9fa1af78ffd2b)
1 /*
2  * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
3  *
4  * Redistribution and use in source and binary forms, with or without
5  * modification, are permitted provided that the following conditions are met:
6  *
7  * Redistributions of source code must retain the above copyright notice, this
8  * list of conditions and the following disclaimer.
9  *
10  * Redistributions in binary form must reproduce the above copyright notice,
11  * this list of conditions and the following disclaimer in the documentation
12  * and/or other materials provided with the distribution.
13  *
14  * Neither the name of ARM nor the names of its contributors may be used
15  * to endorse or promote products derived from this software without specific
16  * prior written permission.
17  *
18  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28  * POSSIBILITY OF SUCH DAMAGE.
29  */
30 #include <arch_helpers.h>
31 #include <arm_gic.h>
32 #include <bl_common.h>
33 #include <cci.h>
34 #include <console.h>
35 #include <debug.h>
36 #include <mmio.h>
37 #include <mtk_plat_common.h>
38 #include <mtk_sip_svc.h>
39 #include <platform.h>
40 #include <plat_private.h>
41 #include <xlat_tables.h>
42 
43 struct atf_arg_t gteearg;
44 
45 void clean_top_32b_of_param(uint32_t smc_fid,
46 				uint64_t *px1,
47 				uint64_t *px2,
48 				uint64_t *px3,
49 				uint64_t *px4)
50 {
51 	/* if parameters from SMC32. Clean top 32 bits */
52 	if (0 == (smc_fid & SMC_AARCH64_BIT)) {
53 		*px1 = *px1 & SMC32_PARAM_MASK;
54 		*px2 = *px2 & SMC32_PARAM_MASK;
55 		*px3 = *px3 & SMC32_PARAM_MASK;
56 		*px4 = *px4 & SMC32_PARAM_MASK;
57 	}
58 }
59 
60 #if MTK_SIP_KERNEL_BOOT_ENABLE
61 static struct kernel_info k_info;
62 
63 static void save_kernel_info(uint64_t pc,
64 			uint64_t r0,
65 			uint64_t r1,
66 			uint64_t k32_64)
67 {
68 	k_info.k32_64 = k32_64;
69 	k_info.pc = pc;
70 
71 	if (LINUX_KERNEL_32 ==  k32_64) {
72 		/* for 32 bits kernel */
73 		k_info.r0 = 0;
74 		/* machtype */
75 		k_info.r1 = r0;
76 		/* tags */
77 		k_info.r2 = r1;
78 	} else {
79 		/* for 64 bits kernel */
80 		k_info.r0 = r0;
81 		k_info.r1 = r1;
82 	}
83 }
84 
85 uint64_t get_kernel_info_pc(void)
86 {
87 	return k_info.pc;
88 }
89 
90 uint64_t get_kernel_info_r0(void)
91 {
92 	return k_info.r0;
93 }
94 
95 uint64_t get_kernel_info_r1(void)
96 {
97 	return k_info.r1;
98 }
99 
100 uint64_t get_kernel_info_r2(void)
101 {
102 	return k_info.r2;
103 }
104 
105 void boot_to_kernel(uint64_t x1, uint64_t x2, uint64_t x3, uint64_t x4)
106 {
107 	static uint8_t kernel_boot_once_flag;
108 	/* only support in booting flow */
109 	if (0 == kernel_boot_once_flag) {
110 		kernel_boot_once_flag = 1;
111 
112 		console_init(gteearg.atf_log_port,
113 			UART_CLOCK, UART_BAUDRATE);
114 		INFO("save kernel info\n");
115 		save_kernel_info(x1, x2, x3, x4);
116 		bl31_prepare_kernel_entry(x4);
117 		INFO("el3_exit\n");
118 		console_uninit();
119 	}
120 }
121 #endif
122 
123 uint32_t plat_get_spsr_for_bl33_entry(void)
124 {
125 	unsigned int mode;
126 	uint32_t spsr;
127 	unsigned int ee;
128 	unsigned long daif;
129 
130 	INFO("Secondary bootloader is AArch32\n");
131 	mode = MODE32_svc;
132 	ee = 0;
133 	/*
134 	 * TODO: Choose async. exception bits if HYP mode is not
135 	 * implemented according to the values of SCR.{AW, FW} bits
136 	 */
137 	daif = DAIF_ABT_BIT | DAIF_IRQ_BIT | DAIF_FIQ_BIT;
138 
139 	spsr = SPSR_MODE32(mode, 0, ee, daif);
140 	return spsr;
141 }
142