zynqmp: Read silicon ID register only once

The silicon ID does not change at runtime. Skip the IO access if the
ID has been read before.

Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>

zynqmp: Read silicon ID register only once

The silicon ID does not change at runtime. Skip the IO access if the
ID has been read before.

Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Acked-by: Michal Simek <michal.simek@xilinx.com>

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Merge pull request #752 from rockchip-linux/rk3399/fixes-s2r-1107

rk3399: fixes and updates for s2r

Merge pull request #750 from jwerner-chromium/m0_build

RK3399 M0 build system improvements

rockchip: remove no needed code for rk3399

We have do something for clocks gate.

Fox example as the below:
susped:
clk_gate_con_save();
clk_gate_con_disable();

resume:
clk_gate_con_restore();
--

rockchip: remove no needed code for rk3399

We have do something for clocks gate.

Fox example as the below:
susped:
clk_gate_con_save();
clk_gate_con_disable();

resume:
clk_gate_con_restore();
--

SO, add the plls_suspend_prepare() and plls_resume_finish() are not
necessary to S2R, that will save S2R time if remove them.

BRANCH=none
BUG=chrome-os-partner:58870,chrome-os-partner:55934
TEST=build kevin, two dogfooders with suspend_stress_test
passing 3000 cycles and still going on.

Change-Id: Icfbabc0b3ea8d2b5108d4f3de99a803b6d459669
Signed-off-by: Caesar Wang <wxt@rock-chips.com>

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rockchip: disable watchdog during suspend

The CA53 and CM0 WDT clock gating in rk3399 SGRF, and ATF is in charge of
it because the kernel can't touch SGRF.

Basically the WDT didn't stop at suspend

rockchip: disable watchdog during suspend

The CA53 and CM0 WDT clock gating in rk3399 SGRF, and ATF is in charge of
it because the kernel can't touch SGRF.

Basically the WDT didn't stop at suspend time, it just switched from the
24M to the 32k clock. That meant that the WDT would fire if you slept for
long enough. In other word, the watchdog timer over count will increase to
750 (24*1000/32) times.
The RK3399 HW watchdog interval is 21 seconds. When machine enters the
suspend, the watchdog will reset the system after 35.7 (750/21) hours.

BUG=chrome-os-partner:59257
TEST=daisydog checked and set value, powerd_dbus_suspend to verify.

Change-Id: I88bb2a05b7d67d5ffd292f9d05d033ae9a6a3593
Signed-off-by: Caesar Wang <wxt@rock-chips.com>

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rockchip: Add proper dependency tracking to M0 Makefile

This patch adds dependency rule generation and inclusion to the M0
Makefile, so that M0 objects will get correctly remade with an
incremental

rockchip: Add proper dependency tracking to M0 Makefile

This patch adds dependency rule generation and inclusion to the M0
Makefile, so that M0 objects will get correctly remade with an
incremental build if a header file they included changed.

Change-Id: I2067bd9fd4d9dad3e77a09cbf09c7b4db3c1eda5
Signed-off-by: Julius Werner <jwerner@chromium.org>

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rockchip: Clean up parent directory creation for M0

The dependencies in the M0 Makefile are not correctly laid out, which
may lead to errors with make -j if the binary target gets evaluated
before t

rockchip: Clean up parent directory creation for M0

The dependencies in the M0 Makefile are not correctly laid out, which
may lead to errors with make -j if the binary target gets evaluated
before the target that creates the directory. In addition, the M0
Makefile just calls mkdir without using the platform-independent macros
from the main ARM TF build system. This patch fixes those issues,
removes some unused (and broken) M0 build targets and merges the two M0
output directories into one (since there's no real point splitting it up
and it creates more hassle).

Change-Id: Ia5002479cf9c57fea7aefa8ca88e373df3a51f61
Signed-off-by: Julius Werner <jwerner@chromium.org>

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Merge pull request #745 from rockchip-linux/support-rk3399-dram

Support rk3399 dram

Merge pull request #742 from masahir0y/misc

Comment fixes and .gitignore update

rockchip: close the PD center logic during suspend

The RK3399 supports close the center logic enter power mode,
so we can close PD_CENTER to save more power during suspend.
Therefore, we need to sup

rockchip: close the PD center logic during suspend

The RK3399 supports close the center logic enter power mode,
so we can close PD_CENTER to save more power during suspend.
Therefore, we need to support save/restore the DDR PHY and
controller registers during suspend/resume.

Also, need CL (http://crosreview.com/397399) to check disabling
center logic.

Change-Id: I288defd8e9caa3846d9fa663a33e4d51df1aaa5d
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Derek Basehore <dbasehore@chromium.org>
Signed-off-by: Caesar Wang <wxt@rock-chips.com>

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rockchip: add support save/restore configuration for DDR during enter S3

This patch intend to support save the registers of the DDR controller
and PHY before suspend, and restore them after resume.

rockchip: add support save/restore configuration for DDR during enter S3

This patch intend to support save the registers of the DDR controller
and PHY before suspend, and restore them after resume.

Change-Id: Ia10b476c0b837628ac0f365416a7118292753e96
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Derek Basehore <dbasehore@chromium.org>
Signed-off-by: Caesar Wang <wxt@rock-chips.com>

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rockchip: Change dmc register accesses to ATF style for rk3399

This changes the style of dmc register accesses to be a read/write on
a base address plus a register offset instead of reinterpretting

rockchip: Change dmc register accesses to ATF style for rk3399

This changes the style of dmc register accesses to be a read/write on
a base address plus a register offset instead of reinterpretting a
base address as a struct and accessing members within that struct.

Change-Id: Iead097cd6afdb830d8bc193608cd39d01ce5a6bc
Signed-off-by: Derek Basehore <dbasehore@chromium.org>
Signed-off-by: Caesar Wang <wxt@rock-chips.com>

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rockchip: Break out common dram code for rk3399

This renames dram.c and dram.h to dfs.c and dfs.h respectively. This
is to make room for common functionality between frequency scaling and
suspend co

rockchip: Break out common dram code for rk3399

This renames dram.c and dram.h to dfs.c and dfs.h respectively. This
is to make room for common functionality between frequency scaling and
suspend code for the DRAM in a pair of common files named dram.c and
dram.h. It also removes a duplicate enum definition from
dram_spec_timing.h

Change-Id: Ibfa1041f8781401f9d27901fe8c61862bcb05562
Signed-off-by: Derek Basehore <dbasehore@chromium.org>
Signed-off-by: Caesar Wang <wxt@rock-chips.com>

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rockchip: move pmu registers into another header for rk3399

This moves the PMU register definitions into another file for use in
later patches.

Change-Id: I8b5f1e7938b63ada6a743cf9661c3e474e96e4e4

rockchip: move pmu registers into another header for rk3399

This moves the PMU register definitions into another file for use in
later patches.

Change-Id: I8b5f1e7938b63ada6a743cf9661c3e474e96e4e4
Signed-off-by: Derek Basehore <dbasehore@chromium.org>
Signed-off-by: Caesar Wang <wxt@rock-chips.com>

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Merge pull request #724 from rockchip-linux/support-rk3399-sdram

rockchip: optimize the link mechanism for SRAM code

Merge pull request #739 from rockchip-linux/fixes-latency

rockchip: fix A72 L2CTLR_DATA_RAM_LATENCY to 5

rockchip: fix A72 L2CTLR_DATA_RAM_LATENCY to 5

The default value of L2CTLR_DATA_RAM_LATENCY is 2, depends to
the test result on rk3399, the A72 will need lower voltage for
high frequency if it's set

rockchip: fix A72 L2CTLR_DATA_RAM_LATENCY to 5

The default value of L2CTLR_DATA_RAM_LATENCY is 2, depends to
the test result on rk3399, the A72 will need lower voltage for
high frequency if it's set to be 5, and almost no effect on performance.

Change-Id: I99a6a43edcc0c58f7775c10f4b85669dc3eff66d
Signed-off-by: Caesar Wang <wxt@rock-chips.com>

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rockchip: clear the power mode status via M0

Due to the PMU design, the PMU may not clear the WAKEUP bit after
wakeup, therefore, the state machine at the power mode may enter
the infinite loop duri

rockchip: clear the power mode status via M0

Due to the PMU design, the PMU may not clear the WAKEUP bit after
wakeup, therefore, the state machine at the power mode may enter
the infinite loop during WFI.

There is a solution that we can use the M0 to monitor the WAKEUP
bit and clear it during power mode, then the state machine will be
recovered immediately. Then, the DUT can exit the WFI normally.

Change-Id: I303628553b728c214bf2d436bd3122032b5e669c
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Caesar Wang <wxt@rock-chips.com>

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rockchip: add M0 source code and build system for RK3399

This CL supports add M0 source code to built into the bl31.bin, the
goal is that we can load the M0 code binary into SRAM and execute it.

We

rockchip: add M0 source code and build system for RK3399

This CL supports add M0 source code to built into the bl31.bin, the
goal is that we can load the M0 code binary into SRAM and execute it.

We need the M0 help us to clean the power_mode_en bit during the AP
PMU enter the state machine with interrupt, and avoid to the AP can
not exit the loop forever.

Change-Id: I844582c54a1f0d44ca41290d44618df58679f341
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Signed-off-by: Caesar Wang <wxt@rock-chips.com>

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rockchip: optimize the link mechanism for SRAM code

Add the common extra.ld.S and customized rk3399.ld.S to extend
to more features for different platforms.
For example, we can add SRAM section and

rockchip: optimize the link mechanism for SRAM code

Add the common extra.ld.S and customized rk3399.ld.S to extend
to more features for different platforms.
For example, we can add SRAM section and specific address to
load there if we need it, and the common bl31.ld.S not need to
be modified.

Therefore, we can remove the unused codes which copying explicitly
from the function pmusram_prepare(). It looks like more clear.

Change-Id: Ibffa2da5e8e3d1d2fca80085ebb296ceb967fce8
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Caesar Wang <wxt@rock-chips.com>

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Fix comment of plat_reset_handler stub

As described in the Porting Guide, plat_reset_handler should
preserve x19 to x29.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

rockchip: fixes the wrong CLKSEL_CON count for CRU

The CRU_CLKSEL_COUNT value is 108, not 0x108.

Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Change-Id: Ib9db066b8b3ecafcee7f645dd5633b55a808e3d7

Merge pull request #729 from dp-arm/dp/arm-sip

Add instrumentation support for PSCI

Introduce ARM SiP service

This patch adds ARM SiP service for use by ARM standard platforms.
This service is added to support the SMC interface for the Performance
measurement framework(PMF).

Chang

Introduce ARM SiP service

This patch adds ARM SiP service for use by ARM standard platforms.
This service is added to support the SMC interface for the Performance
measurement framework(PMF).

Change-Id: I26f5712f9ab54f5f721dd4781e35a16f40aacc44
Signed-off-by: dp-arm <dimitris.papastamos@arm.com>

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rockchip: fixes the clock select and divide register for rk3399

As the new RK3399TRM v1.1, there are some wrong set for CRU_CLKSEL_CON
register.

As the CRU_CLKSEL_CON96～107 high 16-bit isn't write

rockchip: fixes the clock select and divide register for rk3399

As the new RK3399TRM v1.1, there are some wrong set for CRU_CLKSEL_CON
register.

As the CRU_CLKSEL_CON96～107 high 16-bit isn't write mask and the
CRU_CLKSEL_CON offset is 0x100,not 0x80.

Change-Id: Ie127e9de74b87100af9a0150aad43e89e4972529

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