1 /* 2 * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <arch_helpers.h> 32 #include <debug.h> 33 #include <delay_timer.h> 34 #include <mmio.h> 35 #include <platform_def.h> 36 #include <plat_private.h> 37 #include <rk3399_def.h> 38 #include <rk3399m0.h> 39 #include <soc.h> 40 41 /* Table of regions to map using the MMU. */ 42 const mmap_region_t plat_rk_mmap[] = { 43 MAP_REGION_FLAT(RK3399_DEV_RNG0_BASE, RK3399_DEV_RNG0_SIZE, 44 MT_DEVICE | MT_RW | MT_SECURE), 45 46 { 0 } 47 }; 48 49 /* The RockChip power domain tree descriptor */ 50 const unsigned char rockchip_power_domain_tree_desc[] = { 51 /* No of root nodes */ 52 PLATFORM_SYSTEM_COUNT, 53 /* No of children for the root node */ 54 PLATFORM_CLUSTER_COUNT, 55 /* No of children for the first cluster node */ 56 PLATFORM_CLUSTER0_CORE_COUNT, 57 /* No of children for the second cluster node */ 58 PLATFORM_CLUSTER1_CORE_COUNT 59 }; 60 61 void secure_timer_init(void) 62 { 63 mmio_write_32(STIMER1_CHN_BASE(5) + TIMER_END_COUNT0, 0xffffffff); 64 mmio_write_32(STIMER1_CHN_BASE(5) + TIMER_END_COUNT1, 0xffffffff); 65 66 mmio_write_32(STIMER1_CHN_BASE(5) + TIMER_INIT_COUNT0, 0x0); 67 mmio_write_32(STIMER1_CHN_BASE(5) + TIMER_INIT_COUNT0, 0x0); 68 69 /* auto reload & enable the timer */ 70 mmio_write_32(STIMER1_CHN_BASE(5) + TIMER_CONTROL_REG, 71 TIMER_EN | TIMER_FMODE); 72 } 73 74 void sgrf_init(void) 75 { 76 /* security config for master */ 77 mmio_write_32(SGRF_BASE + SGRF_SOC_CON3_7(5), 78 SGRF_SOC_CON_WMSK | SGRF_SOC_ALLMST_NS); 79 mmio_write_32(SGRF_BASE + SGRF_SOC_CON3_7(6), 80 SGRF_SOC_CON_WMSK | SGRF_SOC_ALLMST_NS); 81 mmio_write_32(SGRF_BASE + SGRF_SOC_CON3_7(7), 82 SGRF_SOC_CON_WMSK | SGRF_SOC_ALLMST_NS); 83 84 /* security config for slave */ 85 mmio_write_32(SGRF_BASE + SGRF_PMU_SLV_CON0_1(0), 86 SGRF_PMU_SLV_S_CFGED | 87 SGRF_PMU_SLV_CRYPTO1_NS); 88 mmio_write_32(SGRF_BASE + SGRF_PMU_SLV_CON0_1(1), 89 SGRF_PMU_SLV_CON1_CFG); 90 mmio_write_32(SGRF_BASE + SGRF_SLV_SECURE_CON0_4(0), 91 SGRF_SLV_S_WMSK | SGRF_SLV_S_ALL_NS); 92 mmio_write_32(SGRF_BASE + SGRF_SLV_SECURE_CON0_4(1), 93 SGRF_SLV_S_WMSK | SGRF_SLV_S_ALL_NS); 94 mmio_write_32(SGRF_BASE + SGRF_SLV_SECURE_CON0_4(2), 95 SGRF_SLV_S_WMSK | SGRF_SLV_S_ALL_NS); 96 mmio_write_32(SGRF_BASE + SGRF_SLV_SECURE_CON0_4(3), 97 SGRF_SLV_S_WMSK | SGRF_SLV_S_ALL_NS); 98 mmio_write_32(SGRF_BASE + SGRF_SLV_SECURE_CON0_4(4), 99 SGRF_SLV_S_WMSK | SGRF_SLV_S_ALL_NS); 100 101 /* security config for ddr memery */ 102 mmio_write_32(SGRF_BASE + SGRF_DDRRGN_CON0_16(16), 103 SGRF_DDR_RGN_BYPS); 104 } 105 106 static void dma_secure_cfg(uint32_t secure) 107 { 108 if (secure) { 109 /* rgn0 secure for dmac0 and dmac1 */ 110 mmio_write_32(SGRF_BASE + SGRF_DDRRGN_CON20_34(22), 111 SGRF_L_MST_S_DDR_RGN(0) | /* dmac0 */ 112 SGRF_H_MST_S_DDR_RGN(0) /* dmac1 */ 113 ); 114 115 /* set dmac0 boot, under secure state */ 116 mmio_write_32(SGRF_BASE + SGRF_SOC_CON8_15(8), 117 SGRF_DMAC_CFG_S); 118 mmio_write_32(SGRF_BASE + SGRF_SOC_CON8_15(9), 119 SGRF_DMAC_CFG_S); 120 mmio_write_32(SGRF_BASE + SGRF_SOC_CON8_15(10), 121 SGRF_DMAC_CFG_S); 122 123 /* dmac0 soft reset */ 124 mmio_write_32(CRU_BASE + CRU_SOFTRST_CON(10), 125 CRU_DMAC0_RST); 126 udelay(5); 127 mmio_write_32(CRU_BASE + CRU_SOFTRST_CON(10), 128 CRU_DMAC0_RST_RLS); 129 130 /* set dmac1 boot, under secure state */ 131 mmio_write_32(SGRF_BASE + SGRF_SOC_CON8_15(11), 132 SGRF_DMAC_CFG_S); 133 mmio_write_32(SGRF_BASE + SGRF_SOC_CON8_15(12), 134 SGRF_DMAC_CFG_S); 135 mmio_write_32(SGRF_BASE + SGRF_SOC_CON8_15(13), 136 SGRF_DMAC_CFG_S); 137 mmio_write_32(SGRF_BASE + SGRF_SOC_CON8_15(14), 138 SGRF_DMAC_CFG_S); 139 mmio_write_32(SGRF_BASE + SGRF_SOC_CON8_15(15), 140 SGRF_DMAC_CFG_S); 141 142 /* dmac1 soft reset */ 143 mmio_write_32(CRU_BASE + CRU_SOFTRST_CON(10), 144 CRU_DMAC1_RST); 145 udelay(5); 146 mmio_write_32(CRU_BASE + CRU_SOFTRST_CON(10), 147 CRU_DMAC1_RST_RLS); 148 } else { 149 /* rgn non-secure for dmac0 and dmac1 */ 150 mmio_write_32(SGRF_BASE + SGRF_DDRRGN_CON20_34(22), 151 DMAC1_RGN_NS | DMAC0_RGN_NS); 152 153 /* set dmac0 boot, under non-secure state */ 154 mmio_write_32(SGRF_BASE + SGRF_SOC_CON8_15(8), 155 DMAC0_BOOT_CFG_NS); 156 mmio_write_32(SGRF_BASE + SGRF_SOC_CON8_15(9), 157 DMAC0_BOOT_PERIPH_NS); 158 mmio_write_32(SGRF_BASE + SGRF_SOC_CON8_15(10), 159 DMAC0_BOOT_ADDR_NS); 160 161 /* dmac0 soft reset */ 162 mmio_write_32(CRU_BASE + CRU_SOFTRST_CON(10), 163 CRU_DMAC0_RST); 164 udelay(5); 165 mmio_write_32(CRU_BASE + CRU_SOFTRST_CON(10), 166 CRU_DMAC0_RST_RLS); 167 168 /* set dmac1 boot, under non-secure state */ 169 mmio_write_32(SGRF_BASE + SGRF_SOC_CON8_15(11), 170 DMAC1_BOOT_CFG_NS); 171 mmio_write_32(SGRF_BASE + SGRF_SOC_CON8_15(12), 172 DMAC1_BOOT_PERIPH_L_NS); 173 mmio_write_32(SGRF_BASE + SGRF_SOC_CON8_15(13), 174 DMAC1_BOOT_ADDR_NS); 175 mmio_write_32(SGRF_BASE + SGRF_SOC_CON8_15(14), 176 DMAC1_BOOT_PERIPH_H_NS); 177 mmio_write_32(SGRF_BASE + SGRF_SOC_CON8_15(15), 178 DMAC1_BOOT_IRQ_NS); 179 180 /* dmac1 soft reset */ 181 mmio_write_32(CRU_BASE + CRU_SOFTRST_CON(10), 182 CRU_DMAC1_RST); 183 udelay(5); 184 mmio_write_32(CRU_BASE + CRU_SOFTRST_CON(10), 185 CRU_DMAC1_RST_RLS); 186 } 187 } 188 189 /* pll suspend */ 190 struct deepsleep_data_s slp_data; 191 192 static void pll_suspend_prepare(uint32_t pll_id) 193 { 194 int i; 195 196 if (pll_id == PPLL_ID) 197 for (i = 0; i < PLL_CON_COUNT; i++) 198 slp_data.plls_con[pll_id][i] = 199 mmio_read_32(PMUCRU_BASE + PMUCRU_PPLL_CON(i)); 200 else 201 for (i = 0; i < PLL_CON_COUNT; i++) 202 slp_data.plls_con[pll_id][i] = 203 mmio_read_32(CRU_BASE + CRU_PLL_CON(pll_id, i)); 204 } 205 206 static void set_pll_slow_mode(uint32_t pll_id) 207 { 208 if (pll_id == PPLL_ID) 209 mmio_write_32(PMUCRU_BASE + PMUCRU_PPLL_CON(3), PLL_SLOW_MODE); 210 else 211 mmio_write_32((CRU_BASE + 212 CRU_PLL_CON(pll_id, 3)), PLL_SLOW_MODE); 213 } 214 215 static void set_pll_normal_mode(uint32_t pll_id) 216 { 217 if (pll_id == PPLL_ID) 218 mmio_write_32(PMUCRU_BASE + PMUCRU_PPLL_CON(3), PLL_NOMAL_MODE); 219 else 220 mmio_write_32(CRU_BASE + 221 CRU_PLL_CON(pll_id, 3), PLL_NOMAL_MODE); 222 } 223 224 static void set_pll_bypass(uint32_t pll_id) 225 { 226 if (pll_id == PPLL_ID) 227 mmio_write_32(PMUCRU_BASE + 228 PMUCRU_PPLL_CON(3), PLL_BYPASS_MODE); 229 else 230 mmio_write_32(CRU_BASE + 231 CRU_PLL_CON(pll_id, 3), PLL_BYPASS_MODE); 232 } 233 234 static void _pll_suspend(uint32_t pll_id) 235 { 236 set_pll_slow_mode(pll_id); 237 set_pll_bypass(pll_id); 238 } 239 240 void disable_dvfs_plls(void) 241 { 242 _pll_suspend(CPLL_ID); 243 _pll_suspend(NPLL_ID); 244 _pll_suspend(VPLL_ID); 245 _pll_suspend(GPLL_ID); 246 _pll_suspend(ABPLL_ID); 247 _pll_suspend(ALPLL_ID); 248 } 249 250 void disable_nodvfs_plls(void) 251 { 252 _pll_suspend(PPLL_ID); 253 } 254 255 void plls_suspend_prepare(void) 256 { 257 uint32_t i, pll_id; 258 259 for (pll_id = ALPLL_ID; pll_id < END_PLL_ID; pll_id++) 260 pll_suspend_prepare(pll_id); 261 262 for (i = 0; i < CRU_CLKSEL_COUNT; i++) 263 slp_data.cru_clksel_con[i] = 264 mmio_read_32(CRU_BASE + CRU_CLKSEL_CON(i)); 265 266 for (i = 0; i < PMUCRU_CLKSEL_CONUT; i++) 267 slp_data.pmucru_clksel_con[i] = 268 mmio_read_32(PMUCRU_BASE + 269 PMUCRU_CLKSEL_OFFSET + i * REG_SIZE); 270 } 271 272 void clk_gate_con_save(void) 273 { 274 uint32_t i = 0; 275 276 for (i = 0; i < PMUCRU_GATE_COUNT; i++) 277 slp_data.pmucru_gate_con[i] = 278 mmio_read_32(PMUCRU_BASE + PMUCRU_GATE_CON(i)); 279 280 for (i = 0; i < CRU_GATE_COUNT; i++) 281 slp_data.cru_gate_con[i] = 282 mmio_read_32(CRU_BASE + CRU_GATE_CON(i)); 283 } 284 285 void clk_gate_con_disable(void) 286 { 287 uint32_t i; 288 289 for (i = 0; i < PMUCRU_GATE_COUNT; i++) 290 mmio_write_32(PMUCRU_BASE + PMUCRU_GATE_CON(i), REG_SOC_WMSK); 291 292 for (i = 0; i < CRU_GATE_COUNT; i++) 293 mmio_write_32(CRU_BASE + CRU_GATE_CON(i), REG_SOC_WMSK); 294 } 295 296 void clk_gate_con_restore(void) 297 { 298 uint32_t i; 299 300 for (i = 0; i < PMUCRU_GATE_COUNT; i++) 301 mmio_write_32(PMUCRU_BASE + PMUCRU_GATE_CON(i), 302 REG_SOC_WMSK | slp_data.pmucru_gate_con[i]); 303 304 for (i = 0; i < CRU_GATE_COUNT; i++) 305 mmio_write_32(CRU_BASE + CRU_GATE_CON(i), 306 REG_SOC_WMSK | slp_data.cru_gate_con[i]); 307 } 308 309 static void set_plls_nobypass(uint32_t pll_id) 310 { 311 if (pll_id == PPLL_ID) 312 mmio_write_32(PMUCRU_BASE + PMUCRU_PPLL_CON(3), 313 PLL_NO_BYPASS_MODE); 314 else 315 mmio_write_32(CRU_BASE + CRU_PLL_CON(pll_id, 3), 316 PLL_NO_BYPASS_MODE); 317 } 318 319 static void _pll_resume(uint32_t pll_id) 320 { 321 set_plls_nobypass(pll_id); 322 set_pll_normal_mode(pll_id); 323 } 324 325 void plls_resume_finish(void) 326 { 327 int i; 328 329 for (i = 0; i < CRU_CLKSEL_COUNT; i++) 330 mmio_write_32((CRU_BASE + CRU_CLKSEL_CON(i)), 331 REG_SOC_WMSK | slp_data.cru_clksel_con[i]); 332 for (i = 0; i < PMUCRU_CLKSEL_CONUT; i++) 333 mmio_write_32((PMUCRU_BASE + 334 PMUCRU_CLKSEL_OFFSET + i * REG_SIZE), 335 REG_SOC_WMSK | slp_data.pmucru_clksel_con[i]); 336 } 337 338 void enable_dvfs_plls(void) 339 { 340 _pll_resume(ALPLL_ID); 341 _pll_resume(ABPLL_ID); 342 _pll_resume(GPLL_ID); 343 _pll_resume(VPLL_ID); 344 _pll_resume(NPLL_ID); 345 _pll_resume(CPLL_ID); 346 } 347 348 void enable_nodvfs_plls(void) 349 { 350 _pll_resume(PPLL_ID); 351 } 352 353 void soc_global_soft_reset_init(void) 354 { 355 mmio_write_32(PMUCRU_BASE + CRU_PMU_RSTHOLD_CON(1), 356 CRU_PMU_SGRF_RST_RLS); 357 358 mmio_clrbits_32(CRU_BASE + CRU_GLB_RST_CON, 359 CRU_PMU_WDTRST_MSK | CRU_PMU_FIRST_SFTRST_MSK); 360 } 361 362 void __dead2 soc_global_soft_reset(void) 363 { 364 set_pll_slow_mode(VPLL_ID); 365 set_pll_slow_mode(NPLL_ID); 366 set_pll_slow_mode(GPLL_ID); 367 set_pll_slow_mode(CPLL_ID); 368 set_pll_slow_mode(PPLL_ID); 369 set_pll_slow_mode(ABPLL_ID); 370 set_pll_slow_mode(ALPLL_ID); 371 372 dsb(); 373 374 mmio_write_32(CRU_BASE + CRU_GLB_SRST_FST, GLB_SRST_FST_CFG_VAL); 375 376 /* 377 * Maybe the HW needs some times to reset the system, 378 * so we do not hope the core to excute valid codes. 379 */ 380 while (1) 381 ; 382 } 383 384 static void soc_m0_init(void) 385 { 386 /* secure config for pmu M0 */ 387 mmio_write_32(SGRF_BASE + SGRF_PMU_CON(0), WMSK_BIT(7)); 388 389 /* set the execute address for M0 */ 390 mmio_write_32(SGRF_BASE + SGRF_PMU_CON(3), 391 BITS_WITH_WMASK((M0_BINCODE_BASE >> 12) & 0xffff, 392 0xffff, 0)); 393 mmio_write_32(SGRF_BASE + SGRF_PMU_CON(7), 394 BITS_WITH_WMASK((M0_BINCODE_BASE >> 28) & 0xf, 395 0xf, 0)); 396 } 397 398 void plat_rockchip_soc_init(void) 399 { 400 secure_timer_init(); 401 dma_secure_cfg(0); 402 sgrf_init(); 403 soc_global_soft_reset_init(); 404 plat_rockchip_gpio_init(); 405 soc_m0_init(); 406 } 407