1 /* 2 * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <debug.h> 32 #include <mmio.h> 33 #include <plat_private.h> 34 #include "dfs.h" 35 #include "dram.h" 36 #include "dram_spec_timing.h" 37 #include "string.h" 38 #include "soc.h" 39 #include "pmu.h" 40 41 #include <delay_timer.h> 42 43 #define CTL_TRAINING (1) 44 #define PI_TRAINING (!CTL_TRAINING) 45 46 #define EN_READ_GATE_TRAINING (1) 47 #define EN_CA_TRAINING (0) 48 #define EN_WRITE_LEVELING (0) 49 #define EN_READ_LEVELING (0) 50 #define EN_WDQ_LEVELING (0) 51 52 #define ENPER_CS_TRAINING_FREQ (933) 53 54 struct pll_div { 55 unsigned int mhz; 56 unsigned int refdiv; 57 unsigned int fbdiv; 58 unsigned int postdiv1; 59 unsigned int postdiv2; 60 unsigned int frac; 61 unsigned int freq; 62 }; 63 64 static const struct pll_div dpll_rates_table[] = { 65 66 /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2 */ 67 {.mhz = 933, .refdiv = 3, .fbdiv = 350, .postdiv1 = 3, .postdiv2 = 1}, 68 {.mhz = 800, .refdiv = 1, .fbdiv = 100, .postdiv1 = 3, .postdiv2 = 1}, 69 {.mhz = 732, .refdiv = 1, .fbdiv = 61, .postdiv1 = 2, .postdiv2 = 1}, 70 {.mhz = 666, .refdiv = 1, .fbdiv = 111, .postdiv1 = 4, .postdiv2 = 1}, 71 {.mhz = 600, .refdiv = 1, .fbdiv = 50, .postdiv1 = 2, .postdiv2 = 1}, 72 {.mhz = 528, .refdiv = 1, .fbdiv = 66, .postdiv1 = 3, .postdiv2 = 1}, 73 {.mhz = 400, .refdiv = 1, .fbdiv = 50, .postdiv1 = 3, .postdiv2 = 1}, 74 {.mhz = 300, .refdiv = 1, .fbdiv = 50, .postdiv1 = 4, .postdiv2 = 1}, 75 {.mhz = 200, .refdiv = 1, .fbdiv = 50, .postdiv1 = 3, .postdiv2 = 2}, 76 }; 77 78 static struct rk3399_ddr_pctl_regs *const rk3399_ddr_pctl[2] = { 79 (void *)DDRC0_BASE, (void *)DDRC1_BASE 80 }; 81 82 static struct rk3399_ddr_pi_regs *const rk3399_ddr_pi[2] = { 83 (void *)DDRC0_PI_BASE, (void *)DDRC1_PI_BASE 84 }; 85 86 static struct rk3399_ddr_publ_regs *const rk3399_ddr_publ[2] = { 87 (void *)DDRC0_PHY_BASE, (void *)DDRC1_PHY_BASE 88 }; 89 90 struct rk3399_dram_status { 91 uint32_t current_index; 92 uint32_t index_freq[2]; 93 uint32_t low_power_stat; 94 struct timing_related_config timing_config; 95 struct drv_odt_lp_config drv_odt_lp_cfg; 96 }; 97 98 static struct rk3399_dram_status rk3399_dram_status; 99 static struct ddr_dts_config_timing dts_parameter = { 100 .available = 0 101 }; 102 103 static struct rk3399_sdram_default_config ddr3_default_config = { 104 .bl = 8, 105 .ap = 0, 106 .dramds = 40, 107 .dramodt = 120, 108 .burst_ref_cnt = 1, 109 .zqcsi = 0 110 }; 111 112 static struct drv_odt_lp_config ddr3_drv_odt_default_config = { 113 .ddr3_speed_bin = DDR3_DEFAULT, 114 .pd_idle = 0, 115 .sr_idle = 0, 116 .sr_mc_gate_idle = 0, 117 .srpd_lite_idle = 0, 118 .standby_idle = 0, 119 120 .ddr3_dll_dis_freq = 300, 121 .phy_dll_dis_freq = 125, 122 .odt_dis_freq = 933, 123 124 .dram_side_drv = 40, 125 .dram_side_dq_odt = 120, 126 .dram_side_ca_odt = 120, 127 128 .phy_side_ca_drv = 40, 129 .phy_side_ck_cs_drv = 40, 130 .phy_side_dq_drv = 40, 131 .phy_side_odt = 240, 132 }; 133 134 static struct rk3399_sdram_default_config lpddr3_default_config = { 135 .bl = 8, 136 .ap = 0, 137 .dramds = 34, 138 .dramodt = 240, 139 .burst_ref_cnt = 1, 140 .zqcsi = 0 141 }; 142 143 static struct drv_odt_lp_config lpddr3_drv_odt_default_config = { 144 .ddr3_speed_bin = DDR3_DEFAULT, 145 .pd_idle = 0, 146 .sr_idle = 0, 147 .sr_mc_gate_idle = 0, 148 .srpd_lite_idle = 0, 149 .standby_idle = 0, 150 151 .ddr3_dll_dis_freq = 300, 152 .phy_dll_dis_freq = 125, 153 .odt_dis_freq = 666, 154 155 .dram_side_drv = 40, 156 .dram_side_dq_odt = 120, 157 .dram_side_ca_odt = 120, 158 159 .phy_side_ca_drv = 40, 160 .phy_side_ck_cs_drv = 40, 161 .phy_side_dq_drv = 40, 162 .phy_side_odt = 240, 163 }; 164 165 static struct rk3399_sdram_default_config lpddr4_default_config = { 166 .bl = 16, 167 .ap = 0, 168 .dramds = 40, 169 .dramodt = 240, 170 .caodt = 240, 171 .burst_ref_cnt = 1, 172 .zqcsi = 0 173 }; 174 175 static struct drv_odt_lp_config lpddr4_drv_odt_default_config = { 176 .ddr3_speed_bin = DDR3_DEFAULT, 177 .pd_idle = 0, 178 .sr_idle = 0, 179 .sr_mc_gate_idle = 0, 180 .srpd_lite_idle = 0, 181 .standby_idle = 0, 182 183 .ddr3_dll_dis_freq = 300, 184 .phy_dll_dis_freq = 125, 185 .odt_dis_freq = 933, 186 187 .dram_side_drv = 60, 188 .dram_side_dq_odt = 40, 189 .dram_side_ca_odt = 40, 190 191 .phy_side_ca_drv = 40, 192 .phy_side_ck_cs_drv = 80, 193 .phy_side_dq_drv = 80, 194 .phy_side_odt = 60, 195 }; 196 197 uint32_t dcf_code[] = { 198 #include "dcf_code.inc" 199 }; 200 201 202 #define write_32(addr, value)\ 203 mmio_write_32((uintptr_t)(addr), (uint32_t)(value)) 204 205 #define read_32(addr) \ 206 mmio_read_32((uintptr_t)(addr)) 207 #define clrbits_32(addr, clear)\ 208 mmio_clrbits_32((uintptr_t)(addr), (uint32_t)(clear)) 209 #define setbits_32(addr, set)\ 210 mmio_setbits_32((uintptr_t)(addr), (uint32_t)(set)) 211 #define clrsetbits_32(addr, clear, set)\ 212 mmio_clrsetbits_32((uintptr_t)(addr), (uint32_t)(clear),\ 213 (uint32_t)(set)) 214 215 #define DCF_START_ADDR (SRAM_BASE + 0x1400) 216 #define DCF_PARAM_ADDR (SRAM_BASE + 0x1000) 217 218 /* DCF_PAMET */ 219 #define PARAM_DRAM_FREQ (0) 220 #define PARAM_DPLL_CON0 (4) 221 #define PARAM_DPLL_CON1 (8) 222 #define PARAM_DPLL_CON2 (0xc) 223 #define PARAM_DPLL_CON3 (0x10) 224 #define PARAM_DPLL_CON4 (0x14) 225 #define PARAM_DPLL_CON5 (0x18) 226 /* equal to fn<<4 */ 227 #define PARAM_FREQ_SELECT (0x1c) 228 229 static uint32_t get_cs_die_capability(struct rk3399_sdram_params *sdram_config, 230 uint8_t channel, uint8_t cs) 231 { 232 struct rk3399_sdram_channel *ch = &sdram_config->ch[channel]; 233 uint32_t bandwidth; 234 uint32_t die_bandwidth; 235 uint32_t die; 236 uint32_t cs_cap; 237 uint32_t row; 238 239 row = cs == 0 ? ch->cs0_row : ch->cs1_row; 240 bandwidth = 8 * (1 << ch->bw); 241 die_bandwidth = 8 * (1 << ch->dbw); 242 die = bandwidth / die_bandwidth; 243 cs_cap = (1 << (row + ((1 << ch->bk) / 4 + 1) + ch->col + 244 (bandwidth / 16))); 245 if (ch->row_3_4) 246 cs_cap = cs_cap * 3 / 4; 247 248 return (cs_cap / die); 249 } 250 251 static void drv_odt_lp_cfg_init(uint32_t dram_type, 252 struct ddr_dts_config_timing *dts_timing, 253 struct drv_odt_lp_config *drv_config) 254 { 255 if ((dts_timing) && (dts_timing->available)) { 256 drv_config->ddr3_speed_bin = dts_timing->ddr3_speed_bin; 257 drv_config->pd_idle = dts_timing->pd_idle; 258 drv_config->sr_idle = dts_timing->sr_idle; 259 drv_config->sr_mc_gate_idle = dts_timing->sr_mc_gate_idle; 260 drv_config->srpd_lite_idle = dts_timing->srpd_lite_idle; 261 drv_config->standby_idle = dts_timing->standby_idle; 262 drv_config->ddr3_dll_dis_freq = dts_timing->ddr3_dll_dis_freq; 263 drv_config->phy_dll_dis_freq = dts_timing->phy_dll_dis_freq; 264 } 265 266 switch (dram_type) { 267 case DDR3: 268 if ((dts_timing) && (dts_timing->available)) { 269 drv_config->odt_dis_freq = 270 dts_timing->ddr3_odt_dis_freq; 271 drv_config->dram_side_drv = dts_timing->ddr3_drv; 272 drv_config->dram_side_dq_odt = dts_timing->ddr3_odt; 273 drv_config->phy_side_ca_drv = 274 dts_timing->phy_ddr3_ca_drv; 275 drv_config->phy_side_ck_cs_drv = 276 dts_timing->phy_ddr3_ca_drv; 277 drv_config->phy_side_dq_drv = 278 dts_timing->phy_ddr3_dq_drv; 279 drv_config->phy_side_odt = dts_timing->phy_ddr3_odt; 280 } else { 281 memcpy(drv_config, &ddr3_drv_odt_default_config, 282 sizeof(struct drv_odt_lp_config)); 283 } 284 break; 285 case LPDDR3: 286 if ((dts_timing) && (dts_timing->available)) { 287 drv_config->odt_dis_freq = 288 dts_timing->lpddr3_odt_dis_freq; 289 drv_config->dram_side_drv = dts_timing->lpddr3_drv; 290 drv_config->dram_side_dq_odt = dts_timing->lpddr3_odt; 291 drv_config->phy_side_ca_drv = 292 dts_timing->phy_lpddr3_ca_drv; 293 drv_config->phy_side_ck_cs_drv = 294 dts_timing->phy_lpddr3_ca_drv; 295 drv_config->phy_side_dq_drv = 296 dts_timing->phy_lpddr3_dq_drv; 297 drv_config->phy_side_odt = dts_timing->phy_lpddr3_odt; 298 299 } else { 300 memcpy(drv_config, &lpddr3_drv_odt_default_config, 301 sizeof(struct drv_odt_lp_config)); 302 } 303 break; 304 case LPDDR4: 305 default: 306 if ((dts_timing) && (dts_timing->available)) { 307 drv_config->odt_dis_freq = 308 dts_timing->lpddr4_odt_dis_freq; 309 drv_config->dram_side_drv = dts_timing->lpddr4_drv; 310 drv_config->dram_side_dq_odt = 311 dts_timing->lpddr4_dq_odt; 312 drv_config->dram_side_ca_odt = 313 dts_timing->lpddr4_ca_odt; 314 drv_config->phy_side_ca_drv = 315 dts_timing->phy_lpddr4_ca_drv; 316 drv_config->phy_side_ck_cs_drv = 317 dts_timing->phy_lpddr4_ck_cs_drv; 318 drv_config->phy_side_dq_drv = 319 dts_timing->phy_lpddr4_dq_drv; 320 drv_config->phy_side_odt = dts_timing->phy_lpddr4_odt; 321 } else { 322 memcpy(drv_config, &lpddr4_drv_odt_default_config, 323 sizeof(struct drv_odt_lp_config)); 324 } 325 break; 326 } 327 328 switch (drv_config->phy_side_ca_drv) { 329 case 240: 330 drv_config->phy_side_ca_drv = PHY_DRV_ODT_240; 331 break; 332 case 120: 333 drv_config->phy_side_ca_drv = PHY_DRV_ODT_120; 334 break; 335 case 80: 336 drv_config->phy_side_ca_drv = PHY_DRV_ODT_80; 337 break; 338 case 60: 339 drv_config->phy_side_ca_drv = PHY_DRV_ODT_60; 340 break; 341 case 48: 342 drv_config->phy_side_ca_drv = PHY_DRV_ODT_48; 343 break; 344 case 40: 345 drv_config->phy_side_ca_drv = PHY_DRV_ODT_40; 346 break; 347 default: 348 drv_config->phy_side_ca_drv = PHY_DRV_ODT_34_3; 349 break; 350 }; 351 352 switch (drv_config->phy_side_ck_cs_drv) { 353 case 240: 354 drv_config->phy_side_ck_cs_drv = PHY_DRV_ODT_240; 355 break; 356 case 120: 357 drv_config->phy_side_ck_cs_drv = PHY_DRV_ODT_120; 358 break; 359 case 80: 360 drv_config->phy_side_ck_cs_drv = PHY_DRV_ODT_80; 361 break; 362 case 60: 363 drv_config->phy_side_ck_cs_drv = PHY_DRV_ODT_60; 364 break; 365 case 48: 366 drv_config->phy_side_ck_cs_drv = PHY_DRV_ODT_48; 367 break; 368 case 40: 369 drv_config->phy_side_ck_cs_drv = PHY_DRV_ODT_40; 370 break; 371 default: 372 drv_config->phy_side_ck_cs_drv = PHY_DRV_ODT_34_3; 373 break; 374 } 375 376 switch (drv_config->phy_side_dq_drv) { 377 case 240: 378 drv_config->phy_side_dq_drv = PHY_DRV_ODT_240; 379 break; 380 case 120: 381 drv_config->phy_side_dq_drv = PHY_DRV_ODT_120; 382 break; 383 case 80: 384 drv_config->phy_side_dq_drv = PHY_DRV_ODT_80; 385 break; 386 case 60: 387 drv_config->phy_side_dq_drv = PHY_DRV_ODT_60; 388 break; 389 case 48: 390 drv_config->phy_side_dq_drv = PHY_DRV_ODT_48; 391 break; 392 case 40: 393 drv_config->phy_side_dq_drv = PHY_DRV_ODT_40; 394 break; 395 default: 396 drv_config->phy_side_dq_drv = PHY_DRV_ODT_34_3; 397 break; 398 } 399 400 switch (drv_config->phy_side_odt) { 401 case 240: 402 drv_config->phy_side_odt = PHY_DRV_ODT_240; 403 break; 404 case 120: 405 drv_config->phy_side_odt = PHY_DRV_ODT_120; 406 break; 407 case 80: 408 drv_config->phy_side_odt = PHY_DRV_ODT_80; 409 break; 410 case 60: 411 drv_config->phy_side_odt = PHY_DRV_ODT_60; 412 break; 413 case 48: 414 drv_config->phy_side_odt = PHY_DRV_ODT_48; 415 break; 416 case 40: 417 drv_config->phy_side_odt = PHY_DRV_ODT_40; 418 break; 419 default: 420 drv_config->phy_side_odt = PHY_DRV_ODT_34_3; 421 break; 422 } 423 } 424 425 static void sdram_timing_cfg_init(struct timing_related_config *ptiming_config, 426 struct rk3399_sdram_params *sdram_params, 427 struct drv_odt_lp_config *drv_config) 428 { 429 uint32_t i, j; 430 431 for (i = 0; i < sdram_params->num_channels; i++) { 432 ptiming_config->dram_info[i].speed_rate = 433 drv_config->ddr3_speed_bin; 434 ptiming_config->dram_info[i].cs_cnt = sdram_params->ch[i].rank; 435 for (j = 0; j < sdram_params->ch[i].rank; j++) { 436 ptiming_config->dram_info[i].per_die_capability[j] = 437 get_cs_die_capability(sdram_params, i, j); 438 } 439 } 440 ptiming_config->dram_type = sdram_params->dramtype; 441 ptiming_config->ch_cnt = sdram_params->num_channels; 442 switch (sdram_params->dramtype) { 443 case DDR3: 444 ptiming_config->bl = ddr3_default_config.bl; 445 ptiming_config->ap = ddr3_default_config.ap; 446 break; 447 case LPDDR3: 448 ptiming_config->bl = lpddr3_default_config.bl; 449 ptiming_config->ap = lpddr3_default_config.ap; 450 break; 451 case LPDDR4: 452 ptiming_config->bl = lpddr4_default_config.bl; 453 ptiming_config->ap = lpddr4_default_config.ap; 454 ptiming_config->rdbi = 0; 455 ptiming_config->wdbi = 0; 456 break; 457 } 458 ptiming_config->dramds = drv_config->dram_side_drv; 459 ptiming_config->dramodt = drv_config->dram_side_dq_odt; 460 ptiming_config->caodt = drv_config->dram_side_ca_odt; 461 } 462 463 struct lat_adj_pair { 464 uint32_t cl; 465 uint32_t rdlat_adj; 466 uint32_t cwl; 467 uint32_t wrlat_adj; 468 }; 469 470 const struct lat_adj_pair ddr3_lat_adj[] = { 471 {6, 5, 5, 4}, 472 {8, 7, 6, 5}, 473 {10, 9, 7, 6}, 474 {11, 9, 8, 7}, 475 {13, 0xb, 9, 8}, 476 {14, 0xb, 0xa, 9} 477 }; 478 479 const struct lat_adj_pair lpddr3_lat_adj[] = { 480 {3, 2, 1, 0}, 481 {6, 5, 3, 2}, 482 {8, 7, 4, 3}, 483 {9, 8, 5, 4}, 484 {10, 9, 6, 5}, 485 {11, 9, 6, 5}, 486 {12, 0xa, 6, 5}, 487 {14, 0xc, 8, 7}, 488 {16, 0xd, 8, 7} 489 }; 490 491 const struct lat_adj_pair lpddr4_lat_adj[] = { 492 {6, 5, 4, 2}, 493 {10, 9, 6, 4}, 494 {14, 0xc, 8, 6}, 495 {20, 0x11, 0xa, 8}, 496 {24, 0x15, 0xc, 0xa}, 497 {28, 0x18, 0xe, 0xc}, 498 {32, 0x1b, 0x10, 0xe}, 499 {36, 0x1e, 0x12, 0x10} 500 }; 501 502 static uint32_t get_rdlat_adj(uint32_t dram_type, uint32_t cl) 503 { 504 const struct lat_adj_pair *p; 505 uint32_t cnt; 506 uint32_t i; 507 508 if (dram_type == DDR3) { 509 p = ddr3_lat_adj; 510 cnt = ARRAY_SIZE(ddr3_lat_adj); 511 } else if (dram_type == LPDDR3) { 512 p = lpddr3_lat_adj; 513 cnt = ARRAY_SIZE(lpddr3_lat_adj); 514 } else { 515 p = lpddr4_lat_adj; 516 cnt = ARRAY_SIZE(lpddr4_lat_adj); 517 } 518 519 for (i = 0; i < cnt; i++) { 520 if (cl == p[i].cl) 521 return p[i].rdlat_adj; 522 } 523 /* fail */ 524 return 0xff; 525 } 526 527 static uint32_t get_wrlat_adj(uint32_t dram_type, uint32_t cwl) 528 { 529 const struct lat_adj_pair *p; 530 uint32_t cnt; 531 uint32_t i; 532 533 if (dram_type == DDR3) { 534 p = ddr3_lat_adj; 535 cnt = ARRAY_SIZE(ddr3_lat_adj); 536 } else if (dram_type == LPDDR3) { 537 p = lpddr3_lat_adj; 538 cnt = ARRAY_SIZE(lpddr3_lat_adj); 539 } else { 540 p = lpddr4_lat_adj; 541 cnt = ARRAY_SIZE(lpddr4_lat_adj); 542 } 543 544 for (i = 0; i < cnt; i++) { 545 if (cwl == p[i].cwl) 546 return p[i].wrlat_adj; 547 } 548 /* fail */ 549 return 0xff; 550 } 551 552 #define PI_REGS_DIMM_SUPPORT (0) 553 #define PI_ADD_LATENCY (0) 554 #define PI_DOUBLEFREEK (1) 555 556 #define PI_PAD_DELAY_PS_VALUE (1000) 557 #define PI_IE_ENABLE_VALUE (3000) 558 #define PI_TSEL_ENABLE_VALUE (700) 559 560 static uint32_t get_pi_rdlat_adj(struct dram_timing_t *pdram_timing) 561 { 562 /*[DLLSUBTYPE2] == "STD_DENALI_HS" */ 563 uint32_t rdlat, delay_adder, ie_enable, hs_offset, tsel_adder, 564 extra_adder, tsel_enable; 565 566 ie_enable = PI_IE_ENABLE_VALUE; 567 tsel_enable = PI_TSEL_ENABLE_VALUE; 568 569 rdlat = pdram_timing->cl + PI_ADD_LATENCY; 570 delay_adder = ie_enable / (1000000 / pdram_timing->mhz); 571 if ((ie_enable % (1000000 / pdram_timing->mhz)) != 0) 572 delay_adder++; 573 hs_offset = 0; 574 tsel_adder = 0; 575 extra_adder = 0; 576 /* rdlat = rdlat - (PREAMBLE_SUPPORT & 0x1); */ 577 tsel_adder = tsel_enable / (1000000 / pdram_timing->mhz); 578 if ((tsel_enable % (1000000 / pdram_timing->mhz)) != 0) 579 tsel_adder++; 580 delay_adder = delay_adder - 1; 581 if (tsel_adder > delay_adder) 582 extra_adder = tsel_adder - delay_adder; 583 else 584 extra_adder = 0; 585 if (PI_REGS_DIMM_SUPPORT && PI_DOUBLEFREEK) 586 hs_offset = 2; 587 else 588 hs_offset = 1; 589 590 if (delay_adder > (rdlat - 1 - hs_offset)) { 591 rdlat = rdlat - tsel_adder; 592 } else { 593 if ((rdlat - delay_adder) < 2) 594 rdlat = 2; 595 else 596 rdlat = rdlat - delay_adder - extra_adder; 597 } 598 599 return rdlat; 600 } 601 602 static uint32_t get_pi_wrlat(struct dram_timing_t *pdram_timing, 603 struct timing_related_config *timing_config) 604 { 605 uint32_t tmp; 606 607 if (timing_config->dram_type == LPDDR3) { 608 tmp = pdram_timing->cl; 609 if (tmp >= 14) 610 tmp = 8; 611 else if (tmp >= 10) 612 tmp = 6; 613 else if (tmp == 9) 614 tmp = 5; 615 else if (tmp == 8) 616 tmp = 4; 617 else if (tmp == 6) 618 tmp = 3; 619 else 620 tmp = 1; 621 } else { 622 tmp = 1; 623 } 624 625 return tmp; 626 } 627 628 static uint32_t get_pi_wrlat_adj(struct dram_timing_t *pdram_timing, 629 struct timing_related_config *timing_config) 630 { 631 return get_pi_wrlat(pdram_timing, timing_config) + PI_ADD_LATENCY - 1; 632 } 633 634 static uint32_t get_pi_tdfi_phy_rdlat(struct dram_timing_t *pdram_timing, 635 struct timing_related_config *timing_config) 636 { 637 /* [DLLSUBTYPE2] == "STD_DENALI_HS" */ 638 uint32_t cas_lat, delay_adder, ie_enable, hs_offset, ie_delay_adder; 639 uint32_t mem_delay_ps, round_trip_ps; 640 uint32_t phy_internal_delay, lpddr_adder, dfi_adder, rdlat_delay; 641 642 ie_enable = PI_IE_ENABLE_VALUE; 643 644 delay_adder = ie_enable / (1000000 / pdram_timing->mhz); 645 if ((ie_enable % (1000000 / pdram_timing->mhz)) != 0) 646 delay_adder++; 647 delay_adder = delay_adder - 1; 648 if (PI_REGS_DIMM_SUPPORT && PI_DOUBLEFREEK) 649 hs_offset = 2; 650 else 651 hs_offset = 1; 652 653 cas_lat = pdram_timing->cl + PI_ADD_LATENCY; 654 655 if (delay_adder > (cas_lat - 1 - hs_offset)) { 656 ie_delay_adder = 0; 657 } else { 658 ie_delay_adder = ie_enable / (1000000 / pdram_timing->mhz); 659 if ((ie_enable % (1000000 / pdram_timing->mhz)) != 0) 660 ie_delay_adder++; 661 } 662 663 if (timing_config->dram_type == DDR3) { 664 mem_delay_ps = 0; 665 } else if (timing_config->dram_type == LPDDR4) { 666 mem_delay_ps = 3600; 667 } else if (timing_config->dram_type == LPDDR3) { 668 mem_delay_ps = 5500; 669 } else { 670 printf("get_pi_tdfi_phy_rdlat:dramtype unsupport\n"); 671 return 0; 672 } 673 round_trip_ps = 1100 + 500 + mem_delay_ps + 500 + 600; 674 delay_adder = round_trip_ps / (1000000 / pdram_timing->mhz); 675 if ((round_trip_ps % (1000000 / pdram_timing->mhz)) != 0) 676 delay_adder++; 677 678 phy_internal_delay = 5 + 2 + 4; 679 lpddr_adder = mem_delay_ps / (1000000 / pdram_timing->mhz); 680 if ((mem_delay_ps % (1000000 / pdram_timing->mhz)) != 0) 681 lpddr_adder++; 682 dfi_adder = 0; 683 phy_internal_delay = phy_internal_delay + 2; 684 rdlat_delay = delay_adder + phy_internal_delay + 685 ie_delay_adder + lpddr_adder + dfi_adder; 686 687 rdlat_delay = rdlat_delay + 2; 688 return rdlat_delay; 689 } 690 691 static uint32_t get_pi_todtoff_min(struct dram_timing_t *pdram_timing, 692 struct timing_related_config *timing_config) 693 { 694 uint32_t tmp, todtoff_min_ps; 695 696 if (timing_config->dram_type == LPDDR3) 697 todtoff_min_ps = 2500; 698 else if (timing_config->dram_type == LPDDR4) 699 todtoff_min_ps = 1500; 700 else 701 todtoff_min_ps = 0; 702 /* todtoff_min */ 703 tmp = todtoff_min_ps / (1000000 / pdram_timing->mhz); 704 if ((todtoff_min_ps % (1000000 / pdram_timing->mhz)) != 0) 705 tmp++; 706 return tmp; 707 } 708 709 static uint32_t get_pi_todtoff_max(struct dram_timing_t *pdram_timing, 710 struct timing_related_config *timing_config) 711 { 712 uint32_t tmp, todtoff_max_ps; 713 714 if ((timing_config->dram_type == LPDDR4) 715 || (timing_config->dram_type == LPDDR3)) 716 todtoff_max_ps = 3500; 717 else 718 todtoff_max_ps = 0; 719 720 /* todtoff_max */ 721 tmp = todtoff_max_ps / (1000000 / pdram_timing->mhz); 722 if ((todtoff_max_ps % (1000000 / pdram_timing->mhz)) != 0) 723 tmp++; 724 return tmp; 725 } 726 727 static void gen_rk3399_ctl_params_f0(struct timing_related_config 728 *timing_config, 729 struct dram_timing_t *pdram_timing) 730 { 731 uint32_t i; 732 uint32_t tmp, tmp1; 733 734 for (i = 0; i < timing_config->ch_cnt; i++) { 735 if (timing_config->dram_type == DDR3) { 736 tmp = ((700000 + 10) * timing_config->freq + 737 999) / 1000; 738 tmp += pdram_timing->txsnr + (pdram_timing->tmrd * 3) + 739 pdram_timing->tmod + pdram_timing->tzqinit; 740 write_32(&rk3399_ddr_pctl[i]->denali_ctl[5], tmp); 741 742 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[22], 743 0xffff, pdram_timing->tdllk); 744 745 write_32(&rk3399_ddr_pctl[i]->denali_ctl[32], 746 (pdram_timing->tmod << 8) | 747 pdram_timing->tmrd); 748 749 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[59], 750 0xffff << 16, 751 (pdram_timing->txsr - 752 pdram_timing->trcd) << 16); 753 } else if (timing_config->dram_type == LPDDR4) { 754 write_32(&rk3399_ddr_pctl[i]->denali_ctl[5], 755 pdram_timing->tinit1 + pdram_timing->tinit3); 756 write_32(&rk3399_ddr_pctl[i]->denali_ctl[32], 757 (pdram_timing->tmrd << 8) | 758 pdram_timing->tmrd); 759 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[59], 760 0xffff << 16, pdram_timing->txsr << 16); 761 } else { 762 write_32(&rk3399_ddr_pctl[i]->denali_ctl[5], 763 pdram_timing->tinit1); 764 write_32(&rk3399_ddr_pctl[i]->denali_ctl[7], 765 pdram_timing->tinit4); 766 write_32(&rk3399_ddr_pctl[i]->denali_ctl[32], 767 (pdram_timing->tmrd << 8) | 768 pdram_timing->tmrd); 769 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[59], 770 0xffff << 16, pdram_timing->txsr << 16); 771 } 772 write_32(&rk3399_ddr_pctl[i]->denali_ctl[6], 773 pdram_timing->tinit3); 774 write_32(&rk3399_ddr_pctl[i]->denali_ctl[8], 775 pdram_timing->tinit5); 776 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[23], (0x7f << 16), 777 ((pdram_timing->cl * 2) << 16)); 778 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[23], (0x1f << 24), 779 (pdram_timing->cwl << 24)); 780 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[24], 0x3f, 781 pdram_timing->al); 782 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[26], 0xffff << 16, 783 (pdram_timing->trc << 24) | 784 (pdram_timing->trrd << 16)); 785 write_32(&rk3399_ddr_pctl[i]->denali_ctl[27], 786 (pdram_timing->tfaw << 24) | 787 (pdram_timing->trppb << 16) | 788 (pdram_timing->twtr << 8) | pdram_timing->tras_min); 789 790 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[31], 0xff << 24, 791 max(4, pdram_timing->trtp) << 24); 792 write_32(&rk3399_ddr_pctl[i]->denali_ctl[33], 793 (pdram_timing->tcke << 24) | pdram_timing->tras_max); 794 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[34], 0xff, 795 max(1, pdram_timing->tckesr)); 796 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[39], 797 (0x3f << 16) | (0xff << 8), 798 (pdram_timing->twr << 16) | 799 (pdram_timing->trcd << 8)); 800 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[42], 0x1f << 16, 801 pdram_timing->tmrz << 16); 802 tmp = pdram_timing->tdal ? pdram_timing->tdal : 803 (pdram_timing->twr + pdram_timing->trp); 804 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[44], 0xff, tmp); 805 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[45], 0xff, 806 pdram_timing->trp); 807 write_32(&rk3399_ddr_pctl[i]->denali_ctl[48], 808 ((pdram_timing->trefi - 8) << 16) | 809 pdram_timing->trfc); 810 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[52], 0xffff, 811 pdram_timing->txp); 812 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[53], 0xffff << 16, 813 pdram_timing->txpdll << 16); 814 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[55], 0xf << 24, 815 pdram_timing->tcscke << 24); 816 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[55], 0xff, 817 pdram_timing->tmrri); 818 write_32(&rk3399_ddr_pctl[i]->denali_ctl[56], 819 (pdram_timing->tzqcke << 24) | 820 (pdram_timing->tmrwckel << 16) | 821 (pdram_timing->tckehcs << 8) | pdram_timing->tckelcs); 822 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[60], 0xffff, 823 pdram_timing->txsnr); 824 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[62], 0xffff << 16, 825 (pdram_timing->tckehcmd << 24) | 826 (pdram_timing->tckelcmd << 16)); 827 write_32(&rk3399_ddr_pctl[i]->denali_ctl[63], 828 (pdram_timing->tckelpd << 24) | 829 (pdram_timing->tescke << 16) | 830 (pdram_timing->tsr << 8) | pdram_timing->tckckel); 831 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[64], 0xfff, 832 (pdram_timing->tcmdcke << 8) | 833 pdram_timing->tcsckeh); 834 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[92], 835 (0xffff << 8), 836 (pdram_timing->tcksrx << 16) | 837 (pdram_timing->tcksre << 8)); 838 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[108], (0x1 << 24), 839 (timing_config->dllbp << 24)); 840 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[122], 841 (0x3FF << 16), 842 (pdram_timing->tvrcg_enable << 16)); 843 write_32(&rk3399_ddr_pctl[i]->denali_ctl[123], 844 (pdram_timing->tfc_long << 16) | 845 pdram_timing->tvrcg_disable); 846 write_32(&rk3399_ddr_pctl[i]->denali_ctl[124], 847 (pdram_timing->tvref_long << 16) | 848 (pdram_timing->tckfspx << 8) | 849 pdram_timing->tckfspe); 850 write_32(&rk3399_ddr_pctl[i]->denali_ctl[133], 851 (pdram_timing->mr[1] << 16) | pdram_timing->mr[0]); 852 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[134], 0xffff, 853 pdram_timing->mr[2]); 854 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[138], 0xffff, 855 pdram_timing->mr[3]); 856 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[139], 0xff << 24, 857 pdram_timing->mr11 << 24); 858 write_32(&rk3399_ddr_pctl[i]->denali_ctl[147], 859 (pdram_timing->mr[1] << 16) | pdram_timing->mr[0]); 860 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[148], 0xffff, 861 pdram_timing->mr[2]); 862 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[152], 0xffff, 863 pdram_timing->mr[3]); 864 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[153], 0xff << 24, 865 pdram_timing->mr11 << 24); 866 if (timing_config->dram_type == LPDDR4) { 867 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[140], 868 0xffff << 16, pdram_timing->mr12 << 16); 869 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[142], 870 0xffff << 16, pdram_timing->mr14 << 16); 871 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[145], 872 0xffff << 16, pdram_timing->mr22 << 16); 873 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[154], 874 0xffff << 16, pdram_timing->mr12 << 16); 875 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[156], 876 0xffff << 16, pdram_timing->mr14 << 16); 877 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[159], 878 0xffff << 16, pdram_timing->mr22 << 16); 879 } 880 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[179], 0xfff << 8, 881 pdram_timing->tzqinit << 8); 882 write_32(&rk3399_ddr_pctl[i]->denali_ctl[180], 883 (pdram_timing->tzqcs << 16) | 884 (pdram_timing->tzqinit / 2)); 885 write_32(&rk3399_ddr_pctl[i]->denali_ctl[181], 886 (pdram_timing->tzqlat << 16) | pdram_timing->tzqcal); 887 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[212], 0xff << 8, 888 pdram_timing->todton << 8); 889 890 if (timing_config->odt) { 891 setbits_32(&rk3399_ddr_pctl[i]->denali_ctl[213], 892 1 << 16); 893 if (timing_config->freq < 400) 894 tmp = 4 << 24; 895 else 896 tmp = 8 << 24; 897 } else { 898 clrbits_32(&rk3399_ddr_pctl[i]->denali_ctl[213], 899 1 << 16); 900 tmp = 2 << 24; 901 } 902 903 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[216], 904 0x1f << 24, tmp); 905 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[221], 906 (0x3 << 16) | (0xf << 8), 907 (pdram_timing->tdqsck << 16) | 908 (pdram_timing->tdqsck_max << 8)); 909 tmp = 910 (get_wrlat_adj(timing_config->dram_type, pdram_timing->cwl) 911 << 8) | get_rdlat_adj(timing_config->dram_type, 912 pdram_timing->cl); 913 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[284], 0xffff, 914 tmp); 915 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[82], 0xffff << 16, 916 (4 * pdram_timing->trefi) << 16); 917 918 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[83], 0xffff, 919 (2 * pdram_timing->trefi) & 0xffff); 920 921 if ((timing_config->dram_type == LPDDR3) || 922 (timing_config->dram_type == LPDDR4)) { 923 tmp = get_pi_wrlat(pdram_timing, timing_config); 924 tmp1 = get_pi_todtoff_max(pdram_timing, timing_config); 925 tmp = (tmp > tmp1) ? (tmp - tmp1) : 0; 926 } else { 927 tmp = 0; 928 } 929 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[214], 0x3f << 16, 930 (tmp & 0x3f) << 16); 931 932 if ((timing_config->dram_type == LPDDR3) || 933 (timing_config->dram_type == LPDDR4)) { 934 /* min_rl_preamble= cl+TDQSCK_MIN-1 */ 935 tmp = pdram_timing->cl + 936 get_pi_todtoff_min(pdram_timing, timing_config) - 1; 937 /* todtoff_max */ 938 tmp1 = get_pi_todtoff_max(pdram_timing, timing_config); 939 tmp = (tmp > tmp1) ? (tmp - tmp1) : 0; 940 } else { 941 tmp = pdram_timing->cl - pdram_timing->cwl; 942 } 943 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[215], 0x3f << 8, 944 (tmp & 0x3f) << 8); 945 946 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[275], 0xff << 16, 947 (get_pi_tdfi_phy_rdlat 948 (pdram_timing, timing_config) 949 & 0xff) << 16); 950 951 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[277], 0xffff, 952 (2 * pdram_timing->trefi) & 0xffff); 953 954 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[282], 0xffff, 955 (2 * pdram_timing->trefi) & 0xffff); 956 957 write_32(&rk3399_ddr_pctl[i]->denali_ctl[283], 958 20 * pdram_timing->trefi); 959 960 /* CTL_308 TDFI_CALVL_CAPTURE_F0:RW:16:10 */ 961 tmp1 = 20000 / (1000000 / pdram_timing->mhz) + 1; 962 if ((20000 % (1000000 / pdram_timing->mhz)) != 0) 963 tmp1++; 964 tmp = (tmp1 >> 1) + (tmp1 % 2) + 5; 965 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[308], 0x3ff << 16, 966 tmp << 16); 967 968 /* CTL_308 TDFI_CALVL_CC_F0:RW:0:10 */ 969 tmp = tmp + 18; 970 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[308], 0x3ff, 971 tmp); 972 973 /* CTL_314 TDFI_WRCSLAT_F0:RW:8:8 */ 974 tmp1 = get_pi_wrlat_adj(pdram_timing, timing_config); 975 if (timing_config->freq <= ENPER_CS_TRAINING_FREQ) { 976 if (tmp1 < 5) { 977 if (tmp1 == 0) 978 tmp = 0; 979 else 980 tmp = tmp1 - 1; 981 } else { 982 tmp = tmp1 - 5; 983 } 984 } else { 985 tmp = tmp1 - 2; 986 } 987 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[314], 0xff << 8, 988 tmp << 8); 989 990 /* CTL_314 TDFI_RDCSLAT_F0:RW:0:8 */ 991 if ((timing_config->freq <= ENPER_CS_TRAINING_FREQ) && 992 (pdram_timing->cl >= 5)) 993 tmp = pdram_timing->cl - 5; 994 else 995 tmp = pdram_timing->cl - 2; 996 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[314], 0xff, 997 tmp); 998 } 999 } 1000 1001 static void gen_rk3399_ctl_params_f1(struct timing_related_config 1002 *timing_config, 1003 struct dram_timing_t *pdram_timing) 1004 { 1005 uint32_t i; 1006 uint32_t tmp, tmp1; 1007 1008 for (i = 0; i < timing_config->ch_cnt; i++) { 1009 if (timing_config->dram_type == DDR3) { 1010 tmp = 1011 ((700000 + 10) * timing_config->freq + 1012 999) / 1000; 1013 tmp += 1014 pdram_timing->txsnr + (pdram_timing->tmrd * 3) + 1015 pdram_timing->tmod + pdram_timing->tzqinit; 1016 write_32(&rk3399_ddr_pctl[i]->denali_ctl[9], tmp); 1017 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[22], 1018 0xffff << 16, pdram_timing->tdllk << 16); 1019 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[34], 1020 0xffffff00, 1021 (pdram_timing->tmod << 24) | 1022 (pdram_timing->tmrd << 16) | 1023 (pdram_timing->trtp << 8)); 1024 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[60], 1025 0xffff << 16, 1026 (pdram_timing->txsr - 1027 pdram_timing->trcd) << 16); 1028 } else if (timing_config->dram_type == LPDDR4) { 1029 write_32(&rk3399_ddr_pctl[i]->denali_ctl[9], 1030 pdram_timing->tinit1 + pdram_timing->tinit3); 1031 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[34], 1032 0xffffff00, 1033 (pdram_timing->tmrd << 24) | 1034 (pdram_timing->tmrd << 16) | 1035 (pdram_timing->trtp << 8)); 1036 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[60], 1037 0xffff << 16, pdram_timing->txsr << 16); 1038 } else { 1039 write_32(&rk3399_ddr_pctl[i]->denali_ctl[9], 1040 pdram_timing->tinit1); 1041 write_32(&rk3399_ddr_pctl[i]->denali_ctl[11], 1042 pdram_timing->tinit4); 1043 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[34], 1044 0xffffff00, 1045 (pdram_timing->tmrd << 24) | 1046 (pdram_timing->tmrd << 16) | 1047 (pdram_timing->trtp << 8)); 1048 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[60], 1049 0xffff << 16, pdram_timing->txsr << 16); 1050 } 1051 write_32(&rk3399_ddr_pctl[i]->denali_ctl[10], 1052 pdram_timing->tinit3); 1053 write_32(&rk3399_ddr_pctl[i]->denali_ctl[12], 1054 pdram_timing->tinit5); 1055 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[24], (0x7f << 8), 1056 ((pdram_timing->cl * 2) << 8)); 1057 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[24], (0x1f << 16), 1058 (pdram_timing->cwl << 16)); 1059 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[24], 0x3f << 24, 1060 pdram_timing->al << 24); 1061 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[28], 0xffffff00, 1062 (pdram_timing->tras_min << 24) | 1063 (pdram_timing->trc << 16) | 1064 (pdram_timing->trrd << 8)); 1065 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[29], 0xffffff, 1066 (pdram_timing->tfaw << 16) | 1067 (pdram_timing->trppb << 8) | pdram_timing->twtr); 1068 write_32(&rk3399_ddr_pctl[i]->denali_ctl[35], 1069 (pdram_timing->tcke << 24) | pdram_timing->tras_max); 1070 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[36], 0xff, 1071 max(1, pdram_timing->tckesr)); 1072 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[39], 1073 (0xff << 24), (pdram_timing->trcd << 24)); 1074 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[40], 1075 0x3f, pdram_timing->twr); 1076 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[42], 0x1f << 24, 1077 pdram_timing->tmrz << 24); 1078 tmp = pdram_timing->tdal ? pdram_timing->tdal : 1079 (pdram_timing->twr + pdram_timing->trp); 1080 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[44], 0xff << 8, 1081 tmp << 8); 1082 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[45], 0xff << 8, 1083 pdram_timing->trp << 8); 1084 write_32(&rk3399_ddr_pctl[i]->denali_ctl[49], 1085 ((pdram_timing->trefi - 8) << 16) | 1086 pdram_timing->trfc); 1087 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[52], 0xffff << 16, 1088 pdram_timing->txp << 16); 1089 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[54], 0xffff, 1090 pdram_timing->txpdll); 1091 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[55], 0xff << 8, 1092 pdram_timing->tmrri << 8); 1093 write_32(&rk3399_ddr_pctl[i]->denali_ctl[57], 1094 (pdram_timing->tmrwckel << 24) | 1095 (pdram_timing->tckehcs << 16) | 1096 (pdram_timing->tckelcs << 8) | pdram_timing->tcscke); 1097 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[58], 0xf, 1098 pdram_timing->tzqcke); 1099 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[61], 0xffff, 1100 pdram_timing->txsnr); 1101 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[64], 0xffff << 16, 1102 (pdram_timing->tckehcmd << 24) | 1103 (pdram_timing->tckelcmd << 16)); 1104 write_32(&rk3399_ddr_pctl[i]->denali_ctl[65], 1105 (pdram_timing->tckelpd << 24) | 1106 (pdram_timing->tescke << 16) | 1107 (pdram_timing->tsr << 8) | pdram_timing->tckckel); 1108 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[66], 0xfff, 1109 (pdram_timing->tcmdcke << 8) | 1110 pdram_timing->tcsckeh); 1111 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[92], (0xff << 24), 1112 (pdram_timing->tcksre << 24)); 1113 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[93], 0xff, 1114 pdram_timing->tcksrx); 1115 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[108], (0x1 << 25), 1116 (timing_config->dllbp << 25)); 1117 write_32(&rk3399_ddr_pctl[i]->denali_ctl[125], 1118 (pdram_timing->tvrcg_disable << 16) | 1119 pdram_timing->tvrcg_enable); 1120 write_32(&rk3399_ddr_pctl[i]->denali_ctl[126], 1121 (pdram_timing->tckfspx << 24) | 1122 (pdram_timing->tckfspe << 16) | 1123 pdram_timing->tfc_long); 1124 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[127], 0xffff, 1125 pdram_timing->tvref_long); 1126 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[134], 1127 0xffff << 16, pdram_timing->mr[0] << 16); 1128 write_32(&rk3399_ddr_pctl[i]->denali_ctl[135], 1129 (pdram_timing->mr[2] << 16) | pdram_timing->mr[1]); 1130 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[138], 1131 0xffff << 16, pdram_timing->mr[3] << 16); 1132 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[140], 0xff, 1133 pdram_timing->mr11); 1134 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[148], 1135 0xffff << 16, pdram_timing->mr[0] << 16); 1136 write_32(&rk3399_ddr_pctl[i]->denali_ctl[149], 1137 (pdram_timing->mr[2] << 16) | pdram_timing->mr[1]); 1138 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[152], 1139 0xffff << 16, pdram_timing->mr[3] << 16); 1140 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[154], 0xff, 1141 pdram_timing->mr11); 1142 if (timing_config->dram_type == LPDDR4) { 1143 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[141], 1144 0xffff, pdram_timing->mr12); 1145 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[143], 1146 0xffff, pdram_timing->mr14); 1147 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[146], 1148 0xffff, pdram_timing->mr22); 1149 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[155], 1150 0xffff, pdram_timing->mr12); 1151 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[157], 1152 0xffff, pdram_timing->mr14); 1153 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[160], 1154 0xffff, pdram_timing->mr22); 1155 } 1156 write_32(&rk3399_ddr_pctl[i]->denali_ctl[182], 1157 ((pdram_timing->tzqinit / 2) << 16) | 1158 pdram_timing->tzqinit); 1159 write_32(&rk3399_ddr_pctl[i]->denali_ctl[183], 1160 (pdram_timing->tzqcal << 16) | pdram_timing->tzqcs); 1161 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[184], 0x3f, 1162 pdram_timing->tzqlat); 1163 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[188], 0xfff, 1164 pdram_timing->tzqreset); 1165 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[212], 0xff << 16, 1166 pdram_timing->todton << 16); 1167 1168 if (timing_config->odt) { 1169 setbits_32(&rk3399_ddr_pctl[i]->denali_ctl[213], 1170 (1 << 24)); 1171 if (timing_config->freq < 400) 1172 tmp = 4 << 24; 1173 else 1174 tmp = 8 << 24; 1175 } else { 1176 clrbits_32(&rk3399_ddr_pctl[i]->denali_ctl[213], 1177 (1 << 24)); 1178 tmp = 2 << 24; 1179 } 1180 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[217], 0x1f << 24, 1181 tmp); 1182 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[221], 0xf << 24, 1183 (pdram_timing->tdqsck_max << 24)); 1184 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[222], 0x3, 1185 pdram_timing->tdqsck); 1186 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[291], 0xffff, 1187 (get_wrlat_adj(timing_config->dram_type, 1188 pdram_timing->cwl) << 8) | 1189 get_rdlat_adj(timing_config->dram_type, 1190 pdram_timing->cl)); 1191 1192 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[84], 0xffff, 1193 (4 * pdram_timing->trefi) & 0xffff); 1194 1195 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[84], 0xffff << 16, 1196 ((2 * pdram_timing->trefi) & 0xffff) << 16); 1197 1198 if ((timing_config->dram_type == LPDDR3) || 1199 (timing_config->dram_type == LPDDR4)) { 1200 tmp = get_pi_wrlat(pdram_timing, timing_config); 1201 tmp1 = get_pi_todtoff_max(pdram_timing, timing_config); 1202 tmp = (tmp > tmp1) ? (tmp - tmp1) : 0; 1203 } else { 1204 tmp = 0; 1205 } 1206 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[214], 0x3f << 24, 1207 (tmp & 0x3f) << 24); 1208 1209 if ((timing_config->dram_type == LPDDR3) || 1210 (timing_config->dram_type == LPDDR4)) { 1211 /* min_rl_preamble= cl+TDQSCK_MIN-1 */ 1212 tmp = pdram_timing->cl + 1213 get_pi_todtoff_min(pdram_timing, timing_config) - 1; 1214 /* todtoff_max */ 1215 tmp1 = get_pi_todtoff_max(pdram_timing, timing_config); 1216 tmp = (tmp > tmp1) ? (tmp - tmp1) : 0; 1217 } else { 1218 tmp = pdram_timing->cl - pdram_timing->cwl; 1219 } 1220 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[215], 0x3f << 16, 1221 (tmp & 0x3f) << 16); 1222 1223 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[275], 0xff << 24, 1224 (get_pi_tdfi_phy_rdlat 1225 (pdram_timing, timing_config) 1226 & 0xff) << 24); 1227 1228 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[284], 1229 0xffff << 16, 1230 ((2 * pdram_timing->trefi) & 0xffff) << 16); 1231 1232 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[289], 0xffff, 1233 (2 * pdram_timing->trefi) & 0xffff); 1234 1235 write_32(&rk3399_ddr_pctl[i]->denali_ctl[290], 1236 20 * pdram_timing->trefi); 1237 1238 /* CTL_309 TDFI_CALVL_CAPTURE_F1:RW:16:10 */ 1239 tmp1 = 20000 / (1000000 / pdram_timing->mhz) + 1; 1240 if ((20000 % (1000000 / pdram_timing->mhz)) != 0) 1241 tmp1++; 1242 tmp = (tmp1 >> 1) + (tmp1 % 2) + 5; 1243 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[309], 0x3ff << 16, 1244 tmp << 16); 1245 1246 /* CTL_309 TDFI_CALVL_CC_F1:RW:0:10 */ 1247 tmp = tmp + 18; 1248 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[309], 0x3ff, 1249 tmp); 1250 1251 /* CTL_314 TDFI_WRCSLAT_F1:RW:24:8 */ 1252 tmp1 = get_pi_wrlat_adj(pdram_timing, timing_config); 1253 if (timing_config->freq <= ENPER_CS_TRAINING_FREQ) { 1254 if (tmp1 < 5) { 1255 if (tmp1 == 0) 1256 tmp = 0; 1257 else 1258 tmp = tmp1 - 1; 1259 } else { 1260 tmp = tmp1 - 5; 1261 } 1262 } else { 1263 tmp = tmp1 - 2; 1264 } 1265 1266 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[314], 0xff << 24, 1267 tmp << 24); 1268 1269 /* CTL_314 TDFI_RDCSLAT_F1:RW:16:8 */ 1270 if ((timing_config->freq <= ENPER_CS_TRAINING_FREQ) && 1271 (pdram_timing->cl >= 5)) 1272 tmp = pdram_timing->cl - 5; 1273 else 1274 tmp = pdram_timing->cl - 2; 1275 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[314], 0xff << 16, 1276 tmp << 16); 1277 } 1278 } 1279 1280 static void gen_rk3399_ctl_params(struct timing_related_config *timing_config, 1281 struct dram_timing_t *pdram_timing, 1282 uint32_t fn) 1283 { 1284 if (fn == 0) 1285 gen_rk3399_ctl_params_f0(timing_config, pdram_timing); 1286 else 1287 gen_rk3399_ctl_params_f1(timing_config, pdram_timing); 1288 1289 #if CTL_TRAINING 1290 uint32_t i, tmp0, tmp1; 1291 1292 tmp0 = tmp1 = 0; 1293 #if EN_READ_GATE_TRAINING 1294 tmp1 = 1; 1295 #endif 1296 1297 #if EN_CA_TRAINING 1298 tmp0 |= (1 << 8); 1299 #endif 1300 1301 #if EN_WRITE_LEVELING 1302 tmp0 |= (1 << 16); 1303 #endif 1304 1305 #if EN_READ_LEVELING 1306 tmp0 |= (1 << 24); 1307 #endif 1308 for (i = 0; i < timing_config->ch_cnt; i++) { 1309 if (tmp0 | tmp1) 1310 setbits_32(&rk3399_ddr_pctl[i]->denali_ctl[305], 1311 1 << 16); 1312 if (tmp0) 1313 setbits_32(&rk3399_ddr_pctl[i]->denali_ctl[70], tmp0); 1314 if (tmp1) 1315 setbits_32(&rk3399_ddr_pctl[i]->denali_ctl[71], tmp1); 1316 } 1317 #endif 1318 } 1319 1320 static void gen_rk3399_pi_params_f0(struct timing_related_config *timing_config, 1321 struct dram_timing_t *pdram_timing) 1322 { 1323 uint32_t tmp, tmp1, tmp2; 1324 uint32_t i; 1325 1326 for (i = 0; i < timing_config->ch_cnt; i++) { 1327 /* PI_02 PI_TDFI_PHYMSTR_MAX_F0:RW:0:32 */ 1328 tmp = 4 * pdram_timing->trefi; 1329 write_32(&rk3399_ddr_pi[i]->denali_pi[2], tmp); 1330 /* PI_03 PI_TDFI_PHYMSTR_RESP_F0:RW:0:16 */ 1331 tmp = 2 * pdram_timing->trefi; 1332 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[3], 0xffff, tmp); 1333 /* PI_07 PI_TDFI_PHYUPD_RESP_F0:RW:16:16 */ 1334 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[7], 0xffff << 16, 1335 tmp << 16); 1336 1337 /* PI_42 PI_TDELAY_RDWR_2_BUS_IDLE_F0:RW:0:8 */ 1338 if (timing_config->dram_type == LPDDR4) 1339 tmp = 2; 1340 else 1341 tmp = 0; 1342 tmp = (pdram_timing->bl / 2) + 4 + 1343 (get_pi_rdlat_adj(pdram_timing) - 2) + tmp + 1344 get_pi_tdfi_phy_rdlat(pdram_timing, timing_config); 1345 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[42], 0xff, tmp); 1346 /* PI_43 PI_WRLAT_F0:RW:0:5 */ 1347 if (timing_config->dram_type == LPDDR3) { 1348 tmp = get_pi_wrlat(pdram_timing, timing_config); 1349 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[43], 0x1f, 1350 tmp); 1351 } 1352 /* PI_43 PI_ADDITIVE_LAT_F0:RW:8:6 */ 1353 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[43], 0x3f << 8, 1354 PI_ADD_LATENCY << 8); 1355 1356 /* PI_43 PI_CASLAT_LIN_F0:RW:16:7 */ 1357 tmp = pdram_timing->cl * 2; 1358 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[43], 0x7f << 16, 1359 tmp << 16); 1360 /* PI_46 PI_TREF_F0:RW:16:16 */ 1361 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[46], 0xffff << 16, 1362 pdram_timing->trefi << 16); 1363 /* PI_46 PI_TRFC_F0:RW:0:10 */ 1364 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[46], 0x3ff, 1365 pdram_timing->trfc); 1366 /* PI_66 PI_TODTL_2CMD_F0:RW:24:8 */ 1367 if (timing_config->dram_type == LPDDR3) { 1368 tmp = get_pi_todtoff_max(pdram_timing, timing_config); 1369 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[66], 1370 0xff << 24, tmp << 24); 1371 } 1372 /* PI_72 PI_WR_TO_ODTH_F0:RW:16:6 */ 1373 if ((timing_config->dram_type == LPDDR3) || 1374 (timing_config->dram_type == LPDDR4)) { 1375 tmp1 = get_pi_wrlat(pdram_timing, timing_config); 1376 tmp2 = get_pi_todtoff_max(pdram_timing, timing_config); 1377 if (tmp1 > tmp2) 1378 tmp = tmp1 - tmp2; 1379 else 1380 tmp = 0; 1381 } else if (timing_config->dram_type == DDR3) { 1382 tmp = 0; 1383 } 1384 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[72], 0x3f << 16, 1385 tmp << 16); 1386 /* PI_73 PI_RD_TO_ODTH_F0:RW:8:6 */ 1387 if ((timing_config->dram_type == LPDDR3) || 1388 (timing_config->dram_type == LPDDR4)) { 1389 /* min_rl_preamble= cl+TDQSCK_MIN-1 */ 1390 tmp1 = pdram_timing->cl + 1391 get_pi_todtoff_min(pdram_timing, timing_config) - 1; 1392 /* todtoff_max */ 1393 tmp2 = get_pi_todtoff_max(pdram_timing, timing_config); 1394 if (tmp1 > tmp2) 1395 tmp = tmp1 - tmp2; 1396 else 1397 tmp = 0; 1398 } else if (timing_config->dram_type == DDR3) { 1399 tmp = pdram_timing->cl - pdram_timing->cwl; 1400 } 1401 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[73], 0x3f << 8, 1402 tmp << 8); 1403 /* PI_89 PI_RDLAT_ADJ_F0:RW:16:8 */ 1404 tmp = get_pi_rdlat_adj(pdram_timing); 1405 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[89], 0xff << 16, 1406 tmp << 16); 1407 /* PI_90 PI_WRLAT_ADJ_F0:RW:16:8 */ 1408 tmp = get_pi_wrlat_adj(pdram_timing, timing_config); 1409 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[90], 0xff << 16, 1410 tmp << 16); 1411 /* PI_91 PI_TDFI_WRCSLAT_F0:RW:16:8 */ 1412 tmp1 = tmp; 1413 if (tmp1 < 5) { 1414 if (tmp1 == 0) 1415 tmp = 0; 1416 else 1417 tmp = tmp1 - 1; 1418 } else { 1419 tmp = tmp1 - 5; 1420 } 1421 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[91], 0xff << 16, 1422 tmp << 16); 1423 /* PI_95 PI_TDFI_CALVL_CAPTURE_F0:RW:16:10 */ 1424 tmp1 = 20000 / (1000000 / pdram_timing->mhz) + 1; 1425 if ((20000 % (1000000 / pdram_timing->mhz)) != 0) 1426 tmp1++; 1427 tmp = (tmp1 >> 1) + (tmp1 % 2) + 5; 1428 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[95], 0x3ff << 16, 1429 tmp << 16); 1430 /* PI_95 PI_TDFI_CALVL_CC_F0:RW:0:10 */ 1431 tmp = tmp + 18; 1432 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[95], 0x3ff, tmp); 1433 /* PI_102 PI_TMRZ_F0:RW:8:5 */ 1434 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[102], 0x1f << 8, 1435 pdram_timing->tmrz << 8); 1436 /* PI_111 PI_TDFI_CALVL_STROBE_F0:RW:8:4 */ 1437 tmp1 = 2 * 1000 / (1000000 / pdram_timing->mhz); 1438 if ((2 * 1000 % (1000000 / pdram_timing->mhz)) != 0) 1439 tmp1++; 1440 /* pi_tdfi_calvl_strobe=tds_train+5 */ 1441 tmp = tmp1 + 5; 1442 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[111], 0xf << 8, 1443 tmp << 8); 1444 /* PI_116 PI_TCKEHDQS_F0:RW:16:6 */ 1445 tmp = 10000 / (1000000 / pdram_timing->mhz); 1446 if ((10000 % (1000000 / pdram_timing->mhz)) != 0) 1447 tmp++; 1448 if (pdram_timing->mhz <= 100) 1449 tmp = tmp + 1; 1450 else 1451 tmp = tmp + 8; 1452 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[116], 0x3f << 16, 1453 tmp << 16); 1454 /* PI_125 PI_MR1_DATA_F0_0:RW+:8:16 */ 1455 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[125], 0xffff << 8, 1456 pdram_timing->mr[1] << 8); 1457 /* PI_133 PI_MR1_DATA_F0_1:RW+:0:16 */ 1458 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[133], 0xffff, 1459 pdram_timing->mr[1]); 1460 /* PI_140 PI_MR1_DATA_F0_2:RW+:16:16 */ 1461 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[140], 0xffff << 16, 1462 pdram_timing->mr[1] << 16); 1463 /* PI_148 PI_MR1_DATA_F0_3:RW+:0:16 */ 1464 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[148], 0xffff, 1465 pdram_timing->mr[1]); 1466 /* PI_126 PI_MR2_DATA_F0_0:RW+:0:16 */ 1467 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[126], 0xffff, 1468 pdram_timing->mr[2]); 1469 /* PI_133 PI_MR2_DATA_F0_1:RW+:16:16 */ 1470 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[133], 0xffff << 16, 1471 pdram_timing->mr[2] << 16); 1472 /* PI_141 PI_MR2_DATA_F0_2:RW+:0:16 */ 1473 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[141], 0xffff, 1474 pdram_timing->mr[2]); 1475 /* PI_148 PI_MR2_DATA_F0_3:RW+:16:16 */ 1476 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[148], 0xffff << 16, 1477 pdram_timing->mr[2] << 16); 1478 /* PI_156 PI_TFC_F0:RW:0:10 */ 1479 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[156], 0x3ff, 1480 pdram_timing->trfc); 1481 /* PI_158 PI_TWR_F0:RW:24:6 */ 1482 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[158], 0x3f << 24, 1483 pdram_timing->twr << 24); 1484 /* PI_158 PI_TWTR_F0:RW:16:6 */ 1485 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[158], 0x3f << 16, 1486 pdram_timing->twtr << 16); 1487 /* PI_158 PI_TRCD_F0:RW:8:8 */ 1488 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[158], 0xff << 8, 1489 pdram_timing->trcd << 8); 1490 /* PI_158 PI_TRP_F0:RW:0:8 */ 1491 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[158], 0xff, 1492 pdram_timing->trp); 1493 /* PI_157 PI_TRTP_F0:RW:24:8 */ 1494 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[157], 0xff << 24, 1495 pdram_timing->trtp << 24); 1496 /* PI_159 PI_TRAS_MIN_F0:RW:24:8 */ 1497 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[159], 0xff << 24, 1498 pdram_timing->tras_min << 24); 1499 /* PI_159 PI_TRAS_MAX_F0:RW:0:17 */ 1500 tmp = pdram_timing->tras_max * 99 / 100; 1501 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[159], 0x1ffff, tmp); 1502 /* PI_160 PI_TMRD_F0:RW:16:6 */ 1503 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[160], 0x3f << 16, 1504 pdram_timing->tmrd << 16); 1505 /*PI_160 PI_TDQSCK_MAX_F0:RW:0:4 */ 1506 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[160], 0xf, 1507 pdram_timing->tdqsck_max); 1508 /* PI_187 PI_TDFI_CTRLUPD_MAX_F0:RW:8:16 */ 1509 tmp = 2 * pdram_timing->trefi; 1510 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[187], 0xffff << 8, 1511 tmp << 8); 1512 /* PI_188 PI_TDFI_CTRLUPD_INTERVAL_F0:RW:0:32 */ 1513 tmp = 20 * pdram_timing->trefi; 1514 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[188], 0xffffffff, 1515 tmp); 1516 } 1517 } 1518 1519 static void gen_rk3399_pi_params_f1(struct timing_related_config *timing_config, 1520 struct dram_timing_t *pdram_timing) 1521 { 1522 uint32_t tmp, tmp1, tmp2; 1523 uint32_t i; 1524 1525 for (i = 0; i < timing_config->ch_cnt; i++) { 1526 /* PI_04 PI_TDFI_PHYMSTR_MAX_F1:RW:0:32 */ 1527 tmp = 4 * pdram_timing->trefi; 1528 write_32(&rk3399_ddr_pi[i]->denali_pi[4], tmp); 1529 /* PI_05 PI_TDFI_PHYMSTR_RESP_F1:RW:0:16 */ 1530 tmp = 2 * pdram_timing->trefi; 1531 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[5], 0xffff, tmp); 1532 /* PI_12 PI_TDFI_PHYUPD_RESP_F1:RW:0:16 */ 1533 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[12], 0xffff, tmp); 1534 1535 /* PI_42 PI_TDELAY_RDWR_2_BUS_IDLE_F1:RW:8:8 */ 1536 if (timing_config->dram_type == LPDDR4) 1537 tmp = 2; 1538 else 1539 tmp = 0; 1540 tmp = (pdram_timing->bl / 2) + 4 + 1541 (get_pi_rdlat_adj(pdram_timing) - 2) + tmp + 1542 get_pi_tdfi_phy_rdlat(pdram_timing, timing_config); 1543 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[42], 0xff << 8, 1544 tmp << 8); 1545 /* PI_43 PI_WRLAT_F1:RW:24:5 */ 1546 if (timing_config->dram_type == LPDDR3) { 1547 tmp = get_pi_wrlat(pdram_timing, timing_config); 1548 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[43], 1549 0x1f << 24, tmp << 24); 1550 } 1551 /* PI_44 PI_ADDITIVE_LAT_F1:RW:0:6 */ 1552 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[44], 0x3f, 1553 PI_ADD_LATENCY); 1554 /* PI_44 PI_CASLAT_LIN_F1:RW:8:7:=0x18 */ 1555 tmp = pdram_timing->cl * 2; 1556 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[44], 0x7f << 8, 1557 tmp << 8); 1558 /* PI_47 PI_TREF_F1:RW:16:16 */ 1559 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[47], 0xffff << 16, 1560 pdram_timing->trefi << 16); 1561 /* PI_47 PI_TRFC_F1:RW:0:10 */ 1562 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[47], 0x3ff, 1563 pdram_timing->trfc); 1564 /* PI_67 PI_TODTL_2CMD_F1:RW:8:8 */ 1565 if (timing_config->dram_type == LPDDR3) { 1566 tmp = get_pi_todtoff_max(pdram_timing, timing_config); 1567 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[67], 1568 0xff << 8, tmp << 8); 1569 } 1570 /* PI_72 PI_WR_TO_ODTH_F1:RW:24:6 */ 1571 if ((timing_config->dram_type == LPDDR3) 1572 || (timing_config->dram_type == LPDDR4)) { 1573 tmp1 = get_pi_wrlat(pdram_timing, timing_config); 1574 tmp2 = get_pi_todtoff_max(pdram_timing, timing_config); 1575 if (tmp1 > tmp2) 1576 tmp = tmp1 - tmp2; 1577 else 1578 tmp = 0; 1579 } else if (timing_config->dram_type == DDR3) { 1580 tmp = 0; 1581 } 1582 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[72], 0x3f << 24, 1583 tmp << 24); 1584 /* PI_73 PI_RD_TO_ODTH_F1:RW:16:6 */ 1585 if ((timing_config->dram_type == LPDDR3) 1586 || (timing_config->dram_type == LPDDR4)) { 1587 /* min_rl_preamble= cl+TDQSCK_MIN-1 */ 1588 tmp1 = 1589 pdram_timing->cl + get_pi_todtoff_min(pdram_timing, 1590 timing_config) 1591 - 1; 1592 /* todtoff_max */ 1593 tmp2 = get_pi_todtoff_max(pdram_timing, timing_config); 1594 if (tmp1 > tmp2) 1595 tmp = tmp1 - tmp2; 1596 else 1597 tmp = 0; 1598 } else if (timing_config->dram_type == DDR3) { 1599 tmp = pdram_timing->cl - pdram_timing->cwl; 1600 } 1601 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[73], 0x3f << 16, 1602 tmp << 16); 1603 /*P I_89 PI_RDLAT_ADJ_F1:RW:24:8 */ 1604 tmp = get_pi_rdlat_adj(pdram_timing); 1605 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[89], 0xff << 24, 1606 tmp << 24); 1607 /* PI_90 PI_WRLAT_ADJ_F1:RW:24:8 */ 1608 tmp = get_pi_wrlat_adj(pdram_timing, timing_config); 1609 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[90], 0xff << 24, 1610 tmp << 24); 1611 /* PI_91 PI_TDFI_WRCSLAT_F1:RW:24:8 */ 1612 tmp1 = tmp; 1613 if (tmp1 < 5) { 1614 if (tmp1 == 0) 1615 tmp = 0; 1616 else 1617 tmp = tmp1 - 1; 1618 } else { 1619 tmp = tmp1 - 5; 1620 } 1621 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[91], 0xff << 24, 1622 tmp << 24); 1623 /*PI_96 PI_TDFI_CALVL_CAPTURE_F1:RW:16:10 */ 1624 /* tadr=20ns */ 1625 tmp1 = 20000 / (1000000 / pdram_timing->mhz) + 1; 1626 if ((20000 % (1000000 / pdram_timing->mhz)) != 0) 1627 tmp1++; 1628 tmp = (tmp1 >> 1) + (tmp1 % 2) + 5; 1629 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[96], 0x3ff << 16, 1630 tmp << 16); 1631 /* PI_96 PI_TDFI_CALVL_CC_F1:RW:0:10 */ 1632 tmp = tmp + 18; 1633 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[96], 0x3ff, tmp); 1634 /*PI_103 PI_TMRZ_F1:RW:0:5 */ 1635 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[103], 0x1f, 1636 pdram_timing->tmrz); 1637 /*PI_111 PI_TDFI_CALVL_STROBE_F1:RW:16:4 */ 1638 /* tds_train=ceil(2/ns) */ 1639 tmp1 = 2 * 1000 / (1000000 / pdram_timing->mhz); 1640 if ((2 * 1000 % (1000000 / pdram_timing->mhz)) != 0) 1641 tmp1++; 1642 /* pi_tdfi_calvl_strobe=tds_train+5 */ 1643 tmp = tmp1 + 5; 1644 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[111], 0xf << 16, 1645 tmp << 16); 1646 /* PI_116 PI_TCKEHDQS_F1:RW:24:6 */ 1647 tmp = 10000 / (1000000 / pdram_timing->mhz); 1648 if ((10000 % (1000000 / pdram_timing->mhz)) != 0) 1649 tmp++; 1650 if (pdram_timing->mhz <= 100) 1651 tmp = tmp + 1; 1652 else 1653 tmp = tmp + 8; 1654 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[116], 0x3f << 24, 1655 tmp << 24); 1656 /* PI_128 PI_MR1_DATA_F1_0:RW+:0:16 */ 1657 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[128], 0xffff, 1658 pdram_timing->mr[1]); 1659 /* PI_135 PI_MR1_DATA_F1_1:RW+:8:16 */ 1660 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[135], 0xffff << 8, 1661 pdram_timing->mr[1] << 8); 1662 /* PI_143 PI_MR1_DATA_F1_2:RW+:0:16 */ 1663 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[143], 0xffff, 1664 pdram_timing->mr[1]); 1665 /* PI_150 PI_MR1_DATA_F1_3:RW+:8:16 */ 1666 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[150], 0xffff << 8, 1667 pdram_timing->mr[1] << 8); 1668 /* PI_128 PI_MR2_DATA_F1_0:RW+:16:16 */ 1669 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[128], 0xffff << 16, 1670 pdram_timing->mr[2] << 16); 1671 /* PI_136 PI_MR2_DATA_F1_1:RW+:0:16 */ 1672 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[136], 0xffff, 1673 pdram_timing->mr[2]); 1674 /* PI_143 PI_MR2_DATA_F1_2:RW+:16:16 */ 1675 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[143], 0xffff << 16, 1676 pdram_timing->mr[2] << 16); 1677 /* PI_151 PI_MR2_DATA_F1_3:RW+:0:16 */ 1678 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[151], 0xffff, 1679 pdram_timing->mr[2]); 1680 /* PI_156 PI_TFC_F1:RW:16:10 */ 1681 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[156], 0x3ff << 16, 1682 pdram_timing->trfc << 16); 1683 /* PI_162 PI_TWR_F1:RW:8:6 */ 1684 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[162], 0x3f << 8, 1685 pdram_timing->twr << 8); 1686 /* PI_162 PI_TWTR_F1:RW:0:6 */ 1687 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[162], 0x3f, 1688 pdram_timing->twtr); 1689 /* PI_161 PI_TRCD_F1:RW:24:8 */ 1690 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[161], 0xff << 24, 1691 pdram_timing->trcd << 24); 1692 /* PI_161 PI_TRP_F1:RW:16:8 */ 1693 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[161], 0xff << 16, 1694 pdram_timing->trp << 16); 1695 /* PI_161 PI_TRTP_F1:RW:8:8 */ 1696 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[161], 0xff << 8, 1697 pdram_timing->trtp << 8); 1698 /* PI_163 PI_TRAS_MIN_F1:RW:24:8 */ 1699 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[163], 0xff << 24, 1700 pdram_timing->tras_min << 24); 1701 /* PI_163 PI_TRAS_MAX_F1:RW:0:17 */ 1702 tmp = pdram_timing->tras_max * 99 / 100; 1703 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[163], 0x1ffff, tmp); 1704 /* PI_164 PI_TMRD_F1:RW:16:6 */ 1705 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[164], 0x3f << 16, 1706 pdram_timing->tmrd << 16); 1707 /* PI_164 PI_TDQSCK_MAX_F1:RW:0:4 */ 1708 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[164], 0xf, 1709 pdram_timing->tdqsck_max); 1710 /* PI_189 PI_TDFI_CTRLUPD_MAX_F1:RW:0:16 */ 1711 tmp = 2 * pdram_timing->trefi; 1712 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[189], 0xffff, tmp); 1713 /* PI_190 PI_TDFI_CTRLUPD_INTERVAL_F1:RW:0:32 */ 1714 tmp = 20 * pdram_timing->trefi; 1715 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[190], 0xffffffff, 1716 tmp); 1717 } 1718 } 1719 1720 static void gen_rk3399_pi_params(struct timing_related_config *timing_config, 1721 struct dram_timing_t *pdram_timing, 1722 uint32_t fn) 1723 { 1724 if (fn == 0) 1725 gen_rk3399_pi_params_f0(timing_config, pdram_timing); 1726 else 1727 gen_rk3399_pi_params_f1(timing_config, pdram_timing); 1728 1729 #if PI_TRAINING 1730 uint32_t i; 1731 1732 for (i = 0; i < timing_config->ch_cnt; i++) { 1733 #if EN_READ_GATE_TRAINING 1734 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[80], 3 << 24, 1735 2 << 24); 1736 #endif 1737 1738 #if EN_CA_TRAINING 1739 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[100], 3 << 8, 1740 2 << 8); 1741 #endif 1742 1743 #if EN_WRITE_LEVELING 1744 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[60], 3 << 8, 1745 2 << 8); 1746 #endif 1747 1748 #if EN_READ_LEVELING 1749 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[80], 3 << 16, 1750 2 << 16); 1751 #endif 1752 1753 #if EN_WDQ_LEVELING 1754 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[124], 3 << 16, 1755 2 << 16); 1756 #endif 1757 } 1758 #endif 1759 } 1760 1761 static void gen_rk3399_set_odt(uint32_t odt_en) 1762 { 1763 uint32_t drv_odt_val; 1764 uint32_t i; 1765 1766 for (i = 0; i < rk3399_dram_status.timing_config.ch_cnt; i++) { 1767 drv_odt_val = (odt_en | (0 << 1) | (0 << 2)) << 16; 1768 clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[5], 1769 0x7 << 16, drv_odt_val); 1770 clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[133], 1771 0x7 << 16, drv_odt_val); 1772 clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[261], 1773 0x7 << 16, drv_odt_val); 1774 clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[389], 1775 0x7 << 16, drv_odt_val); 1776 drv_odt_val = (odt_en | (0 << 1) | (0 << 2)) << 24; 1777 clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[6], 1778 0x7 << 24, drv_odt_val); 1779 clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[134], 1780 0x7 << 24, drv_odt_val); 1781 clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[262], 1782 0x7 << 24, drv_odt_val); 1783 clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[390], 1784 0x7 << 24, drv_odt_val); 1785 } 1786 } 1787 1788 static void gen_rk3399_set_ds_odt(struct timing_related_config *timing_config, 1789 struct drv_odt_lp_config *drv_config) 1790 { 1791 uint32_t i, drv_odt_val; 1792 1793 for (i = 0; i < timing_config->ch_cnt; i++) { 1794 if (timing_config->dram_type == LPDDR4) 1795 drv_odt_val = drv_config->phy_side_odt | 1796 (PHY_DRV_ODT_Hi_Z << 4) | 1797 (drv_config->phy_side_dq_drv << 8) | 1798 (drv_config->phy_side_dq_drv << 12); 1799 else if (timing_config->dram_type == LPDDR3) 1800 drv_odt_val = PHY_DRV_ODT_Hi_Z | 1801 (drv_config->phy_side_odt << 4) | 1802 (drv_config->phy_side_dq_drv << 8) | 1803 (drv_config->phy_side_dq_drv << 12); 1804 else 1805 drv_odt_val = drv_config->phy_side_odt | 1806 (drv_config->phy_side_odt << 4) | 1807 (drv_config->phy_side_dq_drv << 8) | 1808 (drv_config->phy_side_dq_drv << 12); 1809 1810 /* DQ drv odt set */ 1811 clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[6], 0xffffff, 1812 drv_odt_val); 1813 clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[134], 0xffffff, 1814 drv_odt_val); 1815 clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[262], 0xffffff, 1816 drv_odt_val); 1817 clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[390], 0xffffff, 1818 drv_odt_val); 1819 /* DQS drv odt set */ 1820 clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[7], 0xffffff, 1821 drv_odt_val); 1822 clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[135], 0xffffff, 1823 drv_odt_val); 1824 clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[263], 0xffffff, 1825 drv_odt_val); 1826 clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[391], 0xffffff, 1827 drv_odt_val); 1828 1829 gen_rk3399_set_odt(timing_config->odt); 1830 1831 /* CA drv set */ 1832 drv_odt_val = drv_config->phy_side_ca_drv | 1833 (drv_config->phy_side_ca_drv << 4); 1834 clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[544], 0xff, 1835 drv_odt_val); 1836 clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[672], 0xff, 1837 drv_odt_val); 1838 clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[800], 0xff, 1839 drv_odt_val); 1840 1841 clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[928], 0xff, 1842 drv_odt_val); 1843 clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[937], 0xff, 1844 drv_odt_val); 1845 clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[935], 0xff, 1846 drv_odt_val); 1847 1848 drv_odt_val = drv_config->phy_side_ck_cs_drv | 1849 (drv_config->phy_side_ck_cs_drv << 4); 1850 clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[929], 0xff, 1851 drv_odt_val); 1852 clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[939], 0xff, 1853 drv_odt_val); 1854 } 1855 } 1856 1857 static void gen_rk3399_phy_params(struct timing_related_config *timing_config, 1858 struct drv_odt_lp_config *drv_config, 1859 struct dram_timing_t *pdram_timing, 1860 uint32_t fn) 1861 { 1862 uint32_t tmp, i, div, j; 1863 uint32_t mem_delay_ps, pad_delay_ps, total_delay_ps, delay_frac_ps; 1864 uint32_t trpre_min_ps, gate_delay_ps, gate_delay_frac_ps; 1865 uint32_t ie_enable, tsel_enable, cas_lat, rddata_en_ie_dly, tsel_adder; 1866 uint32_t extra_adder, delta, hs_offset; 1867 1868 for (i = 0; i < timing_config->ch_cnt; i++) { 1869 1870 pad_delay_ps = PI_PAD_DELAY_PS_VALUE; 1871 ie_enable = PI_IE_ENABLE_VALUE; 1872 tsel_enable = PI_TSEL_ENABLE_VALUE; 1873 1874 clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[896], 1875 (0x3 << 8) | 1, fn << 8); 1876 1877 /* PHY_LOW_FREQ_SEL */ 1878 /* DENALI_PHY_913 1bit offset_0 */ 1879 if (timing_config->freq > 400) 1880 clrbits_32(&rk3399_ddr_publ[i]->denali_phy[913], 1); 1881 else 1882 setbits_32(&rk3399_ddr_publ[i]->denali_phy[913], 1); 1883 1884 /* PHY_RPTR_UPDATE_x */ 1885 /* DENALI_PHY_87/215/343/471 4bit offset_16 */ 1886 tmp = 2500 / (1000000 / pdram_timing->mhz) + 3; 1887 if ((2500 % (1000000 / pdram_timing->mhz)) != 0) 1888 tmp++; 1889 clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[87], 0xf << 16, 1890 tmp << 16); 1891 clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[215], 0xf << 16, 1892 tmp << 16); 1893 clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[343], 0xf << 16, 1894 tmp << 16); 1895 clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[471], 0xf << 16, 1896 tmp << 16); 1897 1898 /* PHY_PLL_CTRL */ 1899 /* DENALI_PHY_911 13bits offset_0 */ 1900 /* PHY_LP4_BOOT_PLL_CTRL */ 1901 /* DENALI_PHY_919 13bits offset_0 */ 1902 if (pdram_timing->mhz <= 150) 1903 tmp = 3; 1904 else if (pdram_timing->mhz <= 300) 1905 tmp = 2; 1906 else if (pdram_timing->mhz <= 600) 1907 tmp = 1; 1908 else 1909 tmp = 0; 1910 tmp = (1 << 12) | (tmp << 9) | (2 << 7) | (1 << 1); 1911 clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[911], 0x1fff, 1912 tmp); 1913 clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[919], 0x1fff, 1914 tmp); 1915 1916 /* PHY_PLL_CTRL_CA */ 1917 /* DENALI_PHY_911 13bits offset_16 */ 1918 /* PHY_LP4_BOOT_PLL_CTRL_CA */ 1919 /* DENALI_PHY_919 13bits offset_16 */ 1920 if (pdram_timing->mhz <= 150) 1921 tmp = 3; 1922 else if (pdram_timing->mhz <= 300) 1923 tmp = 2; 1924 else if (pdram_timing->mhz <= 600) 1925 tmp = 1; 1926 else 1927 tmp = 0; 1928 tmp = (tmp << 9) | (2 << 7) | (1 << 5) | (1 << 1); 1929 clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[911], 1930 0x1fff << 16, tmp << 16); 1931 clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[919], 1932 0x1fff << 16, tmp << 16); 1933 1934 /* PHY_TCKSRE_WAIT */ 1935 /* DENALI_PHY_922 4bits offset_24 */ 1936 if (pdram_timing->mhz <= 400) 1937 tmp = 1; 1938 else if (pdram_timing->mhz <= 800) 1939 tmp = 3; 1940 else if (pdram_timing->mhz <= 1000) 1941 tmp = 4; 1942 else 1943 tmp = 5; 1944 clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[922], 0xf << 24, 1945 tmp << 24); 1946 /* PHY_CAL_CLK_SELECT_0:RW8:3 */ 1947 div = pdram_timing->mhz / (2 * 20); 1948 for (j = 2, tmp = 1; j <= 128; j <<= 1, tmp++) { 1949 if (div < j) 1950 break; 1951 } 1952 clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[947], 0x7 << 8, 1953 tmp << 8); 1954 setbits_32(&rk3399_ddr_publ[i]->denali_phy[927], (1 << 22)); 1955 1956 if (timing_config->dram_type == DDR3) { 1957 mem_delay_ps = 0; 1958 trpre_min_ps = 1000; 1959 } else if (timing_config->dram_type == LPDDR4) { 1960 mem_delay_ps = 1500; 1961 trpre_min_ps = 900; 1962 } else if (timing_config->dram_type == LPDDR3) { 1963 mem_delay_ps = 2500; 1964 trpre_min_ps = 900; 1965 } else { 1966 ERROR("gen_rk3399_phy_params:dramtype unsupport\n"); 1967 return; 1968 } 1969 total_delay_ps = mem_delay_ps + pad_delay_ps; 1970 delay_frac_ps = 1971 1000 * total_delay_ps / (1000000 / pdram_timing->mhz); 1972 gate_delay_ps = delay_frac_ps + 1000 - (trpre_min_ps / 2); 1973 gate_delay_frac_ps = 1974 gate_delay_ps - gate_delay_ps / 1000 * 1000; 1975 tmp = gate_delay_frac_ps * 0x200 / 1000; 1976 /* PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY */ 1977 /* DENALI_PHY_2/130/258/386 10bits offset_0 */ 1978 clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[2], 0x2ff, tmp); 1979 clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[130], 0x2ff, tmp); 1980 clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[258], 0x2ff, tmp); 1981 clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[386], 0x2ff, tmp); 1982 /* PHY_RDDQS_GATE_SLAVE_DELAY */ 1983 /* DENALI_PHY_77/205/333/461 10bits offset_16 */ 1984 clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[77], 0x2ff << 16, 1985 tmp << 16); 1986 clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[205], 0x2ff << 16, 1987 tmp << 16); 1988 clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[333], 0x2ff << 16, 1989 tmp << 16); 1990 clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[461], 0x2ff << 16, 1991 tmp << 16); 1992 1993 tmp = gate_delay_ps / 1000; 1994 /* PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST */ 1995 /* DENALI_PHY_10/138/266/394 4bit offset_0 */ 1996 clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[10], 0xf, tmp); 1997 clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[138], 0xf, tmp); 1998 clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[266], 0xf, tmp); 1999 clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[394], 0xf, tmp); 2000 /* PHY_RDDQS_LATENCY_ADJUST */ 2001 /* DENALI_PHY_78/206/334/462 4bits offset_0 */ 2002 clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[78], 0xf, tmp); 2003 clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[206], 0xf, tmp); 2004 clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[334], 0xf, tmp); 2005 clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[462], 0xf, tmp); 2006 /* PHY_GTLVL_LAT_ADJ_START */ 2007 /* DENALI_PHY_80/208/336/464 4bits offset_16 */ 2008 tmp = delay_frac_ps / 1000; 2009 clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[80], 0xf << 16, 2010 tmp << 16); 2011 clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[208], 0xf << 16, 2012 tmp << 16); 2013 clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[336], 0xf << 16, 2014 tmp << 16); 2015 clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[464], 0xf << 16, 2016 tmp << 16); 2017 2018 cas_lat = pdram_timing->cl + PI_ADD_LATENCY; 2019 rddata_en_ie_dly = ie_enable / (1000000 / pdram_timing->mhz); 2020 if ((ie_enable % (1000000 / pdram_timing->mhz)) != 0) 2021 rddata_en_ie_dly++; 2022 rddata_en_ie_dly = rddata_en_ie_dly - 1; 2023 tsel_adder = tsel_enable / (1000000 / pdram_timing->mhz); 2024 if ((tsel_enable % (1000000 / pdram_timing->mhz)) != 0) 2025 tsel_adder++; 2026 if (rddata_en_ie_dly > tsel_adder) 2027 extra_adder = rddata_en_ie_dly - tsel_adder; 2028 else 2029 extra_adder = 0; 2030 delta = cas_lat - rddata_en_ie_dly; 2031 if (PI_REGS_DIMM_SUPPORT && PI_DOUBLEFREEK) 2032 hs_offset = 2; 2033 else 2034 hs_offset = 1; 2035 if (rddata_en_ie_dly > (cas_lat - 1 - hs_offset)) { 2036 tmp = 0; 2037 } else { 2038 if ((delta == 2) || (delta == 1)) 2039 tmp = rddata_en_ie_dly - 0 - extra_adder; 2040 else 2041 tmp = extra_adder; 2042 } 2043 /* PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY */ 2044 /* DENALI_PHY_9/137/265/393 4bit offset_16 */ 2045 clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[9], 0xf << 16, 2046 tmp << 16); 2047 clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[137], 0xf << 16, 2048 tmp << 16); 2049 clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[265], 0xf << 16, 2050 tmp << 16); 2051 clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[393], 0xf << 16, 2052 tmp << 16); 2053 /* PHY_RDDATA_EN_TSEL_DLY */ 2054 /* DENALI_PHY_86/214/342/470 4bit offset_0 */ 2055 clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[86], 0xf, tmp); 2056 clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[214], 0xf, tmp); 2057 clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[342], 0xf, tmp); 2058 clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[470], 0xf, tmp); 2059 2060 if (tsel_adder > rddata_en_ie_dly) 2061 extra_adder = tsel_adder - rddata_en_ie_dly; 2062 else 2063 extra_adder = 0; 2064 if (rddata_en_ie_dly > (cas_lat - 1 - hs_offset)) 2065 tmp = tsel_adder; 2066 else 2067 tmp = rddata_en_ie_dly - 0 + extra_adder; 2068 /* PHY_LP4_BOOT_RDDATA_EN_DLY */ 2069 /* DENALI_PHY_9/137/265/393 4bit offset_8 */ 2070 clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[9], 0xf << 8, 2071 tmp << 8); 2072 clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[137], 0xf << 8, 2073 tmp << 8); 2074 clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[265], 0xf << 8, 2075 tmp << 8); 2076 clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[393], 0xf << 8, 2077 tmp << 8); 2078 /* PHY_RDDATA_EN_DLY */ 2079 /* DENALI_PHY_85/213/341/469 4bit offset_24 */ 2080 clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[85], 0xf << 24, 2081 tmp << 24); 2082 clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[213], 0xf << 24, 2083 tmp << 24); 2084 clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[341], 0xf << 24, 2085 tmp << 24); 2086 clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[469], 0xf << 24, 2087 tmp << 24); 2088 2089 if (pdram_timing->mhz <= ENPER_CS_TRAINING_FREQ) { 2090 2091 /* 2092 * Note:Per-CS Training is not compatible at speeds 2093 * under 533 MHz. If the PHY is running at a speed 2094 * less than 533MHz, all phy_per_cs_training_en_X 2095 * parameters must be cleared to 0. 2096 */ 2097 2098 /*DENALI_PHY_84/212/340/468 1bit offset_16 */ 2099 clrbits_32(&rk3399_ddr_publ[i]->denali_phy[84], 2100 0x1 << 16); 2101 clrbits_32(&rk3399_ddr_publ[i]->denali_phy[212], 2102 0x1 << 16); 2103 clrbits_32(&rk3399_ddr_publ[i]->denali_phy[340], 2104 0x1 << 16); 2105 clrbits_32(&rk3399_ddr_publ[i]->denali_phy[468], 2106 0x1 << 16); 2107 } else { 2108 setbits_32(&rk3399_ddr_publ[i]->denali_phy[84], 2109 0x1 << 16); 2110 setbits_32(&rk3399_ddr_publ[i]->denali_phy[212], 2111 0x1 << 16); 2112 setbits_32(&rk3399_ddr_publ[i]->denali_phy[340], 2113 0x1 << 16); 2114 setbits_32(&rk3399_ddr_publ[i]->denali_phy[468], 2115 0x1 << 16); 2116 } 2117 } 2118 } 2119 2120 static int to_get_clk_index(unsigned int mhz) 2121 { 2122 int pll_cnt, i; 2123 2124 pll_cnt = ARRAY_SIZE(dpll_rates_table); 2125 2126 /* Assumming rate_table is in descending order */ 2127 for (i = 0; i < pll_cnt; i++) { 2128 if (mhz >= dpll_rates_table[i].mhz) 2129 break; 2130 } 2131 2132 /* if mhz lower than lowest frequency in table, use lowest frequency */ 2133 if (i == pll_cnt) 2134 i = pll_cnt - 1; 2135 2136 return i; 2137 } 2138 2139 uint32_t rkclk_prepare_pll_timing(unsigned int mhz) 2140 { 2141 unsigned int refdiv, postdiv1, fbdiv, postdiv2; 2142 int index; 2143 2144 index = to_get_clk_index(mhz); 2145 refdiv = dpll_rates_table[index].refdiv; 2146 fbdiv = dpll_rates_table[index].fbdiv; 2147 postdiv1 = dpll_rates_table[index].postdiv1; 2148 postdiv2 = dpll_rates_table[index].postdiv2; 2149 write_32(DCF_PARAM_ADDR + PARAM_DPLL_CON0, FBDIV(fbdiv)); 2150 write_32(DCF_PARAM_ADDR + PARAM_DPLL_CON1, POSTDIV2(postdiv2) | 2151 POSTDIV1(postdiv1) | REFDIV(refdiv)); 2152 return (24 * fbdiv) / refdiv / postdiv1 / postdiv2; 2153 } 2154 2155 uint32_t ddr_get_rate(void) 2156 { 2157 uint32_t refdiv, postdiv1, fbdiv, postdiv2; 2158 2159 refdiv = mmio_read_32(CRU_BASE + CRU_PLL_CON(DPLL_ID, 1)) & 0x3f; 2160 fbdiv = mmio_read_32(CRU_BASE + CRU_PLL_CON(DPLL_ID, 0)) & 0xfff; 2161 postdiv1 = 2162 (mmio_read_32(CRU_BASE + CRU_PLL_CON(DPLL_ID, 1)) >> 8) & 0x7; 2163 postdiv2 = 2164 (mmio_read_32(CRU_BASE + CRU_PLL_CON(DPLL_ID, 1)) >> 12) & 0x7; 2165 2166 return (24 / refdiv * fbdiv / postdiv1 / postdiv2) * 1000 * 1000; 2167 } 2168 2169 /* 2170 * return: bit12: channel 1, external self-refresh 2171 * bit11: channel 1, stdby_mode 2172 * bit10: channel 1, self-refresh with controller and memory clock gate 2173 * bit9: channel 1, self-refresh 2174 * bit8: channel 1, power-down 2175 * 2176 * bit4: channel 1, external self-refresh 2177 * bit3: channel 0, stdby_mode 2178 * bit2: channel 0, self-refresh with controller and memory clock gate 2179 * bit1: channel 0, self-refresh 2180 * bit0: channel 0, power-down 2181 */ 2182 uint32_t exit_low_power(void) 2183 { 2184 struct rk3399_ddr_pctl_regs *ddr_pctl_regs; 2185 uint32_t low_power = 0; 2186 uint32_t channel_mask; 2187 uint32_t channel; 2188 uint32_t tmp; 2189 2190 channel_mask = (read_32(PMUGRF_BASE + PMUGRF_OSREG(2)) >> 28) & 0x3; 2191 for (channel = 0; channel < 2; channel++) { 2192 ddr_pctl_regs = rk3399_ddr_pctl[channel]; 2193 if (!(channel_mask & (1 << channel))) 2194 continue; 2195 2196 /* exit stdby mode */ 2197 write_32(CIC_BASE + CIC_CTRL1, 2198 (1 << (channel + 16)) | (0 << channel)); 2199 /* exit external self-refresh */ 2200 tmp = channel ? 12 : 8; 2201 low_power |= ((read_32(PMU_BASE + PMU_SFT_CON) >> tmp) & 0x1) 2202 << (4 + 8 * channel); 2203 clrbits_32(PMU_BASE + PMU_SFT_CON, 1 << tmp); 2204 while (!(read_32(PMU_BASE + PMU_DDR_SREF_ST) & 2205 (1 << channel))) 2206 ; 2207 /* exit auto low-power */ 2208 clrbits_32(&ddr_pctl_regs->denali_ctl[101], 0x7); 2209 /* lp_cmd to exit */ 2210 if (((read_32(&ddr_pctl_regs->denali_ctl[100]) >> 24) & 2211 0x7f) != 0x40) { 2212 while (read_32(&ddr_pctl_regs->denali_ctl[200]) & 0x1) 2213 ; 2214 clrsetbits_32(&ddr_pctl_regs->denali_ctl[93], 2215 0xff << 24, 0x69 << 24); 2216 while (((read_32(&ddr_pctl_regs->denali_ctl[100]) >> 2217 24) & 0x7f) != 0x40) 2218 ; 2219 } 2220 } 2221 return low_power; 2222 } 2223 2224 void resume_low_power(uint32_t low_power) 2225 { 2226 struct rk3399_ddr_pctl_regs *ddr_pctl_regs; 2227 uint32_t channel_mask; 2228 uint32_t channel; 2229 uint32_t tmp; 2230 uint32_t val; 2231 2232 channel_mask = (read_32(PMUGRF_BASE + PMUGRF_OSREG(2)) >> 28) & 0x3; 2233 for (channel = 0; channel < 2; channel++) { 2234 ddr_pctl_regs = rk3399_ddr_pctl[channel]; 2235 if (!(channel_mask & (1 << channel))) 2236 continue; 2237 2238 /* resume external self-refresh */ 2239 tmp = channel ? 12 : 8; 2240 val = (low_power >> (4 + 8 * channel)) & 0x1; 2241 setbits_32(PMU_BASE + PMU_SFT_CON, val << tmp); 2242 /* resume auto low-power */ 2243 val = (low_power >> (8 * channel)) & 0x7; 2244 setbits_32(&ddr_pctl_regs->denali_ctl[101], val); 2245 /* resume stdby mode */ 2246 val = (low_power >> (3 + 8 * channel)) & 0x1; 2247 write_32(CIC_BASE + CIC_CTRL1, 2248 (1 << (channel + 16)) | (val << channel)); 2249 } 2250 } 2251 2252 static void wait_dcf_done(void) 2253 { 2254 while ((read_32(DCF_BASE + DCF_DCF_ISR) & (DCF_DONE)) == 0) 2255 continue; 2256 } 2257 2258 void clr_dcf_irq(void) 2259 { 2260 /* clear dcf irq status */ 2261 mmio_write_32(DCF_BASE + DCF_DCF_ISR, DCF_TIMEOUT | DCF_ERR | DCF_DONE); 2262 } 2263 2264 static void enable_dcf(uint32_t dcf_addr) 2265 { 2266 /* config DCF start addr */ 2267 write_32(DCF_BASE + DCF_DCF_ADDR, dcf_addr); 2268 /* wait dcf done */ 2269 while (read_32(DCF_BASE + DCF_DCF_CTRL) & 1) 2270 continue; 2271 /* clear dcf irq status */ 2272 write_32(DCF_BASE + DCF_DCF_ISR, DCF_TIMEOUT | DCF_ERR | DCF_DONE); 2273 /* DCF start */ 2274 setbits_32(DCF_BASE + DCF_DCF_CTRL, DCF_START); 2275 } 2276 2277 void dcf_code_init(void) 2278 { 2279 memcpy((void *)DCF_START_ADDR, (void *)dcf_code, sizeof(dcf_code)); 2280 /* set dcf master secure */ 2281 write_32(SGRF_BASE + 0xe01c, ((0x3 << 0) << 16) | (0 << 0)); 2282 write_32(DCF_BASE + DCF_DCF_TOSET, 0x80000000); 2283 } 2284 2285 static void dcf_start(uint32_t freq, uint32_t index) 2286 { 2287 write_32(CRU_BASE + CRU_SOFTRST_CON(10), (0x1 << (1 + 16)) | (1 << 1)); 2288 write_32(CRU_BASE + CRU_SOFTRST_CON(11), (0x1 << (0 + 16)) | (1 << 0)); 2289 write_32(DCF_PARAM_ADDR + PARAM_FREQ_SELECT, index << 4); 2290 2291 write_32(DCF_PARAM_ADDR + PARAM_DRAM_FREQ, freq); 2292 2293 rkclk_prepare_pll_timing(freq); 2294 udelay(10); 2295 write_32(CRU_BASE + CRU_SOFTRST_CON(10), (0x1 << (1 + 16)) | (0 << 1)); 2296 write_32(CRU_BASE + CRU_SOFTRST_CON(11), (0x1 << (0 + 16)) | (0 << 0)); 2297 udelay(10); 2298 enable_dcf(DCF_START_ADDR); 2299 } 2300 2301 static void dram_low_power_config(struct drv_odt_lp_config *lp_config) 2302 { 2303 uint32_t tmp, tmp1, i; 2304 uint32_t ch_cnt = rk3399_dram_status.timing_config.ch_cnt; 2305 uint32_t dram_type = rk3399_dram_status.timing_config.dram_type; 2306 uint32_t *low_power = &rk3399_dram_status.low_power_stat; 2307 2308 if (dram_type == LPDDR4) 2309 tmp = (lp_config->srpd_lite_idle << 16) | 2310 lp_config->pd_idle; 2311 else 2312 tmp = lp_config->pd_idle; 2313 2314 if (dram_type == DDR3) 2315 tmp1 = (2 << 16) | (0x7 << 8) | 7; 2316 else 2317 tmp1 = (3 << 16) | (0x7 << 8) | 7; 2318 2319 *low_power = 0; 2320 2321 for (i = 0; i < ch_cnt; i++) { 2322 write_32(&rk3399_ddr_pctl[i]->denali_ctl[102], tmp); 2323 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[103], 0xffff, 2324 (lp_config->sr_mc_gate_idle << 8) | 2325 lp_config->sr_idle); 2326 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[101], 2327 0x70f0f, tmp1); 2328 *low_power |= (7 << (8 * i)); 2329 } 2330 2331 /* standby idle */ 2332 write_32(CIC_BASE + CIC_IDLE_TH, lp_config->standby_idle); 2333 write_32(CIC_BASE + CIC_CG_WAIT_TH, 0x640008); 2334 2335 if (ch_cnt == 2) { 2336 write_32(GRF_BASE + GRF_DDRC1_CON1, 2337 (((0x1<<4) | (0x1<<5) | (0x1<<6) | (0x1<<7)) << 16) | 2338 ((0x1<<4) | (0x0<<5) | (0x1<<6) | (0x1<<7))); 2339 if (lp_config->standby_idle) { 2340 tmp = 0x002a002a; 2341 *low_power |= (1 << 11); 2342 } else { 2343 tmp = 0; 2344 } 2345 write_32(CIC_BASE + CIC_CTRL1, tmp); 2346 } 2347 2348 write_32(GRF_BASE + GRF_DDRC0_CON1, 2349 (((0x1<<4) | (0x1<<5) | (0x1<<6) | (0x1<<7)) << 16) | 2350 ((0x1<<4) | (0x0<<5) | (0x1<<6) | (0x1<<7))); 2351 if (lp_config->standby_idle) { 2352 tmp = 0x00150015; 2353 *low_power |= (1 << 3); 2354 } else { 2355 tmp = 0; 2356 } 2357 write_32(CIC_BASE + CIC_CTRL1, tmp); 2358 } 2359 2360 2361 static void dram_related_init(struct ddr_dts_config_timing *dts_timing) 2362 { 2363 uint32_t trefi0, trefi1; 2364 uint32_t i; 2365 2366 dcf_code_init(); 2367 2368 /* get sdram config for os reg */ 2369 drv_odt_lp_cfg_init(sdram_config.dramtype, dts_timing, 2370 &rk3399_dram_status.drv_odt_lp_cfg); 2371 sdram_timing_cfg_init(&rk3399_dram_status.timing_config, 2372 &sdram_config, 2373 &rk3399_dram_status.drv_odt_lp_cfg); 2374 2375 trefi0 = ((read_32(&rk3399_ddr_pctl[0]->denali_ctl[48]) >> 2376 16) & 0xffff) + 8; 2377 trefi1 = ((read_32(&rk3399_ddr_pctl[0]->denali_ctl[49]) >> 2378 16) & 0xffff) + 8; 2379 2380 rk3399_dram_status.index_freq[0] = trefi0 * 10 / 39; 2381 rk3399_dram_status.index_freq[1] = trefi1 * 10 / 39; 2382 rk3399_dram_status.current_index = 2383 (read_32(&rk3399_ddr_pctl[0]->denali_ctl[111]) 2384 >> 16) & 0x3; 2385 if (rk3399_dram_status.timing_config.dram_type == DDR3) { 2386 rk3399_dram_status.index_freq[0] /= 2; 2387 rk3399_dram_status.index_freq[1] /= 2; 2388 } 2389 rk3399_dram_status.index_freq[(rk3399_dram_status.current_index + 1) 2390 & 0x1] = 0; 2391 2392 /* disable all training by ctl and pi */ 2393 for (i = 0; i < rk3399_dram_status.timing_config.ch_cnt; i++) { 2394 clrbits_32(&rk3399_ddr_pctl[i]->denali_ctl[70], (1 << 24) | 2395 (1 << 16) | (1 << 8) | 1); 2396 clrbits_32(&rk3399_ddr_pctl[i]->denali_ctl[71], 1); 2397 2398 clrbits_32(&rk3399_ddr_pi[i]->denali_pi[60], 0x3 << 8); 2399 clrbits_32(&rk3399_ddr_pi[i]->denali_pi[80], (0x3 << 24) | 2400 (0x3 << 16)); 2401 clrbits_32(&rk3399_ddr_pi[i]->denali_pi[100], 0x3 << 8); 2402 clrbits_32(&rk3399_ddr_pi[i]->denali_pi[124], 0x3 << 16); 2403 } 2404 2405 /* init drv odt */ 2406 if (rk3399_dram_status.index_freq[rk3399_dram_status.current_index] < 2407 rk3399_dram_status.drv_odt_lp_cfg.odt_dis_freq) 2408 rk3399_dram_status.timing_config.odt = 0; 2409 else 2410 rk3399_dram_status.timing_config.odt = 1; 2411 gen_rk3399_set_ds_odt(&rk3399_dram_status.timing_config, 2412 &rk3399_dram_status.drv_odt_lp_cfg); 2413 dram_low_power_config(&rk3399_dram_status.drv_odt_lp_cfg); 2414 } 2415 2416 static uint32_t prepare_ddr_timing(uint32_t mhz) 2417 { 2418 uint32_t index; 2419 struct dram_timing_t dram_timing; 2420 2421 rk3399_dram_status.timing_config.freq = mhz; 2422 2423 if (mhz < rk3399_dram_status.drv_odt_lp_cfg.ddr3_dll_dis_freq) 2424 rk3399_dram_status.timing_config.dllbp = 1; 2425 else 2426 rk3399_dram_status.timing_config.dllbp = 0; 2427 if (mhz < rk3399_dram_status.drv_odt_lp_cfg.odt_dis_freq) { 2428 rk3399_dram_status.timing_config.odt = 0; 2429 } else { 2430 rk3399_dram_status.timing_config.odt = 1; 2431 gen_rk3399_set_odt(1); 2432 } 2433 2434 index = (rk3399_dram_status.current_index + 1) & 0x1; 2435 if (rk3399_dram_status.index_freq[index] == mhz) 2436 goto out; 2437 2438 /* 2439 * checking if having available gate traiing timing for 2440 * target freq. 2441 */ 2442 dram_get_parameter(&rk3399_dram_status.timing_config, &dram_timing); 2443 gen_rk3399_ctl_params(&rk3399_dram_status.timing_config, 2444 &dram_timing, index); 2445 gen_rk3399_pi_params(&rk3399_dram_status.timing_config, 2446 &dram_timing, index); 2447 gen_rk3399_phy_params(&rk3399_dram_status.timing_config, 2448 &rk3399_dram_status.drv_odt_lp_cfg, 2449 &dram_timing, index); 2450 rk3399_dram_status.index_freq[index] = mhz; 2451 2452 2453 out: 2454 return index; 2455 } 2456 2457 void print_dram_status_info(void) 2458 { 2459 uint32_t *p; 2460 uint32_t i; 2461 2462 p = (uint32_t *) &rk3399_dram_status.timing_config; 2463 INFO("rk3399_dram_status.timing_config:\n"); 2464 for (i = 0; i < sizeof(struct timing_related_config) / 4; i++) 2465 tf_printf("%u\n", p[i]); 2466 p = (uint32_t *) &rk3399_dram_status.drv_odt_lp_cfg; 2467 INFO("rk3399_dram_status.drv_odt_lp_cfg:\n"); 2468 for (i = 0; i < sizeof(struct drv_odt_lp_config) / 4; i++) 2469 tf_printf("%u\n", p[i]); 2470 } 2471 2472 uint32_t ddr_set_rate(uint32_t hz) 2473 { 2474 uint32_t low_power, index; 2475 uint32_t mhz = hz / (1000 * 1000); 2476 2477 if (mhz == 2478 rk3399_dram_status.index_freq[rk3399_dram_status.current_index]) 2479 goto out; 2480 2481 index = to_get_clk_index(mhz); 2482 mhz = dpll_rates_table[index].mhz; 2483 2484 low_power = exit_low_power(); 2485 index = prepare_ddr_timing(mhz); 2486 if (index > 1) 2487 goto out; 2488 2489 dcf_start(mhz, index); 2490 wait_dcf_done(); 2491 if (rk3399_dram_status.timing_config.odt == 0) 2492 gen_rk3399_set_odt(0); 2493 2494 rk3399_dram_status.current_index = index; 2495 2496 if (mhz < dts_parameter.auto_pd_dis_freq) 2497 low_power |= rk3399_dram_status.low_power_stat; 2498 2499 resume_low_power(low_power); 2500 out: 2501 return mhz; 2502 } 2503 2504 uint32_t ddr_round_rate(uint32_t hz) 2505 { 2506 int index; 2507 uint32_t mhz = hz / (1000 * 1000); 2508 2509 index = to_get_clk_index(mhz); 2510 2511 return dpll_rates_table[index].mhz * 1000 * 1000; 2512 } 2513 2514 uint32_t dts_timing_receive(uint32_t timing, uint32_t index) 2515 { 2516 uint32_t *p = (uint32_t *) &dts_parameter; 2517 static uint32_t receive_nums; 2518 2519 if (index < (sizeof(dts_parameter) / sizeof(uint32_t) - 1)) { 2520 p[index] = (uint32_t)timing; 2521 receive_nums++; 2522 } else { 2523 dts_parameter.available = 0; 2524 return -1; 2525 } 2526 2527 /* receive all parameter */ 2528 if (receive_nums == (sizeof(dts_parameter) / sizeof(uint32_t) - 1)) { 2529 dts_parameter.available = 1; 2530 receive_nums = 0; 2531 } 2532 2533 return index; 2534 } 2535 2536 void ddr_dfs_init(void) 2537 { 2538 dram_related_init(&dts_parameter); 2539 } 2540