1 /* 2 * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <arch_helpers.h> 32 #include <debug.h> 33 #include <delay_timer.h> 34 #include <mmio.h> 35 #include <platform_def.h> 36 #include <plat_private.h> 37 #include <dram.h> 38 #include <rk3399_def.h> 39 #include <rk3399m0.h> 40 #include <soc.h> 41 42 /* Table of regions to map using the MMU. */ 43 const mmap_region_t plat_rk_mmap[] = { 44 MAP_REGION_FLAT(RK3399_DEV_RNG0_BASE, RK3399_DEV_RNG0_SIZE, 45 MT_DEVICE | MT_RW | MT_SECURE), 46 MAP_REGION_FLAT(PMUSRAM_BASE, PMUSRAM_SIZE, 47 MT_MEMORY | MT_RW | MT_SECURE), 48 49 { 0 } 50 }; 51 52 /* The RockChip power domain tree descriptor */ 53 const unsigned char rockchip_power_domain_tree_desc[] = { 54 /* No of root nodes */ 55 PLATFORM_SYSTEM_COUNT, 56 /* No of children for the root node */ 57 PLATFORM_CLUSTER_COUNT, 58 /* No of children for the first cluster node */ 59 PLATFORM_CLUSTER0_CORE_COUNT, 60 /* No of children for the second cluster node */ 61 PLATFORM_CLUSTER1_CORE_COUNT 62 }; 63 64 void secure_timer_init(void) 65 { 66 mmio_write_32(STIMER1_CHN_BASE(5) + TIMER_END_COUNT0, 0xffffffff); 67 mmio_write_32(STIMER1_CHN_BASE(5) + TIMER_END_COUNT1, 0xffffffff); 68 69 mmio_write_32(STIMER1_CHN_BASE(5) + TIMER_INIT_COUNT0, 0x0); 70 mmio_write_32(STIMER1_CHN_BASE(5) + TIMER_INIT_COUNT0, 0x0); 71 72 /* auto reload & enable the timer */ 73 mmio_write_32(STIMER1_CHN_BASE(5) + TIMER_CONTROL_REG, 74 TIMER_EN | TIMER_FMODE); 75 } 76 77 void sgrf_init(void) 78 { 79 /* security config for master */ 80 mmio_write_32(SGRF_BASE + SGRF_SOC_CON3_7(5), 81 SGRF_SOC_CON_WMSK | SGRF_SOC_ALLMST_NS); 82 mmio_write_32(SGRF_BASE + SGRF_SOC_CON3_7(6), 83 SGRF_SOC_CON_WMSK | SGRF_SOC_ALLMST_NS); 84 mmio_write_32(SGRF_BASE + SGRF_SOC_CON3_7(7), 85 SGRF_SOC_CON_WMSK | SGRF_SOC_ALLMST_NS); 86 87 /* security config for slave */ 88 mmio_write_32(SGRF_BASE + SGRF_PMU_SLV_CON0_1(0), 89 SGRF_PMU_SLV_S_CFGED | 90 SGRF_PMU_SLV_CRYPTO1_NS); 91 mmio_write_32(SGRF_BASE + SGRF_PMU_SLV_CON0_1(1), 92 SGRF_PMU_SLV_CON1_CFG); 93 mmio_write_32(SGRF_BASE + SGRF_SLV_SECURE_CON0_4(0), 94 SGRF_SLV_S_WMSK | SGRF_SLV_S_ALL_NS); 95 mmio_write_32(SGRF_BASE + SGRF_SLV_SECURE_CON0_4(1), 96 SGRF_SLV_S_WMSK | SGRF_SLV_S_ALL_NS); 97 mmio_write_32(SGRF_BASE + SGRF_SLV_SECURE_CON0_4(2), 98 SGRF_SLV_S_WMSK | SGRF_SLV_S_ALL_NS); 99 mmio_write_32(SGRF_BASE + SGRF_SLV_SECURE_CON0_4(3), 100 SGRF_SLV_S_WMSK | SGRF_SLV_S_ALL_NS); 101 mmio_write_32(SGRF_BASE + SGRF_SLV_SECURE_CON0_4(4), 102 SGRF_SLV_S_WMSK | SGRF_SLV_S_ALL_NS); 103 104 /* security config for ddr memery */ 105 mmio_write_32(SGRF_BASE + SGRF_DDRRGN_CON0_16(16), 106 SGRF_DDR_RGN_BYPS); 107 } 108 109 static void dma_secure_cfg(uint32_t secure) 110 { 111 if (secure) { 112 /* rgn0 secure for dmac0 and dmac1 */ 113 mmio_write_32(SGRF_BASE + SGRF_DDRRGN_CON20_34(22), 114 SGRF_L_MST_S_DDR_RGN(0) | /* dmac0 */ 115 SGRF_H_MST_S_DDR_RGN(0) /* dmac1 */ 116 ); 117 118 /* set dmac0 boot, under secure state */ 119 mmio_write_32(SGRF_BASE + SGRF_SOC_CON8_15(8), 120 SGRF_DMAC_CFG_S); 121 mmio_write_32(SGRF_BASE + SGRF_SOC_CON8_15(9), 122 SGRF_DMAC_CFG_S); 123 mmio_write_32(SGRF_BASE + SGRF_SOC_CON8_15(10), 124 SGRF_DMAC_CFG_S); 125 126 /* dmac0 soft reset */ 127 mmio_write_32(CRU_BASE + CRU_SOFTRST_CON(10), 128 CRU_DMAC0_RST); 129 udelay(5); 130 mmio_write_32(CRU_BASE + CRU_SOFTRST_CON(10), 131 CRU_DMAC0_RST_RLS); 132 133 /* set dmac1 boot, under secure state */ 134 mmio_write_32(SGRF_BASE + SGRF_SOC_CON8_15(11), 135 SGRF_DMAC_CFG_S); 136 mmio_write_32(SGRF_BASE + SGRF_SOC_CON8_15(12), 137 SGRF_DMAC_CFG_S); 138 mmio_write_32(SGRF_BASE + SGRF_SOC_CON8_15(13), 139 SGRF_DMAC_CFG_S); 140 mmio_write_32(SGRF_BASE + SGRF_SOC_CON8_15(14), 141 SGRF_DMAC_CFG_S); 142 mmio_write_32(SGRF_BASE + SGRF_SOC_CON8_15(15), 143 SGRF_DMAC_CFG_S); 144 145 /* dmac1 soft reset */ 146 mmio_write_32(CRU_BASE + CRU_SOFTRST_CON(10), 147 CRU_DMAC1_RST); 148 udelay(5); 149 mmio_write_32(CRU_BASE + CRU_SOFTRST_CON(10), 150 CRU_DMAC1_RST_RLS); 151 } else { 152 /* rgn non-secure for dmac0 and dmac1 */ 153 mmio_write_32(SGRF_BASE + SGRF_DDRRGN_CON20_34(22), 154 DMAC1_RGN_NS | DMAC0_RGN_NS); 155 156 /* set dmac0 boot, under non-secure state */ 157 mmio_write_32(SGRF_BASE + SGRF_SOC_CON8_15(8), 158 DMAC0_BOOT_CFG_NS); 159 mmio_write_32(SGRF_BASE + SGRF_SOC_CON8_15(9), 160 DMAC0_BOOT_PERIPH_NS); 161 mmio_write_32(SGRF_BASE + SGRF_SOC_CON8_15(10), 162 DMAC0_BOOT_ADDR_NS); 163 164 /* dmac0 soft reset */ 165 mmio_write_32(CRU_BASE + CRU_SOFTRST_CON(10), 166 CRU_DMAC0_RST); 167 udelay(5); 168 mmio_write_32(CRU_BASE + CRU_SOFTRST_CON(10), 169 CRU_DMAC0_RST_RLS); 170 171 /* set dmac1 boot, under non-secure state */ 172 mmio_write_32(SGRF_BASE + SGRF_SOC_CON8_15(11), 173 DMAC1_BOOT_CFG_NS); 174 mmio_write_32(SGRF_BASE + SGRF_SOC_CON8_15(12), 175 DMAC1_BOOT_PERIPH_L_NS); 176 mmio_write_32(SGRF_BASE + SGRF_SOC_CON8_15(13), 177 DMAC1_BOOT_ADDR_NS); 178 mmio_write_32(SGRF_BASE + SGRF_SOC_CON8_15(14), 179 DMAC1_BOOT_PERIPH_H_NS); 180 mmio_write_32(SGRF_BASE + SGRF_SOC_CON8_15(15), 181 DMAC1_BOOT_IRQ_NS); 182 183 /* dmac1 soft reset */ 184 mmio_write_32(CRU_BASE + CRU_SOFTRST_CON(10), 185 CRU_DMAC1_RST); 186 udelay(5); 187 mmio_write_32(CRU_BASE + CRU_SOFTRST_CON(10), 188 CRU_DMAC1_RST_RLS); 189 } 190 } 191 192 /* pll suspend */ 193 struct deepsleep_data_s slp_data; 194 195 void secure_watchdog_disable(void) 196 { 197 slp_data.sgrf_con[3] = mmio_read_32(SGRF_BASE + SGRF_SOC_CON3_7(3)); 198 199 /* disable CA53 wdt pclk */ 200 mmio_write_32(SGRF_BASE + SGRF_SOC_CON3_7(3), 201 BITS_WITH_WMASK(WDT_CA53_DIS, WDT_CA53_1BIT_MASK, 202 PCLK_WDT_CA53_GATE_SHIFT)); 203 /* disable CM0 wdt pclk */ 204 mmio_write_32(SGRF_BASE + SGRF_SOC_CON3_7(3), 205 BITS_WITH_WMASK(WDT_CM0_DIS, WDT_CM0_1BIT_MASK, 206 PCLK_WDT_CM0_GATE_SHIFT)); 207 } 208 209 void secure_watchdog_restore(void) 210 { 211 mmio_write_32(SGRF_BASE + SGRF_SOC_CON3_7(3), 212 slp_data.sgrf_con[3] | 213 WMSK_BIT(PCLK_WDT_CA53_GATE_SHIFT) | 214 WMSK_BIT(PCLK_WDT_CM0_GATE_SHIFT)); 215 } 216 217 static void pll_suspend_prepare(uint32_t pll_id) 218 { 219 int i; 220 221 if (pll_id == PPLL_ID) 222 for (i = 0; i < PLL_CON_COUNT; i++) 223 slp_data.plls_con[pll_id][i] = 224 mmio_read_32(PMUCRU_BASE + PMUCRU_PPLL_CON(i)); 225 else 226 for (i = 0; i < PLL_CON_COUNT; i++) 227 slp_data.plls_con[pll_id][i] = 228 mmio_read_32(CRU_BASE + CRU_PLL_CON(pll_id, i)); 229 } 230 231 static void set_pll_slow_mode(uint32_t pll_id) 232 { 233 if (pll_id == PPLL_ID) 234 mmio_write_32(PMUCRU_BASE + PMUCRU_PPLL_CON(3), PLL_SLOW_MODE); 235 else 236 mmio_write_32((CRU_BASE + 237 CRU_PLL_CON(pll_id, 3)), PLL_SLOW_MODE); 238 } 239 240 static void set_pll_normal_mode(uint32_t pll_id) 241 { 242 if (pll_id == PPLL_ID) 243 mmio_write_32(PMUCRU_BASE + PMUCRU_PPLL_CON(3), PLL_NOMAL_MODE); 244 else 245 mmio_write_32(CRU_BASE + 246 CRU_PLL_CON(pll_id, 3), PLL_NOMAL_MODE); 247 } 248 249 static void set_pll_bypass(uint32_t pll_id) 250 { 251 if (pll_id == PPLL_ID) 252 mmio_write_32(PMUCRU_BASE + 253 PMUCRU_PPLL_CON(3), PLL_BYPASS_MODE); 254 else 255 mmio_write_32(CRU_BASE + 256 CRU_PLL_CON(pll_id, 3), PLL_BYPASS_MODE); 257 } 258 259 static void _pll_suspend(uint32_t pll_id) 260 { 261 set_pll_slow_mode(pll_id); 262 set_pll_bypass(pll_id); 263 } 264 265 /** 266 * disable_dvfs_plls - To suspend the specific PLLs 267 * 268 * When we close the center logic, the DPLL will be closed, 269 * so we need to keep the ABPLL and switch to it to supply 270 * clock for DDR during suspend, then we should not close 271 * the ABPLL and exclude ABPLL_ID. 272 */ 273 void disable_dvfs_plls(void) 274 { 275 _pll_suspend(CPLL_ID); 276 _pll_suspend(NPLL_ID); 277 _pll_suspend(VPLL_ID); 278 _pll_suspend(GPLL_ID); 279 _pll_suspend(ALPLL_ID); 280 } 281 282 /** 283 * disable_nodvfs_plls - To suspend the PPLL 284 */ 285 void disable_nodvfs_plls(void) 286 { 287 _pll_suspend(PPLL_ID); 288 } 289 290 /** 291 * restore_pll - Copy PLL settings from memory to a PLL. 292 * 293 * This will copy PLL settings from an array in memory to the memory mapped 294 * registers for a PLL. 295 * 296 * Note that: above the PLL exclude PPLL. 297 * 298 * pll_id: One of the values from enum plls_id 299 * src: Pointer to the array of values to restore from 300 */ 301 static void restore_pll(int pll_id, uint32_t *src) 302 { 303 /* Nice to have PLL off while configuring */ 304 mmio_write_32((CRU_BASE + CRU_PLL_CON(pll_id, 3)), PLL_SLOW_MODE); 305 306 mmio_write_32(CRU_BASE + CRU_PLL_CON(pll_id, 0), src[0] | REG_SOC_WMSK); 307 mmio_write_32(CRU_BASE + CRU_PLL_CON(pll_id, 1), src[1] | REG_SOC_WMSK); 308 mmio_write_32(CRU_BASE + CRU_PLL_CON(pll_id, 2), src[2]); 309 mmio_write_32(CRU_BASE + CRU_PLL_CON(pll_id, 4), src[4] | REG_SOC_WMSK); 310 mmio_write_32(CRU_BASE + CRU_PLL_CON(pll_id, 5), src[5] | REG_SOC_WMSK); 311 312 /* Do PLL_CON3 since that will enable things */ 313 mmio_write_32(CRU_BASE + CRU_PLL_CON(pll_id, 3), src[3] | REG_SOC_WMSK); 314 315 /* Wait for PLL lock done */ 316 while ((mmio_read_32(CRU_BASE + CRU_PLL_CON(pll_id, 2)) & 317 0x80000000) == 0x0) 318 ; 319 } 320 321 /** 322 * save_pll - Copy PLL settings a PLL to memory 323 * 324 * This will copy PLL settings from the memory mapped registers for a PLL to 325 * an array in memory. 326 * 327 * Note that: above the PLL exclude PPLL. 328 * 329 * pll_id: One of the values from enum plls_id 330 * src: Pointer to the array of values to save to. 331 */ 332 static void save_pll(uint32_t *dst, int pll_id) 333 { 334 int i; 335 336 for (i = 0; i < PLL_CON_COUNT; i++) 337 dst[i] = mmio_read_32(CRU_BASE + CRU_PLL_CON(pll_id, i)); 338 } 339 340 /** 341 * prepare_abpll_for_ddrctrl - Copy DPLL settings to ABPLL 342 * 343 * This will copy DPLL settings from the memory mapped registers for a PLL to 344 * an array in memory. 345 */ 346 void prepare_abpll_for_ddrctrl(void) 347 { 348 save_pll(slp_data.plls_con[ABPLL_ID], ABPLL_ID); 349 save_pll(slp_data.plls_con[DPLL_ID], DPLL_ID); 350 351 restore_pll(ABPLL_ID, slp_data.plls_con[DPLL_ID]); 352 } 353 354 void restore_abpll(void) 355 { 356 restore_pll(ABPLL_ID, slp_data.plls_con[ABPLL_ID]); 357 } 358 359 void restore_dpll(void) 360 { 361 restore_pll(DPLL_ID, slp_data.plls_con[DPLL_ID]); 362 } 363 364 void plls_suspend_prepare(void) 365 { 366 uint32_t i, pll_id; 367 368 for (pll_id = ALPLL_ID; pll_id < END_PLL_ID; pll_id++) 369 pll_suspend_prepare(pll_id); 370 371 for (i = 0; i < CRU_CLKSEL_COUNT; i++) 372 slp_data.cru_clksel_con[i] = 373 mmio_read_32(CRU_BASE + CRU_CLKSEL_CON(i)); 374 375 for (i = 0; i < PMUCRU_CLKSEL_CONUT; i++) 376 slp_data.pmucru_clksel_con[i] = 377 mmio_read_32(PMUCRU_BASE + 378 PMUCRU_CLKSEL_OFFSET + i * REG_SIZE); 379 } 380 381 void clk_gate_con_save(void) 382 { 383 uint32_t i = 0; 384 385 for (i = 0; i < PMUCRU_GATE_COUNT; i++) 386 slp_data.pmucru_gate_con[i] = 387 mmio_read_32(PMUCRU_BASE + PMUCRU_GATE_CON(i)); 388 389 for (i = 0; i < CRU_GATE_COUNT; i++) 390 slp_data.cru_gate_con[i] = 391 mmio_read_32(CRU_BASE + CRU_GATE_CON(i)); 392 } 393 394 void clk_gate_con_disable(void) 395 { 396 uint32_t i; 397 398 for (i = 0; i < PMUCRU_GATE_COUNT; i++) 399 mmio_write_32(PMUCRU_BASE + PMUCRU_GATE_CON(i), REG_SOC_WMSK); 400 401 for (i = 0; i < CRU_GATE_COUNT; i++) 402 mmio_write_32(CRU_BASE + CRU_GATE_CON(i), REG_SOC_WMSK); 403 } 404 405 void clk_gate_con_restore(void) 406 { 407 uint32_t i; 408 409 for (i = 0; i < PMUCRU_GATE_COUNT; i++) 410 mmio_write_32(PMUCRU_BASE + PMUCRU_GATE_CON(i), 411 REG_SOC_WMSK | slp_data.pmucru_gate_con[i]); 412 413 for (i = 0; i < CRU_GATE_COUNT; i++) 414 mmio_write_32(CRU_BASE + CRU_GATE_CON(i), 415 REG_SOC_WMSK | slp_data.cru_gate_con[i]); 416 } 417 418 static void set_plls_nobypass(uint32_t pll_id) 419 { 420 if (pll_id == PPLL_ID) 421 mmio_write_32(PMUCRU_BASE + PMUCRU_PPLL_CON(3), 422 PLL_NO_BYPASS_MODE); 423 else 424 mmio_write_32(CRU_BASE + CRU_PLL_CON(pll_id, 3), 425 PLL_NO_BYPASS_MODE); 426 } 427 428 static void _pll_resume(uint32_t pll_id) 429 { 430 set_plls_nobypass(pll_id); 431 set_pll_normal_mode(pll_id); 432 } 433 434 void plls_resume_finish(void) 435 { 436 int i; 437 438 for (i = 0; i < CRU_CLKSEL_COUNT; i++) { 439 /* CRU_CLKSEL_CON96~107 the high 16-bit isb't write_mask */ 440 if (i > 95) 441 mmio_write_32((CRU_BASE + CRU_CLKSEL_CON(i)), 442 slp_data.cru_clksel_con[i]); 443 else 444 mmio_write_32((CRU_BASE + CRU_CLKSEL_CON(i)), 445 REG_SOC_WMSK | 446 slp_data.cru_clksel_con[i]); 447 } 448 for (i = 0; i < PMUCRU_CLKSEL_CONUT; i++) 449 mmio_write_32((PMUCRU_BASE + 450 PMUCRU_CLKSEL_OFFSET + i * REG_SIZE), 451 REG_SOC_WMSK | slp_data.pmucru_clksel_con[i]); 452 } 453 454 /** 455 * enable_dvfs_plls - To resume the specific PLLs 456 * 457 * Please see the comment at the disable_dvfs_plls() 458 * we don't suspend the ABPLL, so don't need resume 459 * it too. 460 */ 461 void enable_dvfs_plls(void) 462 { 463 _pll_resume(ALPLL_ID); 464 _pll_resume(GPLL_ID); 465 _pll_resume(VPLL_ID); 466 _pll_resume(NPLL_ID); 467 _pll_resume(CPLL_ID); 468 } 469 470 /** 471 * enable_nodvfs_plls - To resume the PPLL 472 */ 473 void enable_nodvfs_plls(void) 474 { 475 _pll_resume(PPLL_ID); 476 } 477 478 void soc_global_soft_reset_init(void) 479 { 480 mmio_write_32(PMUCRU_BASE + CRU_PMU_RSTHOLD_CON(1), 481 CRU_PMU_SGRF_RST_RLS); 482 483 mmio_clrbits_32(CRU_BASE + CRU_GLB_RST_CON, 484 CRU_PMU_WDTRST_MSK | CRU_PMU_FIRST_SFTRST_MSK); 485 } 486 487 void __dead2 soc_global_soft_reset(void) 488 { 489 set_pll_slow_mode(VPLL_ID); 490 set_pll_slow_mode(NPLL_ID); 491 set_pll_slow_mode(GPLL_ID); 492 set_pll_slow_mode(CPLL_ID); 493 set_pll_slow_mode(PPLL_ID); 494 set_pll_slow_mode(ABPLL_ID); 495 set_pll_slow_mode(ALPLL_ID); 496 497 dsb(); 498 499 mmio_write_32(CRU_BASE + CRU_GLB_SRST_FST, GLB_SRST_FST_CFG_VAL); 500 501 /* 502 * Maybe the HW needs some times to reset the system, 503 * so we do not hope the core to excute valid codes. 504 */ 505 while (1) 506 ; 507 } 508 509 static void soc_m0_init(void) 510 { 511 /* secure config for pmu M0 */ 512 mmio_write_32(SGRF_BASE + SGRF_PMU_CON(0), WMSK_BIT(7)); 513 514 /* set the execute address for M0 */ 515 mmio_write_32(SGRF_BASE + SGRF_PMU_CON(3), 516 BITS_WITH_WMASK((M0_BINCODE_BASE >> 12) & 0xffff, 517 0xffff, 0)); 518 mmio_write_32(SGRF_BASE + SGRF_PMU_CON(7), 519 BITS_WITH_WMASK((M0_BINCODE_BASE >> 28) & 0xf, 520 0xf, 0)); 521 } 522 523 void plat_rockchip_soc_init(void) 524 { 525 secure_timer_init(); 526 dma_secure_cfg(0); 527 sgrf_init(); 528 soc_global_soft_reset_init(); 529 plat_rockchip_gpio_init(); 530 soc_m0_init(); 531 dram_init(); 532 } 533