ARM platform changes for new version of image loading

This patch adds changes in ARM platform code to use new
version of image loading.

Following are the major changes:
-Refactor the signatures f

ARM platform changes for new version of image loading

This patch adds changes in ARM platform code to use new
version of image loading.

Following are the major changes:
-Refactor the signatures for bl31_early_platform_setup()
and arm_bl31_early_platform_setup() function to use
`void *` instead of `bl31_params_t *`.
-Introduce `plat_arm_bl2_handle_scp_bl2()` to handle
loading of SCP_BL2 image from BL2.
-Remove usage of reserve_mem() function from
`arm_bl1_early_platform_setup()`
-Extract BL32 & BL33 entrypoint info, from the link list
passed by BL2, in `arm_bl31_early_platform_setup()`
-Provides weak definitions for following platform functions:
plat_get_bl_image_load_info
plat_get_next_bl_params
plat_flush_next_bl_params
bl2_plat_handle_post_image_load
-Instantiates a descriptor array for ARM platforms
describing image and entrypoint information for
`SCP_BL2`, `BL31`, `BL32` and `BL33` images.

All the above changes are conditionally compiled using the
`LOAD_IMAGE_V2` flag.

Change-Id: I5e88b9785a3df1a2b2bbbb37d85b8e353ca61049

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Merge pull request #711 from leon-chen-mtk/mt6795_2

Remove MT6795 plat_sip_svc.c to fix Coverity analysis error.

Merge pull request #702 from jeenu-arm/psci-node-hw-state

Support for PSCI NODE_HW_STATE

Remove MT6795 plat_sip_svc.c to fix Coverity analysis error.

Merge pull request #709 from Xilinx/zynqmp-2016-09

xilinx: ZynqMP updates
- new SIP calls for bitstream programming
- new SIP call to discover the SOC silicon version
- support the delay timer

CSS: Implement support for NODE_HW_STATE

This patch implements CSS platform hook to support NODE_HW_STATE PSCI
API. The platform hook queries SCP to obtain CSS power state. Power
states returned by

CSS: Implement support for NODE_HW_STATE

This patch implements CSS platform hook to support NODE_HW_STATE PSCI
API. The platform hook queries SCP to obtain CSS power state. Power
states returned by SCP are then converted to expected PSCI return codes.

Juno's PSCI operation structure is modified to use the CSS
implementation.

Change-Id: I4a5edac0e5895dd77b51398cbd78f934831dafc0

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SCPI: Add function to query CSS power state

This patch adds the function scpi_get_css_power_state to perform the
'Get CSS Power State' SCP command and handle its response. The function
parses SCP re

SCPI: Add function to query CSS power state

This patch adds the function scpi_get_css_power_state to perform the
'Get CSS Power State' SCP command and handle its response. The function
parses SCP response to obtain power states of requested cluster and CPUs
within.

Change-Id: I3ea26e48dff1a139da73f6c1e0893f21accaf9f0

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FVP: Implement support for NODE_HW_STATE

This patch implements FVP platform hook to support NODE_HW_STATE PSCI
API. The platform hook validates the given MPIDR and reads corresponding
status from FV

FVP: Implement support for NODE_HW_STATE

This patch implements FVP platform hook to support NODE_HW_STATE PSCI
API. The platform hook validates the given MPIDR and reads corresponding
status from FVP power controller, and returns expected values for the
PSCI call.

Change-Id: I286c92637da11858db2c8aba8ba079389032de6d

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Merge pull request #663 from leon-chen-mtk/mt6795_2

mediatek: Support for Mediatek MT6795 SoC

Merge pull request #700 from rockchip-linux/fixes-typo-and-warnings

rockchip: Fixes typo and warnings

zynqmp: Make MMIO write FW call synchronous

We must guarantee that writes have become effective before returning to
the caller. Hence, wait for PMUFW signaling completion of the FW call
before retur

zynqmp: Make MMIO write FW call synchronous

We must guarantee that writes have become effective before returning to
the caller. Hence, wait for PMUFW signaling completion of the FW call
before returning to the rich OS.

Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>

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zynqmp: Add support to provide silicon id through SMC

Add support to provide silicon id to non-secure
software through SMC.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>

[ sb
Move

zynqmp: Add support to provide silicon id through SMC

Add support to provide silicon id to non-secure
software through SMC.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>

[ sb
Move zynqmp_get_silicon_id outside of compile guards to avoid build
errors.
]

Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Acked-by: Michal Simek <michal.simek@xilinx.com>

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zynqmp: pm: Implemented pm API functions to load the bitstream into PL

This patch adds pm_fpga_load() and pm_fpga_get_status() API's to provide
the Access to the xilfpga library to load the bitstrea

zynqmp: pm: Implemented pm API functions to load the bitstream into PL

This patch adds pm_fpga_load() and pm_fpga_get_status() API's to provide
the Access to the xilfpga library to load the bitstream into zynqmp
PL region.

Signed-off-by: Nava kishore Manne <navam@xilinx.com>

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zynqmp: pm: adds new pm ID to sync with PMUFW ID numbers

This patch adds a new pm ID to sync with PMUFW ID numbers.

Signed-off-by: Nava kishore Manne <navam@xilinx.com>

zynqmp: Initialize GIC on suspend_finish

Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>

zynqmp: pm: Call set_wakeup_source for all wake devices on sys-suspend

During system suspend, identify slaves which are configured
as wake sources and call pm_set_wakeup_source API for each of them.

zynqmp: pm: Call set_wakeup_source for all wake devices on sys-suspend

During system suspend, identify slaves which are configured
as wake sources and call pm_set_wakeup_source API for each of them.

Identifying if device may wake the system is done by checking if any
interrupt of that device is enabled in GICD_ISENABLER when the APU is
about to enter SUSPEND_TO_RAM state. If such interrupt is found,
pm_set_wakeup_source is called with corresponding PM node ID as
argument.

Signed-off-by: Filip Drazic <filip.drazic@aggios.com>

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zynqmp: pm: Add PM node IDs for GPU, PCIE, PCAP and RTC

Signed-off-by: Filip Drazic <filip.drazic@aggios.com>

zynqmp: pm: Provide state argument to the pm_self_suspend API call

The state argument of the pm_self_suspend API encodes the state to
which the APU intends to suspend. The state can be:
- PM_APU_STA

zynqmp: pm: Provide state argument to the pm_self_suspend API call

The state argument of the pm_self_suspend API encodes the state to
which the APU intends to suspend. The state can be:
- PM_APU_STATE_CPU_IDLE - processor power down, all memories remain
on
- PM_APU_STATE_SUSPEND_TO_RAM - all processors powered down, L2$
powered down, all OCM banks in retention and DDR in
self-refresh.
The calls for setting requirements for L2$ and OCM banks are now
redundant and removed.

Signed-off-by: Filip Drazic <filip.drazic@aggios.com>
[ sb
- remove redundant #defines
]
Signed-off-by: Sören Brinkmann <soren.brinkmann@xilinx.com>

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zynqmp: Add simple implementation of zynqmp_validate_power_state()

Implementation is based on arm_validate_power_state().
This function is called during CPU_SUSPEND PSCI call to validate
power_state

zynqmp: Add simple implementation of zynqmp_validate_power_state()

Implementation is based on arm_validate_power_state().
This function is called during CPU_SUSPEND PSCI call to validate
power_state parameter. If state is valid this function populate it
in req_state array as power domain level specific local state.
ATF platform migration guide chapter 2.2 defines this function as
mandatory for PSCIv1.0 CPU_SUSPEND support.

Signed-off-by: Stefan Krsmanovic <stefan.krsmanovic@aggios.com>

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zynqmp: Increase MAX_XLAT_TABLES

When moving the ATF into the DRAM address space an additional
translation table is required.

Reported-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Sore

zynqmp: Increase MAX_XLAT_TABLES

When moving the ATF into the DRAM address space an additional
translation table is required.

Reported-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>

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zynqmp: Change default BL31 address space

The OCM space was reorganized to use the space more efficiently. Adjust
the default ATF location to be aligned with other ZynqMP software
components.

Signe

zynqmp: Change default BL31 address space

The OCM space was reorganized to use the space more efficiently. Adjust
the default ATF location to be aligned with other ZynqMP software
components.

Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>

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zynqmp: Add RW access to L2ACTLR_EL1 and CPUACTLR_EL1

Arm provided error injection support. To enable this error injection,
we need to set L2DEIEN in L2ACTLR_EL1 register and L1DEIEN in
CPUACTLR_EL1

zynqmp: Add RW access to L2ACTLR_EL1 and CPUACTLR_EL1

Arm provided error injection support. To enable this error injection,
we need to set L2DEIEN in L2ACTLR_EL1 register and L1DEIEN in
CPUACTLR_EL1 register.

This is needed for our cortexa53 edac linux driver testing.
These registers need write access from non secure EL1 i.e linux
at the time of setting the above bits.

Signed-off-by: Naga Sureshkumar Relli <nagasure@xilinx.com>

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zynqmp: Set RESET_TO_BL31 through platform.mk

ZynqMP only supports builds with RESET_TO_BL31=1. Set this option
through the platform makefile on default.

Signed-off-by: Soren Brinkmann <soren.brink

zynqmp: Set RESET_TO_BL31 through platform.mk

ZynqMP only supports builds with RESET_TO_BL31=1. Set this option
through the platform makefile on default.

Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>

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zynqmp: pm: Added NODE_IPI_RPU_0 node definition in pm_defs

Nodes represent IPI dedicated to the RPU (not accessible by APU)

Signed-off-by: Mirela Simonovic <mirela.simonovic@aggios.com>

zynqmp: Add support for generic_delay_timer

Initialize the generic_delay_timer in the zynqmp port.

Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>