Changes to support execution in AArch32 state for JUNO

Following steps are required to boot JUNO in AArch32 state:
1> BL1, in AArch64 state, loads BL2.
2> BL2, in AArch64 state, initializes DDR.
L

Changes to support execution in AArch32 state for JUNO

Following steps are required to boot JUNO in AArch32 state:
1> BL1, in AArch64 state, loads BL2.
2> BL2, in AArch64 state, initializes DDR.
Loads SP_MIN & BL33 (AArch32 executable)images.
Calls RUN_IMAGE SMC to go back to BL1.
3> BL1 writes AArch32 executable opcodes, to load and branch
at the entrypoint address of SP_MIN, at HI-VECTOR address and
then request for warm reset in AArch32 state using RMR_EL3.

This patch makes following changes to facilitate above steps:
* Added assembly function to carry out step 3 above.
* Added region in TZC that enables Secure access to the
HI-VECTOR(0xFFFF0000) address space.
* AArch32 image descriptor is used, in BL2, to load
SP_MIN and BL33 AArch32 executable images.

A new flag `JUNO_AARCH32_EL3_RUNTIME` is introduced that
controls above changes. By default this flag is disabled.

NOTE: BL1 and BL2 are not supported in AArch32 state for JUNO.

Change-Id: I091d56a0e6d36663e6d9d2bb53c92c672195d1ec
Signed-off-by: Yatharth Kochar <yatharth.kochar@arm.com>
Signed-off-by: dp-arm <dimitris.papastamos@arm.com>

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css: Ensure PSCI system off/reset is not interrupted

If there is a pending interrupt, it is possible for the AP to come out
of the final WFI before SCP has a chance to act on it. Prevent this
by di

css: Ensure PSCI system off/reset is not interrupted

If there is a pending interrupt, it is possible for the AP to come out
of the final WFI before SCP has a chance to act on it. Prevent this
by disabling the GIC CPU interface before issuing a WFI.

Previously, SCP would not wait on WFI before taking an action but
would shut down the core or system regardless.

Change-Id: Ib0bcf69a515d540ed4f73c11e40ec7c863e39c92
Signed-off-by: dp-arm <dimitris.papastamos@arm.com>

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Remove build option `ASM_ASSERTION`

The build option `ENABLE_ASSERTIONS` should be used instead. That way
both C and ASM assertions can be enabled or disabled together.

All occurrences of `ASM_ASSE

Remove build option `ASM_ASSERTION`

The build option `ENABLE_ASSERTIONS` should be used instead. That way
both C and ASM assertions can be enabled or disabled together.

All occurrences of `ASM_ASSERTION` in common code and ARM platforms have
been replaced by `ENABLE_ASSERTIONS`.

ASM_ASSERTION has been removed from the user guide.

Change-Id: I51f1991f11b9b7ff83e787c9a3270c274748ec6f
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

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Tegra: smmu: fix the size used to save context

This patch fixes the size used to save the context, when the
device enters System Suspend.

Reported by: David Cunado

Signed-off-by: Varun Wadekar <vw

Tegra: smmu: fix the size used to save context

This patch fixes the size used to save the context, when the
device enters System Suspend.

Reported by: David Cunado

Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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ARM platforms: Add option to use xlat tables lib v1

ARM platforms have migrated to the translation tables library v2.
However, for testing purposes, it can be useful to temporarily switch
back to th

ARM platforms: Add option to use xlat tables lib v1

ARM platforms have migrated to the translation tables library v2.
However, for testing purposes, it can be useful to temporarily switch
back to the old version.

This patch introduces the option `ARM_XLAT_TABLES_LIB_V1`, that switches
to v1 of the library when is set to 1. By default, it is 0, so that ARM
platforms use the new version unless specifically stated.

Updated User Guide.

Change-Id: I53d3c8dd97706f6af9c6fca0364a88ef341efd31
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

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Tegra186: Support AARCH32/64 encoding for MCE calls

On Tegra systems, there are multiple software components that
require to interact with MCE. The components can either be 32-bit
or 64-bit payloads

Tegra186: Support AARCH32/64 encoding for MCE calls

On Tegra systems, there are multiple software components that
require to interact with MCE. The components can either be 32-bit
or 64-bit payloads. This patch supports MCE SMC functions ID for
AARCH32 and AARCH64 architectures to support such clients.

Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Merge pull request #899 from vwadekar/tegra186-platform-support-v6

Tegra186 platform support v6

Merge pull request #890 from masahir0y/scp

Build: add generic way to include SCP_BL2 into FIP image

Merge pull request #897 from vwadekar/memctrl-v1-xlat-table-v2

Tegra: memctrl_v1: enable 'xlat_table_v2' library

Tegra: fix trivial misra issues

Not having U or ULL as a suffix for these enums causes
a lot of unnecessary MISRA issues. This patch adds U or
ULL suffix to these common enums to reduce number of
MI

Tegra: fix trivial misra issues

Not having U or ULL as a suffix for these enums causes
a lot of unnecessary MISRA issues. This patch adds U or
ULL suffix to these common enums to reduce number of
MISRA issues.

Signed-off-by: Anthony Zhou <anzhou@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra: no need to re-init the same console

This patch stops initialising the same UART console, as a "crash"
console. The normal and the crash consoles use the same UART port
and hence the crash con

Tegra: no need to re-init the same console

This patch stops initialising the same UART console, as a "crash"
console. The normal and the crash consoles use the same UART port
and hence the crash console init function now only checks if the
console is ready to be used.

Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra: Add support for fake system suspend

This patch adds support for fake system suspend (SC7).
This is a debug mode, to ensure that a different code path is
executed for cases like pre-silicon de

Tegra: Add support for fake system suspend

This patch adds support for fake system suspend (SC7).
This is a debug mode, to ensure that a different code path is
executed for cases like pre-silicon development, where a
full-fledged SC7 is not possible in early stages.

This particular patch ensures that, if fake system suspend is
enabled (denoted by tegra_fake_system_suspend variable
having a non-zero value), instead of calling WFI, a request
for a warm reset is made for starting the SC7 exit procedure.

This ensures that the code path of kernel->ATF and back to
kernel is executed without depending on other components
involved in SC7 code path.

Additionally, this patch also adds support for SMC call
from kernel, enabling fake system suspend mode.

Signed-off-by: Vignesh Radhakrishnan <vigneshr@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra: memctrl_v2: restore MC_TXN_OVERRIDE settings

This patch restores the MC_TXN_OVERRIDE settings when we exit from
System Suspend.

Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

Tegra: memctrl_v1: disable AHB redirection after cold boot

During boot, USB3 and flash media (SDMMC/SATA) devices need access to
IRAM. Because these clients connect to the MC and do not have a direc

Tegra: memctrl_v1: disable AHB redirection after cold boot

During boot, USB3 and flash media (SDMMC/SATA) devices need access to
IRAM. Because these clients connect to the MC and do not have a direct
path to the IRAM, the MC implements AHB redirection during boot to allow
path to IRAM. In this mode, accesses to a programmed memory address aperture
are directed to the AHB bus, allowing access to the IRAM. The AHB aperture
is defined by the IRAM_BASE_LO and IRAM_BASE_HI registers, which are
initialized to disable this aperture. Once bootup is complete, we must
program IRAM base/top, thus disabling access to IRAM.

This patch provides functionality to disable this access. The tegra port
calls this new function before jumping to the non-secure world during
cold boot.

Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra: platform: support Tegra186 chip id

This patch adds support to read the chip id and identify if
the current platform is Tegra186.

Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

Tegra: memctrl_v2: MC transaction overrides for newer chips

This patch programs MC transaction overrides settings using
mc_txn_override_cfgs array for all Tegra chips beyond Tegra186
rev. A01

Signe

Tegra: memctrl_v2: MC transaction overrides for newer chips

This patch programs MC transaction overrides settings using
mc_txn_override_cfgs array for all Tegra chips beyond Tegra186
rev. A01

Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra186: mce: Avoid implementation-defined bitfield types

GCC version 4.8 (and presumably earlier) warn when non-standard types are
used for bitfield definitions when -pedantic is enabled. This pre

Tegra186: mce: Avoid implementation-defined bitfield types

GCC version 4.8 (and presumably earlier) warn when non-standard types are
used for bitfield definitions when -pedantic is enabled. This prevents TF
from being built with such toolchains, since -Werror -pedantic options are
used.

gcc-4.9 removed this warning; -pedantic is intended to cause gcc to emit a
warning in all cases required by the standard, but the standard does not
require a warning in this case.

See: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=57773

Signed-off-by: Stephen Warren <swarren@nvidia.com>

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Tegra: smmu: support for multiple devices

This patch adds flexibility to the code to initialise multiple SMMU
devices. The base address macro name has been changed to make it
explicit that we suppor

Tegra: smmu: support for multiple devices

This patch adds flexibility to the code to initialise multiple SMMU
devices. The base address macro name has been changed to make it
explicit that we support multiple SMMUs.

Change-Id: Id4854fb010ebeb699512d79c769de24050c2ad69
Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com>
Signed-off-by: Krishna Reddy <vdumpa@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra: smmu: platform handler for SMMU settings

This patch empowers the platforms to provide an array with the
registers that must be saved/restored across System Suspend.

Original-change-by: Prite

Tegra: smmu: platform handler for SMMU settings

This patch empowers the platforms to provide an array with the
registers that must be saved/restored across System Suspend.

Original-change-by: Pritesh Raithatha <praithatha@nvidia.com>

Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Merge pull request #895 from vwadekar/tegra186-platform-support-v5

Tegra186 platform support v5

Merge pull request #894 from Xilinx/errata-855873

zynqmp: Enable workaround for errata 855873

Merge pull request #885 from antonio-nino-diaz-arm/an/console-flush

Implement console_flush()

Tegra: memctrl_v1: enable 'xlat_table_v2' library

This patch enables the 'xlat_table_v2' library for the Tegra Memory
Controller driver. This library allows us to dynamically map/unmap
memory region

Tegra: memctrl_v1: enable 'xlat_table_v2' library

This patch enables the 'xlat_table_v2' library for the Tegra Memory
Controller driver. This library allows us to dynamically map/unmap
memory regions, with MMU enabled.

The Memory Controller driver maps/unmaps non-overlapping Video Memory
region, to clean it of any secure contents, before it resizes the
region.

Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra: allow platforms to override plat_core_pos_by_mpidr()

This patch makes the default implementation of plat_core_pos_by_mpidr()
as weakly linked, so that platforms can override it with their own

Tegra: allow platforms to override plat_core_pos_by_mpidr()

This patch makes the default implementation of plat_core_pos_by_mpidr()
as weakly linked, so that platforms can override it with their own.

Tegra186, for one, does not have CPU IDs 2 and 3, so it has its own
implementation of plat_core_pos_by_mpidr().

Change-Id: I7a5319869c01ede3775386cb95af1431792f74b3
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra: memctrl_v2: platform handler for MC settings

This patch empowers the platforms to provide the settings (e.g. stream ID,
security setting, transaction overrides) required by the Memory Control

Tegra: memctrl_v2: platform handler for MC settings

This patch empowers the platforms to provide the settings (e.g. stream ID,
security setting, transaction overrides) required by the Memory Controller
driver. This allows the platforms to program the Memory Controller as per
their needs and makes the driver scalable.

Original-change-by: Pritesh Raithatha <praithatha@nvidia.com>

Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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