1 /* 2 * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #ifndef T18X_TEGRA_ARI_H 32 #define T18X_TEGRA_ARI_H 33 34 /* 35 * ---------------------------------------------------------------------------- 36 * t18x_ari.h 37 * 38 * Global ARI definitions. 39 * ---------------------------------------------------------------------------- 40 */ 41 42 enum { 43 TEGRA_ARI_VERSION_MAJOR = 3, 44 TEGRA_ARI_VERSION_MINOR = 1, 45 }; 46 47 typedef enum { 48 /* indexes below get the core lock */ 49 TEGRA_ARI_MISC = 0, 50 /* index 1 is deprecated */ 51 /* index 2 is deprecated */ 52 /* index 3 is deprecated */ 53 TEGRA_ARI_ONLINE_CORE = 4, 54 55 /* indexes below need cluster lock */ 56 TEGRA_ARI_MISC_CLUSTER = 41, 57 TEGRA_ARI_IS_CCX_ALLOWED = 42, 58 TEGRA_ARI_CC3_CTRL = 43, 59 60 /* indexes below need ccplex lock */ 61 TEGRA_ARI_ENTER_CSTATE = 80, 62 TEGRA_ARI_UPDATE_CSTATE_INFO = 81, 63 TEGRA_ARI_IS_SC7_ALLOWED = 82, 64 /* index 83 is deprecated */ 65 TEGRA_ARI_PERFMON = 84, 66 TEGRA_ARI_UPDATE_CCPLEX_GSC = 85, 67 /* index 86 is depracated */ 68 /* index 87 is deprecated */ 69 TEGRA_ARI_ROC_FLUSH_CACHE_ONLY = 88, 70 TEGRA_ARI_ROC_FLUSH_CACHE_TRBITS = 89, 71 TEGRA_ARI_MISC_CCPLEX = 90, 72 TEGRA_ARI_MCA = 91, 73 TEGRA_ARI_UPDATE_CROSSOVER = 92, 74 TEGRA_ARI_CSTATE_STATS = 93, 75 TEGRA_ARI_WRITE_CSTATE_STATS = 94, 76 TEGRA_ARI_COPY_MISCREG_AA64_RST = 95, 77 TEGRA_ARI_ROC_CLEAN_CACHE_ONLY = 96, 78 } tegra_ari_req_id_t; 79 80 typedef enum { 81 TEGRA_ARI_MISC_ECHO = 0, 82 TEGRA_ARI_MISC_VERSION = 1, 83 TEGRA_ARI_MISC_FEATURE_LEAF_0 = 2, 84 } tegra_ari_misc_index_t; 85 86 typedef enum { 87 TEGRA_ARI_MISC_CCPLEX_SHUTDOWN_POWER_OFF = 0, 88 TEGRA_ARI_MISC_CCPLEX_SHUTDOWN_REBOOT = 1, 89 TEGRA_ARI_MISC_CCPLEX_CORESIGHT_CG_CTRL = 2, 90 TEGRA_ARI_MISC_CCPLEX_EDBGREQ = 3, 91 } tegra_ari_misc_ccplex_index_t; 92 93 typedef enum { 94 TEGRA_ARI_CORE_C0 = 0, 95 TEGRA_ARI_CORE_C1 = 1, 96 TEGRA_ARI_CORE_C6 = 6, 97 TEGRA_ARI_CORE_C7 = 7, 98 TEGRA_ARI_CORE_WARMRSTREQ = 8, 99 } tegra_ari_core_sleep_state_t; 100 101 typedef enum { 102 TEGRA_ARI_CLUSTER_CC0 = 0, 103 TEGRA_ARI_CLUSTER_CC1 = 1, 104 TEGRA_ARI_CLUSTER_CC6 = 6, 105 TEGRA_ARI_CLUSTER_CC7 = 7, 106 } tegra_ari_cluster_sleep_state_t; 107 108 typedef enum { 109 TEGRA_ARI_CCPLEX_CCP0 = 0, 110 TEGRA_ARI_CCPLEX_CCP1 = 1, 111 TEGRA_ARI_CCPLEX_CCP3 = 3, /* obsoleted */ 112 } tegra_ari_ccplex_sleep_state_t; 113 114 typedef enum { 115 TEGRA_ARI_SYSTEM_SC0 = 0, 116 TEGRA_ARI_SYSTEM_SC1 = 1, /* obsoleted */ 117 TEGRA_ARI_SYSTEM_SC2 = 2, /* obsoleted */ 118 TEGRA_ARI_SYSTEM_SC3 = 3, /* obsoleted */ 119 TEGRA_ARI_SYSTEM_SC4 = 4, /* obsoleted */ 120 TEGRA_ARI_SYSTEM_SC7 = 7, 121 TEGRA_ARI_SYSTEM_SC8 = 8, 122 } tegra_ari_system_sleep_state_t; 123 124 typedef enum { 125 TEGRA_ARI_CROSSOVER_C1_C6 = 0, 126 TEGRA_ARI_CROSSOVER_CC1_CC6 = 1, 127 TEGRA_ARI_CROSSOVER_CC1_CC7 = 2, 128 TEGRA_ARI_CROSSOVER_CCP1_CCP3 = 3, /* obsoleted */ 129 TEGRA_ARI_CROSSOVER_CCP3_SC2 = 4, /* obsoleted */ 130 TEGRA_ARI_CROSSOVER_CCP3_SC3 = 5, /* obsoleted */ 131 TEGRA_ARI_CROSSOVER_CCP3_SC4 = 6, /* obsoleted */ 132 TEGRA_ARI_CROSSOVER_CCP3_SC7 = 7, /* obsoleted */ 133 TEGRA_ARI_CROSSOVER_SC0_SC7 = 7, 134 TEGRA_ARI_CROSSOVER_CCP3_SC1 = 8, /* obsoleted */ 135 } tegra_ari_crossover_index_t; 136 137 typedef enum { 138 TEGRA_ARI_CSTATE_STATS_CLEAR = 0, 139 TEGRA_ARI_CSTATE_STATS_SC7_ENTRIES, 140 TEGRA_ARI_CSTATE_STATS_SC4_ENTRIES, /* obsoleted */ 141 TEGRA_ARI_CSTATE_STATS_SC3_ENTRIES, /* obsoleted */ 142 TEGRA_ARI_CSTATE_STATS_SC2_ENTRIES, /* obsoleted */ 143 TEGRA_ARI_CSTATE_STATS_CCP3_ENTRIES, /* obsoleted */ 144 TEGRA_ARI_CSTATE_STATS_A57_CC6_ENTRIES, 145 TEGRA_ARI_CSTATE_STATS_A57_CC7_ENTRIES, 146 TEGRA_ARI_CSTATE_STATS_D15_CC6_ENTRIES, 147 TEGRA_ARI_CSTATE_STATS_D15_CC7_ENTRIES, 148 TEGRA_ARI_CSTATE_STATS_D15_0_C6_ENTRIES, 149 TEGRA_ARI_CSTATE_STATS_D15_1_C6_ENTRIES, 150 TEGRA_ARI_CSTATE_STATS_D15_0_C7_ENTRIES = 14, 151 TEGRA_ARI_CSTATE_STATS_D15_1_C7_ENTRIES, 152 TEGRA_ARI_CSTATE_STATS_A57_0_C7_ENTRIES = 18, 153 TEGRA_ARI_CSTATE_STATS_A57_1_C7_ENTRIES, 154 TEGRA_ARI_CSTATE_STATS_A57_2_C7_ENTRIES, 155 TEGRA_ARI_CSTATE_STATS_A57_3_C7_ENTRIES, 156 TEGRA_ARI_CSTATE_STATS_LAST_CSTATE_ENTRY_D15_0, 157 TEGRA_ARI_CSTATE_STATS_LAST_CSTATE_ENTRY_D15_1, 158 TEGRA_ARI_CSTATE_STATS_LAST_CSTATE_ENTRY_A57_0 = 26, 159 TEGRA_ARI_CSTATE_STATS_LAST_CSTATE_ENTRY_A57_1, 160 TEGRA_ARI_CSTATE_STATS_LAST_CSTATE_ENTRY_A57_2, 161 TEGRA_ARI_CSTATE_STATS_LAST_CSTATE_ENTRY_A57_3, 162 } tegra_ari_cstate_stats_index_t; 163 164 typedef enum { 165 TEGRA_ARI_GSC_ALL = 0, 166 167 TEGRA_ARI_GSC_BPMP = 6, 168 TEGRA_ARI_GSC_APE = 7, 169 TEGRA_ARI_GSC_SPE = 8, 170 TEGRA_ARI_GSC_SCE = 9, 171 TEGRA_ARI_GSC_APR = 10, 172 TEGRA_ARI_GSC_TZRAM = 11, 173 TEGRA_ARI_GSC_SE = 12, 174 175 TEGRA_ARI_GSC_BPMP_TO_SPE = 16, 176 TEGRA_ARI_GSC_SPE_TO_BPMP = 17, 177 TEGRA_ARI_GSC_CPU_TZ_TO_BPMP = 18, 178 TEGRA_ARI_GSC_BPMP_TO_CPU_TZ = 19, 179 TEGRA_ARI_GSC_CPU_NS_TO_BPMP = 20, 180 TEGRA_ARI_GSC_BPMP_TO_CPU_NS = 21, 181 TEGRA_ARI_GSC_IPC_SE_SPE_SCE_BPMP = 22, 182 TEGRA_ARI_GSC_SC7_RESUME_FW = 23, 183 184 TEGRA_ARI_GSC_TZ_DRAM_IDX = 34, 185 TEGRA_ARI_GSC_VPR_IDX = 35, 186 } tegra_ari_gsc_index_t; 187 188 /* This macro will produce enums for __name##_LSB, __name##_MSB and __name##_MSK */ 189 #define TEGRA_ARI_ENUM_MASK_LSB_MSB(__name, __lsb, __msb) __name##_LSB = __lsb, __name##_MSB = __msb 190 191 typedef enum { 192 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_UPDATE_CSTATE_INFO__CLUSTER_CSTATE, 0, 2), 193 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_UPDATE_CSTATE_INFO__CLUSTER_CSTATE_PRESENT, 7, 7), 194 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_UPDATE_CSTATE_INFO__CCPLEX_CSTATE, 8, 9), 195 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_UPDATE_CSTATE_INFO__CCPLEX_CSTATE_PRESENT, 15, 15), 196 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_UPDATE_CSTATE_INFO__SYSTEM_CSTATE, 16, 19), 197 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_UPDATE_CSTATE_INFO__IGNORE_CROSSOVERS, 22, 22), 198 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_UPDATE_CSTATE_INFO__SYSTEM_CSTATE_PRESENT, 23, 23), 199 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_UPDATE_CSTATE_INFO__WAKE_MASK_PRESENT, 31, 31), 200 } tegra_ari_update_cstate_info_bitmasks_t; 201 202 typedef enum { 203 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MISC_CCPLEX_CORESIGHT_CG_CTRL__EN, 0, 0), 204 } tegra_ari_misc_ccplex_bitmasks_t; 205 206 typedef enum { 207 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_CC3_CTRL__IDLE_FREQ, 0, 8), 208 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_CC3_CTRL__IDLE_VOLT, 16, 23), 209 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_CC3_CTRL__ENABLE, 31, 31), 210 } tegra_ari_cc3_ctrl_bitmasks_t; 211 212 typedef enum { 213 TEGRA_ARI_MCA_NOP = 0, 214 TEGRA_ARI_MCA_READ_SERR = 1, 215 TEGRA_ARI_MCA_WRITE_SERR = 2, 216 TEGRA_ARI_MCA_CLEAR_SERR = 4, 217 TEGRA_ARI_MCA_REPORT_SERR = 5, 218 TEGRA_ARI_MCA_READ_INTSTS = 6, 219 TEGRA_ARI_MCA_WRITE_INTSTS = 7, 220 TEGRA_ARI_MCA_READ_PREBOOT_SERR = 8, 221 } tegra_ari_mca_commands_t; 222 223 typedef enum { 224 TEGRA_ARI_MCA_RD_WR_DPMU = 0, 225 TEGRA_ARI_MCA_RD_WR_IOB = 1, 226 TEGRA_ARI_MCA_RD_WR_MCB = 2, 227 TEGRA_ARI_MCA_RD_WR_CCE = 3, 228 TEGRA_ARI_MCA_RD_WR_CQX = 4, 229 TEGRA_ARI_MCA_RD_WR_CTU = 5, 230 TEGRA_ARI_MCA_RD_WR_JSR_MTS = 7, 231 TEGRA_ARI_MCA_RD_BANK_INFO = 0x0f, 232 TEGRA_ARI_MCA_RD_BANK_TEMPLATE = 0x10, 233 TEGRA_ARI_MCA_RD_WR_SECURE_ACCESS_REGISTER = 0x11, 234 TEGRA_ARI_MCA_RD_WR_GLOBAL_CONFIG_REGISTER = 0x12, 235 } tegra_ari_mca_rd_wr_indexes_t; 236 237 typedef enum { 238 TEGRA_ARI_MCA_RD_WR_ASERRX_CTRL = 0, 239 TEGRA_ARI_MCA_RD_WR_ASERRX_STATUS = 1, 240 TEGRA_ARI_MCA_RD_WR_ASERRX_ADDR = 2, 241 TEGRA_ARI_MCA_RD_WR_ASERRX_MISC1 = 3, 242 TEGRA_ARI_MCA_RD_WR_ASERRX_MISC2 = 4, 243 } tegra_ari_mca_read_asserx_subindexes_t; 244 245 typedef enum { 246 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_SECURE_REGISTER_SETTING_ENABLES_NS_PERMITTED, 0, 0), 247 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_SECURE_REGISTER_READING_STATUS_NS_PERMITTED, 1, 1), 248 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_SECURE_REGISTER_PENDING_MCA_ERRORS_NS_PERMITTED, 2, 2), 249 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_SECURE_REGISTER_CLEARING_MCA_INTERRUPTS_NS_PERMITTED, 3, 3), 250 } tegra_ari_mca_secure_register_bitmasks_t; 251 252 typedef enum { 253 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR0_STAT_SERR_ERR_CODE, 0, 15), 254 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR0_STAT_PWM_ERR, 16, 16), 255 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR0_STAT_CRAB_ERR, 17, 17), 256 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR0_STAT_RD_WR_N, 18, 18), 257 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR0_STAT_UCODE_ERR, 19, 19), 258 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR0_STAT_PWM, 20, 23), 259 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR0_STAT_AV, 58, 58), 260 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR0_STAT_MV, 59, 59), 261 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR0_STAT_EN, 60, 60), 262 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR0_STAT_UC, 61, 61), 263 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR0_STAT_OVF, 62, 62), 264 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR0_STAT_VAL, 63, 63), 265 266 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR0_ADDR_ADDR, 0, 41), 267 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR0_ADDR_UCODE_ERRCD, 42, 52), 268 269 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR0_CTRL_EN_PWM_ERR, 0, 0), 270 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR0_CTRL_EN_CRAB_ERR, 1, 1), 271 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR0_CTRL_EN_UCODE_ERR, 3, 3), 272 } tegra_ari_mca_aserr0_bitmasks_t; 273 274 typedef enum { 275 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR1_STAT_SERR_ERR_CODE, 0, 15), 276 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR1_STAT_MSI_ERR, 16, 16), 277 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR1_STAT_IHI_ERR, 17, 17), 278 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR1_STAT_CRI_ERR, 18, 18), 279 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR1_STAT_MMCRAB_ERR, 19, 19), 280 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR1_STAT_CSI_ERR, 20, 20), 281 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR1_STAT_RD_WR_N, 21, 21), 282 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR1_STAT_REQ_ERRT, 22, 23), 283 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR1_STAT_RESP_ERRT, 24, 25), 284 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR1_STAT_AV, 58, 58), 285 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR1_STAT_MV, 59, 59), 286 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR1_STAT_EN, 60, 60), 287 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR1_STAT_UC, 61, 61), 288 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR1_STAT_OVF, 62, 62), 289 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR1_STAT_VAL, 63, 63), 290 291 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR1_STAT_AXI_ID, 0, 7), 292 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR1_STAT_CQX_ID, 8, 27), 293 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR1_STAT_CQX_CID, 28, 31), 294 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR1_STAT_CQX_CMD, 32, 35), 295 296 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR1_CTRL_EN_MSI_ERR, 0, 0), 297 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR1_CTRL_EN_IHI_ERR, 1, 1), 298 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR1_CTRL_EN_CRI_ERR, 2, 2), 299 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR1_CTRL_EN_MMCRAB_ERR, 3, 3), 300 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR1_CTRL_EN_CSI_ERR, 4, 4), 301 302 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR1_MISC_ADDR, 0, 41), 303 } tegra_ari_mca_aserr1_bitmasks_t; 304 305 typedef enum { 306 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR2_STAT_SERR_ERR_CODE, 0, 15), 307 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR2_STAT_MC_ERR, 16, 16), 308 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR2_STAT_SYSRAM_ERR, 17, 17), 309 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR2_STAT_CLIENT_ID, 18, 19), 310 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR2_STAT_AV, 58, 58), 311 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR2_STAT_MV, 59, 59), 312 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR2_STAT_EN, 60, 60), 313 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR2_STAT_UC, 61, 61), 314 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR2_STAT_OVF, 62, 62), 315 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR2_STAT_VAL, 63, 63), 316 317 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR2_ADDR_ID, 0, 17), 318 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR2_ADDR_CMD, 18, 21), 319 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR2_ADDR_ADDR, 22, 53), 320 321 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR2_CTRL_EN_MC_ERR, 0, 0), 322 } tegra_ari_mca_aserr2_bitmasks_t; 323 324 typedef enum { 325 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_STAT_SERR_ERR_CODE, 0, 15), 326 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_STAT_TO_ERR, 16, 16), 327 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_STAT_STAT_ERR, 17, 17), 328 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_STAT_DST_ERR, 18, 18), 329 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_STAT_UNC_ERR, 19, 19), 330 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_STAT_MH_ERR, 20, 20), 331 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_STAT_PERR, 21, 21), 332 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_STAT_PSN_ERR, 22, 22), 333 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_STAT_AV, 58, 58), 334 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_STAT_MV, 59, 59), 335 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_STAT_EN, 60, 60), 336 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_STAT_UC, 61, 61), 337 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_STAT_OVF, 62, 62), 338 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_STAT_VAL, 63, 63), 339 340 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_ADDR_CMD, 0, 5), 341 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_ADDR_ADDR, 6, 47), 342 343 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_MISC1_TO, 0, 0), 344 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_MISC1_DIV4, 1, 1), 345 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_MISC1_TLIMIT, 2, 11), 346 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_MISC1_PSN_ERR_CORR_MSK, 12, 25), 347 348 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_MISC2_MORE_INFO, 0, 17), 349 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_MISC2_TO_INFO, 18, 43), 350 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_MISC2_SRC, 44, 45), 351 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_MISC2_TID, 46, 52), 352 353 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_CTRL_EN_TO_ERR, 0, 0), 354 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_CTRL_EN_STAT_ERR, 1, 1), 355 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_CTRL_EN_DST_ERR, 2, 2), 356 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_CTRL_EN_UNC_ERR, 3, 3), 357 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_CTRL_EN_MH_ERR, 4, 4), 358 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_CTRL_EN_PERR, 5, 5), 359 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_CTRL_EN_PSN_ERR, 6, 19), 360 } tegra_ari_mca_aserr3_bitmasks_t; 361 362 typedef enum { 363 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR4_STAT_SERR_ERR_CODE, 0, 15), 364 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR4_STAT_SRC_ERR, 16, 16), 365 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR4_STAT_DST_ERR, 17, 17), 366 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR4_STAT_REQ_ERR, 18, 18), 367 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR4_STAT_RSP_ERR, 19, 19), 368 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR4_STAT_AV, 58, 58), 369 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR4_STAT_MV, 59, 59), 370 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR4_STAT_EN, 60, 60), 371 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR4_STAT_UC, 61, 61), 372 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR4_STAT_OVF, 62, 62), 373 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR4_STAT_VAL, 63, 63), 374 375 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR4_CTRL_EN_CPE_ERR, 0, 0), 376 } tegra_ari_mca_aserr4_bitmasks_t; 377 378 typedef enum { 379 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR5_STAT_SERR_ERR_CODE, 0, 15), 380 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR5_STAT_CTUPAR, 16, 16), 381 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR5_STAT_MULTI, 17, 17), 382 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR5_STAT_AV, 58, 58), 383 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR5_STAT_MV, 59, 59), 384 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR5_STAT_EN, 60, 60), 385 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR5_STAT_UC, 61, 61), 386 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR5_STAT_OVF, 62, 62), 387 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR5_STAT_VAL, 63, 63), 388 389 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR5_ADDR_SRC, 0, 7), 390 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR5_ADDR_ID, 8, 15), 391 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR5_ADDR_DATA, 16, 26), 392 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR5_ADDR_CMD, 32, 35), 393 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR5_ADDR_ADDR, 36, 45), 394 395 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR5_CTRL_EN_CTUPAR, 0, 0), 396 } tegra_ari_mca_aserr5_bitmasks_t; 397 398 typedef enum { 399 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_SERR1_STAT_SERR_ERR_CODE, 0, 15), 400 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_SERR1_STAT_AV, 58, 58), 401 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_SERR1_STAT_MV, 59, 59), 402 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_SERR1_STAT_EN, 60, 60), 403 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_SERR1_STAT_UC, 61, 61), 404 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_SERR1_STAT_OVF, 62, 62), 405 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_SERR1_STAT_VAL, 63, 63), 406 TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_SERR1_ADDR_TBD_INFO, 0, 63), 407 } tegra_ari_mca_serr1_bitmasks_t; 408 409 #undef TEGRA_ARI_ENUM_MASK_LSB_MSB 410 411 typedef enum { 412 TEGRA_NVG_CHANNEL_PMIC = 0, 413 TEGRA_NVG_CHANNEL_POWER_PERF = 1, 414 TEGRA_NVG_CHANNEL_POWER_MODES = 2, 415 TEGRA_NVG_CHANNEL_WAKE_TIME = 3, 416 TEGRA_NVG_CHANNEL_CSTATE_INFO = 4, 417 TEGRA_NVG_CHANNEL_CROSSOVER_C1_C6 = 5, 418 TEGRA_NVG_CHANNEL_CROSSOVER_CC1_CC6 = 6, 419 TEGRA_NVG_CHANNEL_CROSSOVER_CC1_CC7 = 7, 420 TEGRA_NVG_CHANNEL_CROSSOVER_CCP1_CCP3 = 8, /* obsoleted */ 421 TEGRA_NVG_CHANNEL_CROSSOVER_CCP3_SC2 = 9, /* obsoleted */ 422 TEGRA_NVG_CHANNEL_CROSSOVER_CCP3_SC3 = 10, /* obsoleted */ 423 TEGRA_NVG_CHANNEL_CROSSOVER_CCP3_SC4 = 11, /* obsoleted */ 424 TEGRA_NVG_CHANNEL_CROSSOVER_CCP3_SC7 = 12, /* obsoleted */ 425 TEGRA_NVG_CHANNEL_CROSSOVER_SC0_SC7 = 12, 426 TEGRA_NVG_CHANNEL_CSTATE_STATS_CLEAR = 13, 427 TEGRA_NVG_CHANNEL_CSTATE_STATS_SC7_ENTRIES = 14, 428 TEGRA_NVG_CHANNEL_CSTATE_STATS_SC4_ENTRIES = 15, /* obsoleted */ 429 TEGRA_NVG_CHANNEL_CSTATE_STATS_SC3_ENTRIES = 16, /* obsoleted */ 430 TEGRA_NVG_CHANNEL_CSTATE_STATS_SC2_ENTRIES = 17, /* obsoleted */ 431 TEGRA_NVG_CHANNEL_CSTATE_STATS_CCP3_ENTRIES = 18, /* obsoleted */ 432 TEGRA_NVG_CHANNEL_CSTATE_STATS_A57_CC6_ENTRIES = 19, 433 TEGRA_NVG_CHANNEL_CSTATE_STATS_A57_CC7_ENTRIES = 20, 434 TEGRA_NVG_CHANNEL_CSTATE_STATS_D15_CC6_ENTRIES = 21, 435 TEGRA_NVG_CHANNEL_CSTATE_STATS_D15_CC7_ENTRIES = 22, 436 TEGRA_NVG_CHANNEL_CSTATE_STATS_D15_0_C6_ENTRIES = 23, 437 TEGRA_NVG_CHANNEL_CSTATE_STATS_D15_1_C6_ENTRIES = 24, 438 TEGRA_NVG_CHANNEL_CSTATE_STATS_D15_2_C6_ENTRIES = 25, /* Reserved (for Denver15 core 2) */ 439 TEGRA_NVG_CHANNEL_CSTATE_STATS_D15_3_C6_ENTRIES = 26, /* Reserved (for Denver15 core 3) */ 440 TEGRA_NVG_CHANNEL_CSTATE_STATS_D15_0_C7_ENTRIES = 27, 441 TEGRA_NVG_CHANNEL_CSTATE_STATS_D15_1_C7_ENTRIES = 28, 442 TEGRA_NVG_CHANNEL_CSTATE_STATS_D15_2_C7_ENTRIES = 29, /* Reserved (for Denver15 core 2) */ 443 TEGRA_NVG_CHANNEL_CSTATE_STATS_D15_3_C7_ENTRIES = 30, /* Reserved (for Denver15 core 3) */ 444 TEGRA_NVG_CHANNEL_CSTATE_STATS_A57_0_C7_ENTRIES = 31, 445 TEGRA_NVG_CHANNEL_CSTATE_STATS_A57_1_C7_ENTRIES = 32, 446 TEGRA_NVG_CHANNEL_CSTATE_STATS_A57_2_C7_ENTRIES = 33, 447 TEGRA_NVG_CHANNEL_CSTATE_STATS_A57_3_C7_ENTRIES = 34, 448 TEGRA_NVG_CHANNEL_CSTATE_STATS_LAST_CSTATE_ENTRY_D15_0 = 35, 449 TEGRA_NVG_CHANNEL_CSTATE_STATS_LAST_CSTATE_ENTRY_D15_1 = 36, 450 TEGRA_NVG_CHANNEL_CSTATE_STATS_LAST_CSTATE_ENTRY_D15_2 = 37, /* Reserved (for Denver15 core 2) */ 451 TEGRA_NVG_CHANNEL_CSTATE_STATS_LAST_CSTATE_ENTRY_D15_3 = 38, /* Reserved (for Denver15 core 3) */ 452 TEGRA_NVG_CHANNEL_CSTATE_STATS_LAST_CSTATE_ENTRY_A57_0 = 39, 453 TEGRA_NVG_CHANNEL_CSTATE_STATS_LAST_CSTATE_ENTRY_A57_1 = 40, 454 TEGRA_NVG_CHANNEL_CSTATE_STATS_LAST_CSTATE_ENTRY_A57_2 = 41, 455 TEGRA_NVG_CHANNEL_CSTATE_STATS_LAST_CSTATE_ENTRY_A57_3 = 42, 456 TEGRA_NVG_CHANNEL_IS_SC7_ALLOWED = 43, 457 TEGRA_NVG_CHANNEL_ONLINE_CORE = 44, 458 TEGRA_NVG_CHANNEL_CC3_CTRL = 45, 459 TEGRA_NVG_CHANNEL_CROSSOVER_CCP3_SC1 = 46, /* obsoleted */ 460 TEGRA_NVG_CHANNEL_LAST_INDEX, 461 } tegra_nvg_channel_id_t; 462 463 #endif /* T18X_TEGRA_ARI_H */ 464