1 /* 2 * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #ifndef __MCE_PRIVATE_H__ 32 #define __MCE_PRIVATE_H__ 33 34 #include <mmio.h> 35 #include <tegra_def.h> 36 37 /******************************************************************************* 38 * Macros to prepare CSTATE info request 39 ******************************************************************************/ 40 /* Description of the parameters for UPDATE_CSTATE_INFO request */ 41 #define CLUSTER_CSTATE_MASK 0x7 42 #define CLUSTER_CSTATE_SHIFT 0 43 #define CLUSTER_CSTATE_UPDATE_BIT (1 << 7) 44 #define CCPLEX_CSTATE_MASK 0x3 45 #define CCPLEX_CSTATE_SHIFT 8 46 #define CCPLEX_CSTATE_UPDATE_BIT (1 << 15) 47 #define SYSTEM_CSTATE_MASK 0xF 48 #define SYSTEM_CSTATE_SHIFT 16 49 #define SYSTEM_CSTATE_FORCE_UPDATE_SHIFT 22 50 #define SYSTEM_CSTATE_FORCE_UPDATE_BIT (1 << 22) 51 #define SYSTEM_CSTATE_UPDATE_BIT (1 << 23) 52 #define CSTATE_WAKE_MASK_UPDATE_BIT (1 << 31) 53 #define CSTATE_WAKE_MASK_SHIFT 32 54 #define CSTATE_WAKE_MASK_CLEAR 0xFFFFFFFF 55 56 /******************************************************************************* 57 * Auto-CC3 control macros 58 ******************************************************************************/ 59 #define MCE_AUTO_CC3_FREQ_MASK 0x1FF 60 #define MCE_AUTO_CC3_FREQ_SHIFT 0 61 #define MCE_AUTO_CC3_VTG_MASK 0x7F 62 #define MCE_AUTO_CC3_VTG_SHIFT 16 63 #define MCE_AUTO_CC3_ENABLE_BIT (1 << 31) 64 65 /******************************************************************************* 66 * Macros for the 'IS_SC7_ALLOWED' command 67 ******************************************************************************/ 68 #define MCE_SC7_ALLOWED_MASK 0x7 69 #define MCE_SC7_WAKE_TIME_SHIFT 32 70 71 /******************************************************************************* 72 * Macros for 'read/write ctats' commands 73 ******************************************************************************/ 74 #define MCE_CSTATE_STATS_TYPE_SHIFT 32 75 #define MCE_CSTATE_WRITE_DATA_LO_MASK 0xF 76 77 /******************************************************************************* 78 * Macros for 'update crossover threshold' command 79 ******************************************************************************/ 80 #define MCE_CROSSOVER_THRESHOLD_TIME_SHIFT 32 81 82 /******************************************************************************* 83 * MCA command struct 84 ******************************************************************************/ 85 typedef union mca_cmd { 86 struct command { 87 uint8_t cmd; 88 uint8_t idx; 89 uint8_t subidx; 90 } command; 91 struct input { 92 uint32_t low; 93 uint32_t high; 94 } input; 95 uint64_t data; 96 } mca_cmd_t; 97 98 /******************************************************************************* 99 * MCA argument struct 100 ******************************************************************************/ 101 typedef union mca_arg { 102 struct err { 103 uint64_t error:8; 104 uint64_t unused:48; 105 uint64_t finish:8; 106 } err; 107 struct arg { 108 uint32_t low; 109 uint32_t high; 110 } arg; 111 uint64_t data; 112 } mca_arg_t; 113 114 /******************************************************************************* 115 * Uncore PERFMON ARI struct 116 ******************************************************************************/ 117 typedef union uncore_perfmon_req { 118 struct perfmon_command { 119 /* 120 * Commands: 0 = READ, 1 = WRITE 121 */ 122 uint64_t cmd:8; 123 /* 124 * The unit group: L2=0, L3=1, ROC=2, MC=3, IOB=4 125 */ 126 uint64_t grp:4; 127 /* 128 * Unit selector: Selects the unit instance, with 0 = Unit 129 * = (number of units in group) - 1. 130 */ 131 uint64_t unit:4; 132 /* 133 * Selects the uncore perfmon register to access 134 */ 135 uint64_t reg:8; 136 /* 137 * Counter number. Selects which counter to use for 138 * registers NV_PMEVCNTR and NV_PMEVTYPER. 139 */ 140 uint64_t counter:8; 141 } perfmon_command; 142 struct perfmon_status { 143 /* 144 * Resulting command status 145 */ 146 uint64_t val:8; 147 uint64_t unused:24; 148 } perfmon_status; 149 uint64_t data; 150 } uncore_perfmon_req_t; 151 152 #define UNCORE_PERFMON_CMD_READ 0 153 #define UNCORE_PERFMON_CMD_WRITE 1 154 155 #define UNCORE_PERFMON_CMD_MASK 0xFF 156 #define UNCORE_PERFMON_UNIT_GRP_MASK 0xF 157 #define UNCORE_PERFMON_SELECTOR_MASK 0xF 158 #define UNCORE_PERFMON_REG_MASK 0xFF 159 #define UNCORE_PERFMON_CTR_MASK 0xFF 160 #define UNCORE_PERFMON_RESP_STATUS_MASK 0xFF 161 162 /******************************************************************************* 163 * Structure populated by arch specific code to export routines which perform 164 * common low level MCE functions 165 ******************************************************************************/ 166 typedef struct arch_mce_ops { 167 /* 168 * This ARI request sets up the MCE to start execution on assertion 169 * of STANDBYWFI, update the core power state and expected wake time, 170 * then determine the proper power state to enter. 171 */ 172 int (*enter_cstate)(uint32_t ari_base, uint32_t state, 173 uint32_t wake_time); 174 /* 175 * This ARI request allows updating of the CLUSTER_CSTATE, 176 * CCPLEX_CSTATE, and SYSTEM_CSTATE register values. 177 */ 178 int (*update_cstate_info)(uint32_t ari_base, 179 uint32_t cluster, 180 uint32_t ccplex, 181 uint32_t system, 182 uint8_t sys_state_force, 183 uint32_t wake_mask, 184 uint8_t update_wake_mask); 185 /* 186 * This ARI request allows updating of power state crossover 187 * threshold times. An index value specifies which crossover 188 * state is being updated. 189 */ 190 int (*update_crossover_time)(uint32_t ari_base, 191 uint32_t type, 192 uint32_t time); 193 /* 194 * This ARI request allows read access to statistical information 195 * related to power states. 196 */ 197 uint64_t (*read_cstate_stats)(uint32_t ari_base, 198 uint32_t state); 199 /* 200 * This ARI request allows write access to statistical information 201 * related to power states. 202 */ 203 int (*write_cstate_stats)(uint32_t ari_base, 204 uint32_t state, 205 uint32_t stats); 206 /* 207 * This ARI request allows the CPU to understand the features 208 * supported by the MCE firmware. 209 */ 210 uint64_t (*call_enum_misc)(uint32_t ari_base, uint32_t cmd, 211 uint32_t data); 212 /* 213 * This ARI request allows querying the CCPLEX to determine if 214 * the CCx state is allowed given a target core C-state and wake 215 * time. If the CCx state is allowed, the response indicates CCx 216 * must be entered. If the CCx state is not allowed, the response 217 * indicates CC6/CC7 can't be entered 218 */ 219 int (*is_ccx_allowed)(uint32_t ari_base, uint32_t state, 220 uint32_t wake_time); 221 /* 222 * This ARI request allows querying the CCPLEX to determine if 223 * the SC7 state is allowed given a target core C-state and wake 224 * time. If the SC7 state is allowed, all cores but the associated 225 * core are offlined (WAKE_EVENTS are set to 0) and the response 226 * indicates SC7 must be entered. If the SC7 state is not allowed, 227 * the response indicates SC7 can't be entered 228 */ 229 int (*is_sc7_allowed)(uint32_t ari_base, uint32_t state, 230 uint32_t wake_time); 231 /* 232 * This ARI request allows a core to bring another offlined core 233 * back online to the C0 state. Note that a core is offlined by 234 * entering a C-state where the WAKE_MASK is all 0. 235 */ 236 int (*online_core)(uint32_t ari_base, uint32_t cpuid); 237 /* 238 * This ARI request allows the CPU to enable/disable Auto-CC3 idle 239 * state. 240 */ 241 int (*cc3_ctrl)(uint32_t ari_base, 242 uint32_t freq, 243 uint32_t volt, 244 uint8_t enable); 245 /* 246 * This ARI request allows updating the reset vector register for 247 * D15 and A57 CPUs. 248 */ 249 int (*update_reset_vector)(uint32_t ari_base); 250 /* 251 * This ARI request instructs the ROC to flush A57 data caches in 252 * order to maintain coherency with the Denver cluster. 253 */ 254 int (*roc_flush_cache)(uint32_t ari_base); 255 /* 256 * This ARI request instructs the ROC to flush A57 data caches along 257 * with the caches covering ARM code in order to maintain coherency 258 * with the Denver cluster. 259 */ 260 int (*roc_flush_cache_trbits)(uint32_t ari_base); 261 /* 262 * This ARI request instructs the ROC to clean A57 data caches along 263 * with the caches covering ARM code in order to maintain coherency 264 * with the Denver cluster. 265 */ 266 int (*roc_clean_cache)(uint32_t ari_base); 267 /* 268 * This ARI request reads/writes the Machine Check Arch. (MCA) 269 * registers. 270 */ 271 uint64_t (*read_write_mca)(uint32_t ari_base, 272 mca_cmd_t cmd, 273 uint64_t *data); 274 /* 275 * Some MC GSC (General Security Carveout) register values are 276 * expected to be changed by TrustZone secure ARM code after boot. 277 * Since there is no hardware mechanism for the CCPLEX to know 278 * that an MC GSC register has changed to allow it to update its 279 * own internal GSC register, there needs to be a mechanism that 280 * can be used by ARM code to cause the CCPLEX to update its GSC 281 * register value. This ARI request allows updating the GSC register 282 * value for a certain carveout in the CCPLEX. 283 */ 284 int (*update_ccplex_gsc)(uint32_t ari_base, uint32_t gsc_idx); 285 /* 286 * This ARI request instructs the CCPLEX to either shutdown or 287 * reset the entire system 288 */ 289 void (*enter_ccplex_state)(uint32_t ari_base, uint32_t state_idx); 290 /* 291 * This ARI request reads/writes data from/to Uncore PERFMON 292 * registers 293 */ 294 int (*read_write_uncore_perfmon)(uint32_t ari_base, 295 uncore_perfmon_req_t req, uint64_t *data); 296 /* 297 * This ARI implements ARI_MISC_CCPLEX commands. This can be 298 * used to enable/disable coresight clock gating. 299 */ 300 void (*misc_ccplex)(uint32_t ari_base, uint32_t index, 301 uint32_t value); 302 } arch_mce_ops_t; 303 304 /* declarations for ARI/NVG handler functions */ 305 int ari_enter_cstate(uint32_t ari_base, uint32_t state, uint32_t wake_time); 306 int ari_update_cstate_info(uint32_t ari_base, uint32_t cluster, uint32_t ccplex, 307 uint32_t system, uint8_t sys_state_force, uint32_t wake_mask, 308 uint8_t update_wake_mask); 309 int ari_update_crossover_time(uint32_t ari_base, uint32_t type, uint32_t time); 310 uint64_t ari_read_cstate_stats(uint32_t ari_base, uint32_t state); 311 int ari_write_cstate_stats(uint32_t ari_base, uint32_t state, uint32_t stats); 312 uint64_t ari_enumeration_misc(uint32_t ari_base, uint32_t cmd, uint32_t data); 313 int ari_is_ccx_allowed(uint32_t ari_base, uint32_t state, uint32_t wake_time); 314 int ari_is_sc7_allowed(uint32_t ari_base, uint32_t state, uint32_t wake_time); 315 int ari_online_core(uint32_t ari_base, uint32_t core); 316 int ari_cc3_ctrl(uint32_t ari_base, uint32_t freq, uint32_t volt, uint8_t enable); 317 int ari_reset_vector_update(uint32_t ari_base); 318 int ari_roc_flush_cache_trbits(uint32_t ari_base); 319 int ari_roc_flush_cache(uint32_t ari_base); 320 int ari_roc_clean_cache(uint32_t ari_base); 321 uint64_t ari_read_write_mca(uint32_t ari_base, mca_cmd_t cmd, uint64_t *data); 322 int ari_update_ccplex_gsc(uint32_t ari_base, uint32_t gsc_idx); 323 void ari_enter_ccplex_state(uint32_t ari_base, uint32_t state_idx); 324 int ari_read_write_uncore_perfmon(uint32_t ari_base, 325 uncore_perfmon_req_t req, uint64_t *data); 326 void ari_misc_ccplex(uint32_t ari_base, uint32_t index, uint32_t value); 327 328 int nvg_enter_cstate(uint32_t ari_base, uint32_t state, uint32_t wake_time); 329 int nvg_update_cstate_info(uint32_t ari_base, uint32_t cluster, uint32_t ccplex, 330 uint32_t system, uint8_t sys_state_force, uint32_t wake_mask, 331 uint8_t update_wake_mask); 332 int nvg_update_crossover_time(uint32_t ari_base, uint32_t type, uint32_t time); 333 uint64_t nvg_read_cstate_stats(uint32_t ari_base, uint32_t state); 334 int nvg_write_cstate_stats(uint32_t ari_base, uint32_t state, uint32_t val); 335 int nvg_is_ccx_allowed(uint32_t ari_base, uint32_t state, uint32_t wake_time); 336 int nvg_is_sc7_allowed(uint32_t ari_base, uint32_t state, uint32_t wake_time); 337 int nvg_online_core(uint32_t ari_base, uint32_t core); 338 int nvg_cc3_ctrl(uint32_t ari_base, uint32_t freq, uint32_t volt, uint8_t enable); 339 340 #endif /* __MCE_PRIVATE_H__ */ 341