1 /* 2 * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <arch_helpers.h> 32 #include <assert.h> 33 #include <bl31.h> 34 #include <bl_common.h> 35 #include <console.h> 36 #include <context.h> 37 #include <context_mgmt.h> 38 #include <cortex_a57.h> 39 #include <debug.h> 40 #include <denver.h> 41 #include <interrupt_mgmt.h> 42 #include <mce.h> 43 #include <platform.h> 44 #include <tegra_def.h> 45 #include <tegra_platform.h> 46 #include <tegra_private.h> 47 #include <xlat_tables.h> 48 49 DEFINE_RENAME_SYSREG_RW_FUNCS(l2ctlr_el1, L2CTLR_EL1) 50 extern uint64_t tegra_enable_l2_ecc_parity_prot; 51 52 /******************************************************************************* 53 * Tegra186 CPU numbers in cluster #0 54 ******************************************************************************* 55 */ 56 #define TEGRA186_CLUSTER0_CORE2 2 57 #define TEGRA186_CLUSTER0_CORE3 3 58 59 /******************************************************************************* 60 * The Tegra power domain tree has a single system level power domain i.e. a 61 * single root node. The first entry in the power domain descriptor specifies 62 * the number of power domains at the highest power level. 63 ******************************************************************************* 64 */ 65 const unsigned char tegra_power_domain_tree_desc[] = { 66 /* No of root nodes */ 67 1, 68 /* No of clusters */ 69 PLATFORM_CLUSTER_COUNT, 70 /* No of CPU cores - cluster0 */ 71 PLATFORM_MAX_CPUS_PER_CLUSTER, 72 /* No of CPU cores - cluster1 */ 73 PLATFORM_MAX_CPUS_PER_CLUSTER 74 }; 75 76 /* 77 * Table of regions to map using the MMU. 78 */ 79 static const mmap_region_t tegra_mmap[] = { 80 MAP_REGION_FLAT(TEGRA_MISC_BASE, 0x10000, /* 64KB */ 81 MT_DEVICE | MT_RW | MT_SECURE), 82 MAP_REGION_FLAT(TEGRA_TSA_BASE, 0x20000, /* 128KB */ 83 MT_DEVICE | MT_RW | MT_SECURE), 84 MAP_REGION_FLAT(TEGRA_MC_STREAMID_BASE, 0x10000, /* 64KB */ 85 MT_DEVICE | MT_RW | MT_SECURE), 86 MAP_REGION_FLAT(TEGRA_MC_BASE, 0x10000, /* 64KB */ 87 MT_DEVICE | MT_RW | MT_SECURE), 88 MAP_REGION_FLAT(TEGRA_UARTA_BASE, 0x20000, /* 128KB - UART A, B*/ 89 MT_DEVICE | MT_RW | MT_SECURE), 90 MAP_REGION_FLAT(TEGRA_UARTC_BASE, 0x20000, /* 128KB - UART C, G */ 91 MT_DEVICE | MT_RW | MT_SECURE), 92 MAP_REGION_FLAT(TEGRA_UARTD_BASE, 0x30000, /* 192KB - UART D, E, F */ 93 MT_DEVICE | MT_RW | MT_SECURE), 94 MAP_REGION_FLAT(TEGRA_FUSE_BASE, 0x10000, /* 64KB */ 95 MT_DEVICE | MT_RW | MT_SECURE), 96 MAP_REGION_FLAT(TEGRA_GICD_BASE, 0x20000, /* 128KB */ 97 MT_DEVICE | MT_RW | MT_SECURE), 98 MAP_REGION_FLAT(TEGRA_SE0_BASE, 0x10000, /* 64KB */ 99 MT_DEVICE | MT_RW | MT_SECURE), 100 MAP_REGION_FLAT(TEGRA_PKA1_BASE, 0x10000, /* 64KB */ 101 MT_DEVICE | MT_RW | MT_SECURE), 102 MAP_REGION_FLAT(TEGRA_RNG1_BASE, 0x10000, /* 64KB */ 103 MT_DEVICE | MT_RW | MT_SECURE), 104 MAP_REGION_FLAT(TEGRA_CAR_RESET_BASE, 0x10000, /* 64KB */ 105 MT_DEVICE | MT_RW | MT_SECURE), 106 MAP_REGION_FLAT(TEGRA_PMC_BASE, 0x40000, /* 256KB */ 107 MT_DEVICE | MT_RW | MT_SECURE), 108 MAP_REGION_FLAT(TEGRA_SCRATCH_BASE, 0x10000, /* 64KB */ 109 MT_DEVICE | MT_RW | MT_SECURE), 110 MAP_REGION_FLAT(TEGRA_MMCRAB_BASE, 0x60000, /* 384KB */ 111 MT_DEVICE | MT_RW | MT_SECURE), 112 MAP_REGION_FLAT(TEGRA_ARM_ACTMON_CTR_BASE, 0x20000, /* 128KB - ARM/Denver */ 113 MT_DEVICE | MT_RW | MT_SECURE), 114 #if ENABLE_SMMU_DEVICE 115 MAP_REGION_FLAT(TEGRA_SMMU_BASE, 0x1000000, /* 64KB */ 116 MT_DEVICE | MT_RW | MT_SECURE), 117 #endif 118 {0} 119 }; 120 121 /******************************************************************************* 122 * Set up the pagetables as per the platform memory map & initialize the MMU 123 ******************************************************************************/ 124 const mmap_region_t *plat_get_mmio_map(void) 125 { 126 /* MMIO space */ 127 return tegra_mmap; 128 } 129 130 /******************************************************************************* 131 * Handler to get the System Counter Frequency 132 ******************************************************************************/ 133 unsigned int plat_get_syscnt_freq2(void) 134 { 135 return 31250000; 136 } 137 138 /******************************************************************************* 139 * Maximum supported UART controllers 140 ******************************************************************************/ 141 #define TEGRA186_MAX_UART_PORTS 7 142 143 /******************************************************************************* 144 * This variable holds the UART port base addresses 145 ******************************************************************************/ 146 static uint32_t tegra186_uart_addresses[TEGRA186_MAX_UART_PORTS + 1] = { 147 0, /* undefined - treated as an error case */ 148 TEGRA_UARTA_BASE, 149 TEGRA_UARTB_BASE, 150 TEGRA_UARTC_BASE, 151 TEGRA_UARTD_BASE, 152 TEGRA_UARTE_BASE, 153 TEGRA_UARTF_BASE, 154 TEGRA_UARTG_BASE, 155 }; 156 157 /******************************************************************************* 158 * Retrieve the UART controller base to be used as the console 159 ******************************************************************************/ 160 uint32_t plat_get_console_from_id(int id) 161 { 162 if (id > TEGRA186_MAX_UART_PORTS) 163 return 0; 164 165 return tegra186_uart_addresses[id]; 166 } 167 168 /* represent chip-version as concatenation of major (15:12), minor (11:8) and subrev (7:0) */ 169 #define TEGRA186_VER_A02P 0x1201 170 171 /******************************************************************************* 172 * Handler for early platform setup 173 ******************************************************************************/ 174 void plat_early_platform_setup(void) 175 { 176 int impl = (read_midr() >> MIDR_IMPL_SHIFT) & MIDR_IMPL_MASK; 177 uint32_t chip_subrev, val; 178 179 /* sanity check MCE firmware compatibility */ 180 mce_verify_firmware_version(); 181 182 /* 183 * Enable ECC and Parity Protection for Cortex-A57 CPUs 184 * for Tegra A02p SKUs 185 */ 186 if (impl != DENVER_IMPL) { 187 188 /* get the major, minor and sub-version values */ 189 chip_subrev = mmio_read_32(TEGRA_FUSE_BASE + OPT_SUBREVISION) & 190 SUBREVISION_MASK; 191 192 /* prepare chip version number */ 193 val = (tegra_get_chipid_major() << 12) | 194 (tegra_get_chipid_minor() << 8) | 195 chip_subrev; 196 197 /* enable L2 ECC for Tegra186 A02P and beyond */ 198 if (val >= TEGRA186_VER_A02P) { 199 200 val = read_l2ctlr_el1(); 201 val |= L2_ECC_PARITY_PROTECTION_BIT; 202 write_l2ctlr_el1(val); 203 204 /* 205 * Set the flag to enable ECC/Parity Protection 206 * when we exit System Suspend or Cluster Powerdn 207 */ 208 tegra_enable_l2_ecc_parity_prot = 1; 209 } 210 } 211 } 212 213 /* Secure IRQs for Tegra186 */ 214 static const irq_sec_cfg_t tegra186_sec_irqs[] = { 215 { 216 TEGRA186_TOP_WDT_IRQ, 217 TEGRA186_SEC_IRQ_TARGET_MASK, 218 INTR_TYPE_EL3, 219 }, 220 { 221 TEGRA186_AON_WDT_IRQ, 222 TEGRA186_SEC_IRQ_TARGET_MASK, 223 INTR_TYPE_EL3, 224 }, 225 }; 226 227 /******************************************************************************* 228 * Initialize the GIC and SGIs 229 ******************************************************************************/ 230 void plat_gic_setup(void) 231 { 232 tegra_gic_setup(tegra186_sec_irqs, 233 sizeof(tegra186_sec_irqs) / sizeof(tegra186_sec_irqs[0])); 234 235 /* 236 * Initialize the FIQ handler only if the platform supports any 237 * FIQ interrupt sources. 238 */ 239 if (sizeof(tegra186_sec_irqs) > 0) 240 tegra_fiq_handler_setup(); 241 } 242 243 /******************************************************************************* 244 * Return pointer to the BL31 params from previous bootloader 245 ******************************************************************************/ 246 bl31_params_t *plat_get_bl31_params(void) 247 { 248 uint32_t val; 249 250 val = mmio_read_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV53_LO); 251 252 return (bl31_params_t *)(uintptr_t)val; 253 } 254 255 /******************************************************************************* 256 * Return pointer to the BL31 platform params from previous bootloader 257 ******************************************************************************/ 258 plat_params_from_bl2_t *plat_get_bl31_plat_params(void) 259 { 260 uint32_t val; 261 262 val = mmio_read_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV53_HI); 263 264 return (plat_params_from_bl2_t *)(uintptr_t)val; 265 } 266 267 /******************************************************************************* 268 * This function implements a part of the critical interface between the psci 269 * generic layer and the platform that allows the former to query the platform 270 * to convert an MPIDR to a unique linear index. An error code (-1) is returned 271 * in case the MPIDR is invalid. 272 ******************************************************************************/ 273 int plat_core_pos_by_mpidr(u_register_t mpidr) 274 { 275 unsigned int cluster_id, cpu_id, pos; 276 277 cluster_id = (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK; 278 cpu_id = (mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK; 279 280 /* 281 * Validate cluster_id by checking whether it represents 282 * one of the two clusters present on the platform. 283 */ 284 if (cluster_id >= PLATFORM_CLUSTER_COUNT) 285 return PSCI_E_NOT_PRESENT; 286 287 /* 288 * Validate cpu_id by checking whether it represents a CPU in 289 * one of the two clusters present on the platform. 290 */ 291 if (cpu_id >= PLATFORM_MAX_CPUS_PER_CLUSTER) 292 return PSCI_E_NOT_PRESENT; 293 294 /* calculate the core position */ 295 pos = cpu_id + (cluster_id << 2); 296 297 /* check for non-existent CPUs */ 298 if (pos == TEGRA186_CLUSTER0_CORE2 || pos == TEGRA186_CLUSTER0_CORE3) 299 return PSCI_E_NOT_PRESENT; 300 301 return pos; 302 } 303