feat(versal2): add bufferless IPI Support

Versal Gen 2 SOC has same IPI mapping as Versal NET SOC.

Ports the bufferless Versal NET IPI mapping to
Versal Gen 2.

Change-Id: I1dc11c8473c390a517fdd3a9

feat(versal2): add bufferless IPI Support

Versal Gen 2 SOC has same IPI mapping as Versal NET SOC.

Ports the bufferless Versal NET IPI mapping to
Versal Gen 2.

Change-Id: I1dc11c8473c390a517fdd3a9e4fc35dc5563792b
Signed-off-by: Ben Levinsky <ben.levinsky@amd.com>
Signed-off-by: Akshay Belsare <akshay.belsare@amd.com>

show more ...

chore(versal2): use BIT_32() macro

Use BIT_32() macro for readability for Versal Gen 2 IPI Bit positions.

Change-Id: I69718b22de890519e906be185f593b4fd9df1be5
Signed-off-by: Ben Levinsky <ben.levin

chore(versal2): use BIT_32() macro

Use BIT_32() macro for readability for Versal Gen 2 IPI Bit positions.

Change-Id: I69718b22de890519e906be185f593b4fd9df1be5
Signed-off-by: Ben Levinsky <ben.levinsky@amd.com>
Signed-off-by: Akshay Belsare <akshay.belsare@amd.com>

show more ...

Merge changes from topic "lto-by-default" into integration

* changes:
fix(libc): make sure __init functions are garbage collected
fix(platforms): remove platform_core_pos_helper()

fix(ti): fix UNUSED_VALUE in AM62L PSCI Driver

New Defects reported by Coverity Scan found value "-6" to "ret" here,
but that stored value is overwritten before it can be used.
We'd rather just retu

fix(ti): fix UNUSED_VALUE in AM62L PSCI Driver

New Defects reported by Coverity Scan found value "-6" to "ret" here,
but that stored value is overwritten before it can be used.
We'd rather just return from those places to avoid this, similar
to how it was being done in k3_psci as well.

Change-Id: I7661586f191aad541387c06ab221c1d7cb58e461
Signed-off-by: Dhruva Gole <d-gole@ti.com>

show more ...

feat(neoverse_rd): deprecate and remove RD-V1 platform variants

deprecate and remove support for RD-V1 and RD-V1-MC platform variants.

Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id:

feat(neoverse_rd): deprecate and remove RD-V1 platform variants

deprecate and remove support for RD-V1 and RD-V1-MC platform variants.

Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: Ifab7b95e00615806986e316e0bde7788dc8af04f

show more ...

feat(neoverse_rd): deprecate and remove RD-N1-Edge platform variants

deprecate and remove support for RD-N1-Edge and RD-N1-Edgex2 platform
variants.

Signed-off-by: Rohit Mathew <rohit.mathew@arm.co

feat(neoverse_rd): deprecate and remove RD-N1-Edge platform variants

deprecate and remove support for RD-N1-Edge and RD-N1-Edgex2 platform
variants.

Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: I59dce73b70014b3416d89b0d024d7204356b1b77

show more ...

feat(neoverse_rd): deprecate and remove SGI-575 platform

deprecate and remove support for SGI-575 platform.

Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: Iffee2fa8f4faa463c4b4df5911

feat(neoverse_rd): deprecate and remove SGI-575 platform

deprecate and remove support for SGI-575 platform.

Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: Iffee2fa8f4faa463c4b4df591182f72a461c880b

show more ...

Merge "fix(juno): resolve BL2 RAM overflow with RSA+ECDSA in GCC(14.2.1)" into integration

Merge changes from topic "bk/fvp_r" into integration

* changes:
fix(tbbr): remove tbbr_cot_bl1_r64.c
fix(xlat): remove xlat_mpu

Merge changes from topic "ti-am62l-mailbox-psci-base-support" into integration

* changes:
feat(ti): introduce basic support for the AM62L
feat(ti): introduce PSCI Driver for AM62L
feat(ti): ad

Merge changes from topic "ti-am62l-mailbox-psci-base-support" into integration

* changes:
feat(ti): introduce basic support for the AM62L
feat(ti): introduce PSCI Driver for AM62L
feat(ti): add support for TI mailbox driver
refactor(ti): move out k3/common to ti/common
refactor(ti): introduce ti_bl31_setup
refactor(ti): add the sec hdr to the ti sci msg
refactor(ti): rename the k3_sec_proxy_chan_id
refactor(ti): rename the sec_proxy functions
refactor(ti): add top level ti_sci transport layer
refactor(ti): move TI SCI and sec proxy to drivers

show more ...

feat(fvp): support AArch32 booting with handoff

Enable AArch32 SP_MIN booting on the FVP platform using Firmware
Handoff. Update plat_arm_sp_min_early_platform_setup() to parse boot
arguments passed

feat(fvp): support AArch32 booting with handoff

Enable AArch32 SP_MIN booting on the FVP platform using Firmware
Handoff. Update plat_arm_sp_min_early_platform_setup() to parse boot
arguments passed via the Firmware Handoff framework.

Also, adjust the maximum BL32 size calculation to use
PLAT_ARM_FW_HANDOFF_SIZE when TRANSFER_LIST is enabled.

Change-Id: I82032b1cebf8b37ff24dde4f2d07f7aaede33eb6
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>

show more ...

feat(arm): support AArch32 booting with handoff

Configre SP-MIN to receive information via the firmare handoff
framework. In BL1 and BL2, select the 32-bit variants of the SRAM layout
and entry poin

feat(arm): support AArch32 booting with handoff

Configre SP-MIN to receive information via the firmare handoff
framework. In BL1 and BL2, select the 32-bit variants of the SRAM layout
and entry point info to enable booting in aarch32 mode. In SP-MIN
process expected data directly from the transfer list in secure memory.

Change-Id: If0417cdd4c47b772332eb6fd4b71ef0ea474f0fa
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>

show more ...

fix(xlat): remove xlat_mpu

The only platform to use this is fvp_r. As this platform is now gone, so
is the need for this library. Support for it never went out of
"experimental" so it does not appea

fix(xlat): remove xlat_mpu

The only platform to use this is fvp_r. As this platform is now gone, so
is the need for this library. Support for it never went out of
"experimental" so it does not appear to be finished.

Change-Id: I76499b92ca4368651330f17dc80803991158cc36
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

show more ...

fix(platforms): remove platform_core_pos_helper()

Its last user was removed some time ago so it is no longer necessary.

Change-Id: I28264367abd2902ed0d3f207f686538a82a44eba
Signed-off-by: Boyan Kar

fix(platforms): remove platform_core_pos_helper()

Its last user was removed some time ago so it is no longer necessary.

Change-Id: I28264367abd2902ed0d3f207f686538a82a44eba
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

show more ...

fix(versal-net): enable PSCI reset2 interface

Enable the PSCI reset2 interface for Versal NET. Since warm/soft reset
functionality is not supported in the Versal NET system, the reset2
implementatio

fix(versal-net): enable PSCI reset2 interface

Enable the PSCI reset2 interface for Versal NET. Since warm/soft reset
functionality is not supported in the Versal NET system, the reset2
implementation is aligned with the existing PSCI reset interface.

This implementation allows the external users to define
platform-specific actions for warm/soft reset within the reset2
handler if needed.

Change-Id: Ibb937e4c0994a29b45b9b19f8addad56fe7e7e23
Signed-off-by: Michal Simek <michal.simek@amd.com>
Signed-off-by: Senthil Nathan Thangaraj <senthilnathan.thangaraj@amd.com>

show more ...

Merge changes I2d140b32,Id59ae926,I31c71551 into integration

* changes:
feat(mt8189): add GPIO support
feat(mt8189): initialize platform for MT8189
refactor(mediatek): move headers to common f

Merge changes I2d140b32,Id59ae926,I31c71551 into integration

* changes:
feat(mt8189): add GPIO support
feat(mt8189): initialize platform for MT8189
refactor(mediatek): move headers to common folder

show more ...

fix(juno): resolve BL2 RAM overflow with RSA+ECDSA in GCC(14.2.1)

* Using "TF_MBEDTLS_RSA_AND_ECDSA" algorithm with toolchain 14.2.1
causes the BL2 image to exceed RAM limits, triggering a link er

fix(juno): resolve BL2 RAM overflow with RSA+ECDSA in GCC(14.2.1)

* Using "TF_MBEDTLS_RSA_AND_ECDSA" algorithm with toolchain 14.2.1
causes the BL2 image to exceed RAM limits, triggering a link error
("region `RAM' overflowed by 4096 bytes").

* Resolved by increasing PLAT_ARM_MAX_BL2_SIZE by 4KB to accommodate
the larger image.

Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
Change-Id: Ie9d411c1207801436d8cffcf72fec2752371eb69

show more ...

Merge "fix(plat): remove fvp_r" into integration

fix(trng): allow FEAT_RNG_TRAP in dynamic fashion

The documentation promises for ENABLE_FEAT_RNG_TRAP to support the
numeric semantics, with a value of "2" meaning runtime detection. However
two pla

fix(trng): allow FEAT_RNG_TRAP in dynamic fashion

The documentation promises for ENABLE_FEAT_RNG_TRAP to support the
numeric semantics, with a value of "2" meaning runtime detection. However
two places in the build system did not support this, instead were just
checking for a value of "1".

Fix the AArch32 check and build the FVP specific handler routine when
the value is not "0", instead of relying on it to be exactly "1".

Change-Id: I1acd3ed6d2a461d541b9bf57e4aac9c0798ab56b
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

show more ...

Merge "fix(arm): resolve misra rule R11.6 violation" into integration

fix(plat): remove fvp_r

The platform has not been maintained for some years and is generally
broken. Remove it to avoid confusion.

Change-Id: I93d832d51e114689ec79969af5d96071a03f4a88
Signed-off-by

fix(plat): remove fvp_r

The platform has not been maintained for some years and is generally
broken. Remove it to avoid confusion.

Change-Id: I93d832d51e114689ec79969af5d96071a03f4a88
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

show more ...

feat(ti): introduce basic support for the AM62L

The AM62L is a lite, low power and performance optimized family of
application processors that are built for Linux application development.

Some high

feat(ti): introduce basic support for the AM62L

The AM62L is a lite, low power and performance optimized family of
application processors that are built for Linux application development.

Some highlights of AM62L SoC are:
- Single to Dual 64-bit Arm® Cortex®-A53 microprocessor subsystem
- 16-bit DDR Subsystem that supports LPDDR4, DDR4 memory types.
- Multiple low power modes support, ex: Deep sleep and RTC+DDR
- Mailbox transport layer for TI SCI

For more information check out our Technical Reference Manual (TRM)
which is loacted here:

https://www.ti.com/lit/pdf/sprujb4

Change-Id: I9d7c707b5b220c5ec13bd2de67f872b3da3c308a
Signed-off-by: Dhruva Gole <d-gole@ti.com>

show more ...

feat(ti): introduce PSCI Driver for AM62L

The AM62L is a lite, low power and performance optimized family of
application processors that are built for Linux application development

There is enough

feat(ti): introduce PSCI Driver for AM62L

The AM62L is a lite, low power and performance optimized family of
application processors that are built for Linux application development

There is enough deviation from the previous K3 gen SoCs with regards to
how the PSCI functionality looks like on this device. For example, it
no longer does reset or LPSC turn ON/OFF operations using any external
Device Management entity like it did earlier.

The actual power ON/OFF operations will be implemented in a later stage
once all the PM related drivers are integrated. Such places in this
driver have been marked as TODO and will be replaced with actual call
to power on/off the cores at a later point.

This warranted the addition of a new am62l_psci driver for the AM62L
family of devices. For further details of how this new device looks
like, refer to the TRM [1].

[1] https://www.ti.com/lit/pdf/sprujb4

Change-Id: Ic53096e7bbc25fa55386ac4b6bef364dd6d0cf3b
Signed-off-by: Dhruva Gole <d-gole@ti.com>

show more ...

refactor(ti): move out k3/common to ti/common

This will allow us to support more platforms that share commonalities
like the k3_gicv3, console, helpers, etc.
With this new common folder location, we

refactor(ti): move out k3/common to ti/common

This will allow us to support more platforms that share commonalities
like the k3_gicv3, console, helpers, etc.
With this new common folder location, we can move the previously
created ti_bl31_setup file into the new location so it can be shared
across multiple TI SoCs when need comes.
With this, also update all copyright dates.

Change-Id: Ie4365e32cd3b4b5870fe2cd03843400506e46265
Signed-off-by: Dhruva Gole <d-gole@ti.com>

show more ...

feat(mt8189): add GPIO support

- Add GPIO support for MT8189.

Change-Id: I2d140b32eef8c05aba9170bf4af894ed43d52978
Signed-off-by: Cathy Xu <ot_cathy.xu@mediatek.com>