Merge "feat(intel): provide atf build version via smc call" into integration

Merge "fix(intel): this patch is used to solve DDR and VAB" into integration

Merge "feat(rmmd): add FEAT_MEC support" into integration

Merge "fix(xilinx): avoid unexpected variable update" into integration

feat(rmmd): add FEAT_MEC support

This patch provides architectural support for further use of
Memory Encryption Contexts (MEC) by declaring the necessary
registers, bits, masks, helpers and values a

feat(rmmd): add FEAT_MEC support

This patch provides architectural support for further use of
Memory Encryption Contexts (MEC) by declaring the necessary
registers, bits, masks, helpers and values and modifying the
necessary registers to enable FEAT_MEC.

Signed-off-by: Tushar Khandelwal <tushar.khandelwal@arm.com>
Signed-off-by: Juan Pablo Conde <juanpablo.conde@arm.com>
Change-Id: I670dbfcef46e131dcbf3a0b927467ebf6f438fa4

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Merge "build(poetry): install dependencies with `--no-root`" into integration

build(poetry): install dependencies with `--no-root`

More recent versions of Poetry introduced the `package-mode` key to
configure whether the project should be used for dependency management
only,

build(poetry): install dependencies with `--no-root`

More recent versions of Poetry introduced the `package-mode` key to
configure whether the project should be used for dependency management
only, but this is incompatible with the earlier versions of Poetry that
we still support.

Instead, we rely on installing with the `--no-root` flag, which behaves
similarly. Installing without passing the `--no-root` flag is
deprecated, and in recent versions of Poetry has become a hard error.

This change ensures that the build system always installs dependencies
with the required flag.

Change-Id: Ic1543511314dcd20c00b73fd9e8cfae3dd034a41
Signed-off-by: Chris Kay <chris.kay@arm.com>

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fix(intel): this patch is used to solve DDR and VAB

The patch provide solutions for:
1. Enable BL31 console logs during run-time.
2. Update VAB initialization.
3. Update DDR size accordin to Linux D

fix(intel): this patch is used to solve DDR and VAB

The patch provide solutions for:
1. Enable BL31 console logs during run-time.
2. Update VAB initialization.
3. Update DDR size accordin to Linux DTS configuration.
4. Solve VAB CCERT address issue.

Change-Id: I41eb0fab747de5010d369e845c33a45decb41e21
Signed-off-by: Jit Loon Lim <jit.loon.lim@altera.com>

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feat(intel): provide atf build version via smc call

This patch provides ATF build version via SMC call
on Agilex7, Agilex5, Stratix10 and N5X platforms.

Change-Id: I61af83433fe61f85987f38ffc86380a4

feat(intel): provide atf build version via smc call

This patch provides ATF build version via SMC call
on Agilex7, Agilex5, Stratix10 and N5X platforms.

Change-Id: I61af83433fe61f85987f38ffc86380a41cdb5289
Signed-off-by: Girisha Dengi <girisha.dengi@intel.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@altera.com>

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fix(platforms): modify function to have single return

This corrects the MISRA violation C2012-15.5:
A function should have a single point of exit at the end.
Introduced a temporary variable to store

fix(platforms): modify function to have single return

This corrects the MISRA violation C2012-15.5:
A function should have a single point of exit at the end.
Introduced a temporary variable to store the return value to
ensure single return for the function.

Change-Id: I9c2ca05b506a6ac35b24966fc5fdd5e88e65770d
Signed-off-by: Nithin G <nithing@amd.com>
Signed-off-by: Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>

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fix(platforms): add missing curly braces

This corrects the MISRA violation C2012-15.6:
The body of an iteration-statement or a selection-statement shall
be a compound-statement.
Enclosed statement b

fix(platforms): add missing curly braces

This corrects the MISRA violation C2012-15.6:
The body of an iteration-statement or a selection-statement shall
be a compound-statement.
Enclosed statement body within the curly braces.

Change-Id: I1327a206782ccd341c0c7eaa3f26078150458ed0
Signed-off-by: Nithin G <nithing@amd.com>
Signed-off-by: Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>

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fix(xilinx): avoid unexpected variable update

The commit 50ab13577fd5 ("fix(xilinx): typecast expression to match
data type") introduced a change where the isenabler1 variable is
modified within the

fix(xilinx): avoid unexpected variable update

The commit 50ab13577fd5 ("fix(xilinx): typecast expression to match
data type") introduced a change where the isenabler1 variable is
modified within the loop iterating over GICD_ISENABLER registers.
Instead of computing the offset from the base address for each
register, the offset is accumulated incorrectly, leading to an
incorrect register read.

As a result, some GIC enablers, including the RTC device were missed,
so pm_set_wakeup_source was not called for them and the
suspend-resume use case was failed because of that.

Fix the logic to ensure the correct offset calculation for each
iteration, preserving the intended behavior.

Fixes: 50ab13577fd5 fix(xilinx): typecast expression to match data type
Change-Id: Iec5bafcbde21078545a37259b2cf0353585ef1fa
Signed-off-by: Madhav Bhatt <madhav.bhatt@amd.com>
Signed-off-by: Ronak Jain <ronak.jain@amd.com>

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Merge "feat(spm_mm): move mm_communication header define to general header" into integration

fix(imx8mp): apply ERRATA_A53_1530924 erratum

Apply erratum ERRATA_A53_1530924.

Change-Id: I971bb75bd0bda05f823599919a6936b61a2509ca
Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>

feat(fvp): increase cactus-tertiary size

Increase the size of cactus-tertiary partition to match update in
manifest. Part of effort to use cactus-tertiary partition in StMM/HOB
testing.

Dependent o

feat(fvp): increase cactus-tertiary size

Increase the size of cactus-tertiary partition to match update in
manifest. Part of effort to use cactus-tertiary partition in StMM/HOB
testing.

Dependent on
https://review.trustedfirmware.org/c/TF-A/tf-a-tests/+/35383

Signed-off-by: Kathleen Capella <kathleen.capella@arm.com>
Signed-off-by: J-Alves <joao.alves@arm.com>
Change-Id: I5b91400848e2cf5d04d1c7442874a7a4b9847399

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Merge changes I0396b597,I326f920f,I0437eec8,Ieadf01fc,I4e1d8c24, ... into integration

* changes:
feat(fvp): set defaults for build commandline
docs(arm): enable Linux boot from fip as BL33
fea

Merge changes I0396b597,I326f920f,I0437eec8,Ieadf01fc,I4e1d8c24, ... into integration

* changes:
feat(fvp): set defaults for build commandline
docs(arm): enable Linux boot from fip as BL33
feat(arm): enable Linux boot from fip as BL33
docs(fvp): update fvp build time options
docs(arm): add initrd props to dtb at build time
feat(arm): add initrd props to dtb at build time

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feat(zynqmp): add pin group for lower qspi interface

ZynqMP provides two QSPI interfaces on MIO[0..12],
but the existing pin group definitions only allow
all or none of the pins to be configured for

feat(zynqmp): add pin group for lower qspi interface

ZynqMP provides two QSPI interfaces on MIO[0..12],
but the existing pin group definitions only allow
all or none of the pins to be configured for QSPI.

This is an issue on platforms that use only the lower
QSPI interface and require the remaining pins to be
configured for other purposes such as general I/O.

Add pin groups to support QSPI on MIO[0..4] with SS
(slave select) on MIO5, freeing up MIO[7..12] for
other uses.

The new pin groups can be accessed from Linux as
'qspi0_1_grp' and 'qspi_ss_1_grp'.

Change-Id: Ibdb3f13d4ba9194a3be8ce5e63478d9066d087ac
Signed-off-by: Carsten Hansen <Carsten.Hansen@bksv.com>
Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com>

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feat(fvp): set defaults for build commandline

When using ARM_LINUX_KERNEL_AS_BL33, set defaults for the below for
increased build time efficiency:

PRELOADED_BL33_BASE=0x80080000
This address suppor

feat(fvp): set defaults for build commandline

When using ARM_LINUX_KERNEL_AS_BL33, set defaults for the below for
increased build time efficiency:

PRELOADED_BL33_BASE=0x80080000
This address supports older kernels before v5.7

ARM_PRELOADED_DTB_BASE=0x87F00000 (only in RESET_TO_BL31)
1MiB before the address 0x88000000 in FVP. 1MiB seems enough for the
device tree blob (DTB).

Change-Id: I0396b597485e163b43f7c6677c04fcc08db55aa8
Signed-off-by: Salman Nabi <salman.nabi@arm.com>

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feat(arm): enable Linux boot from fip as BL33

Disable the reliance of ARM_LINUX_KERNEL_AS_BL33 on PRELOADED_BL33_BASE
so that a Linux Kernel can be loaded and booted from the fip as BL33.

Change-Id

feat(arm): enable Linux boot from fip as BL33

Disable the reliance of ARM_LINUX_KERNEL_AS_BL33 on PRELOADED_BL33_BASE
so that a Linux Kernel can be loaded and booted from the fip as BL33.

Change-Id: I0437eec852cf17e0ed37a7ff77fcc4e66b1cea7a
Signed-off-by: Salman Nabi <salman.nabi@arm.com>

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feat(arm): add initrd props to dtb at build time

Add initrd properties to the device tree blob at build time, giving
users the ability to run a linux kernel and successfully boot it to
the terminal.

feat(arm): add initrd props to dtb at build time

Add initrd properties to the device tree blob at build time, giving
users the ability to run a linux kernel and successfully boot it to
the terminal. Users can boot a linux kernel in a normal flow as well
as in RESET_TO_BL31. This function is an extension of the build time
option "ARM_LINUX_KERNEL_AS_BL33=1".

The build time options INITRD_SIZE or INITRD_PATH will trigger the
insertion of initrd properties in to the DTB. If both options are
provided then the INITRD_SIZE will take precedence.

The available options are:
INITRD_SIZE: Provide the initrd size in dec or hex (hex format must
precede with '0x'.
Example: INITRD_SIZE=0x1000000

INITRD_PATH: Provide an initrd path for the build time to find its
exact size.

INITRD_BASE: A required build time option that sets the initrd base
address in hex format. A default value can be set by the platform.
Example: INITRD_BASE=0x90000000

Change-Id: Ief8de5f00c453509bcc6e978e0a95d768f1f509c
Signed-off-by: Salman Nabi <salman.nabi@arm.com>

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Merge "feat(mt8196): fix MT8196 gpio driver" into integration

fix(el3-runtime): replace CTX_ESR_EL3 with CTX_DOUBLE_FAULT_ESR

ESR_EL3 value is updated when an exception is taken to EL3 and its value
does not change until a new exception is taken to EL3. We nee

fix(el3-runtime): replace CTX_ESR_EL3 with CTX_DOUBLE_FAULT_ESR

ESR_EL3 value is updated when an exception is taken to EL3 and its value
does not change until a new exception is taken to EL3. We need to save
ESR in context memory only when we expect nested exception in EL3.

The scenarios where we would expect nested EL3 execution are related
with FFH_SUPPORT, namely
1.Handling pending async EAs at EL3 boundry
- It uses CTX_SAVED_ESR_EL3 to preserve origins esr_el3
2.Double fault handling
- Introduce an explicit storage (CTX_DOUBLE_FAULT_ESR) for esr_el3
to take care of DobuleFault.

As the ESR context has been removed, read the register directly instead
of its context value in RD platform.

Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: I7720c5f03903f894a77413a235e3cc05c86f9c17

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Merge changes from topic "mb/drtm" into integration

* changes:
feat(drtm): retrieve DLME image authentication features
feat(drtm): log No-Action Event in Event Log for DRTM measurements
feat(f

Merge changes from topic "mb/drtm" into integration

* changes:
feat(drtm): retrieve DLME image authentication features
feat(drtm): log No-Action Event in Event Log for DRTM measurements
feat(fvp): add stub function to retrieve DLME image auth features
feat(drtm): introduce plat API for DLME authentication features
feat(drtm): ensure event types aligns with DRTM specification v1.1
fix(drtm): add missing DLME data regions for min size requirement
feat(fvp): add stub platform function to get ACPI table region size
feat(drtm): add platform API to retrieve ACPI tables region size

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Merge changes from topic "gr/build_fix_spmd" into integration

* changes:
fix(rdv3): handle invalid build combination
fix(build): handle invalid spd build options

Merge changes I5aabe415,Ief6fb4fc into integration

* changes:
feat(stm32mp15-fdts): add SP_MIN versions of DT files
feat(st): use dedicated version of DT for SP_MIN