1 /* 2 * Copyright (c) 2022, Xilinx, Inc. All rights reserved. 3 * Copyright (c) 2022-2025, Advanced Micro Devices, Inc. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /* Versal Gen 2 IPI management enums and defines */ 9 10 #ifndef PLAT_IPI_H 11 #define PLAT_IPI_H 12 13 #include <stdint.h> 14 #include <lib/utils_def.h> 15 16 #include <ipi.h> 17 18 /********************************************************************* 19 * IPI agent IDs macros 20 ********************************************************************/ 21 #define IPI_ID_PMC 1U 22 #define IPI_ID_APU 2U 23 #define IPI_ID_RPU0 3U 24 #define IPI_ID_RPU1 4U 25 #define IPI_ID_3 5U 26 #define IPI_ID_4 6U 27 #define IPI_ID_5 7U 28 #define IPI_ID_MAX 8U 29 30 /********************************************************************* 31 * IPI message buffers 32 ********************************************************************/ 33 #define IPI_BUFFER_BASEADDR (0xEB3F0000U) 34 35 #define IPI_LOCAL_ID IPI_ID_APU 36 #define IPI_REMOTE_ID IPI_ID_PMC 37 38 #define IPI_BUFFER_LOCAL_BASE (IPI_BUFFER_BASEADDR + (IPI_LOCAL_ID * 0x200U)) 39 #define IPI_BUFFER_REMOTE_BASE (IPI_BUFFER_BASEADDR + (IPI_REMOTE_ID * 0x200U)) 40 41 #define IPI_BUFFER_TARGET_LOCAL_OFFSET (IPI_LOCAL_ID * 0x40U) 42 #define IPI_BUFFER_TARGET_REMOTE_OFFSET (IPI_REMOTE_ID * 0x40U) 43 44 #define IPI_BUFFER_MAX_WORDS 8 45 46 #define IPI_BUFFER_REQ_OFFSET 0x0U 47 #define IPI_BUFFER_RESP_OFFSET 0x20U 48 49 /********************************************************************* 50 * Platform specific IPI API declarations 51 ********************************************************************/ 52 53 /* Configure IPI table */ 54 extern void soc_ipi_config_table_init(void); 55 56 /******************************************************************************* 57 * IPI registers and bitfields 58 ******************************************************************************/ 59 #define IPI0_REG_BASE (0xEB330000U) 60 #define IPI0_TRIG_BIT BIT_32(2) 61 #define PMC_IPI_TRIG_BIT BIT_32(1) 62 #define IPI1_REG_BASE (0xEB340000U) 63 #define IPI1_TRIG_BIT BIT_32(3) 64 #define IPI2_REG_BASE (0xEB350000U) 65 #define IPI2_TRIG_BIT BIT_32(4) 66 #define IPI3_REG_BASE (0xEB360000U) 67 #define IPI3_TRIG_BIT BIT_32(5) 68 #define IPI4_REG_BASE (0xEB370000U) 69 #define IPI4_TRIG_BIT BIT_32(6) 70 #define IPI5_REG_BASE (0xEB380000U) 71 #define IPI5_TRIG_BIT BIT_32(7) 72 73 #endif /* PLAT_IPI_H */ 74