Fix PSCI STAT time stamp collection

This patch includes various fixes for PSCI STAT functionality
relating to timestamp collection:

1. The PSCI stat accounting for retention states for higher level

Fix PSCI STAT time stamp collection

This patch includes various fixes for PSCI STAT functionality
relating to timestamp collection:

1. The PSCI stat accounting for retention states for higher level
power domains were done outside the locks which could lead to
spurious values in some race conditions. This is moved inside
the locks. Also, the call to start the stat accounting was redundant
which is now removed.

2. The timestamp wrap-around case when calculating residency did
not cater for AArch32. This is now fixed.

3. In the warm boot path, `plat_psci_stat_accounting_stop()` was
getting invoked prior to population of target power states. This
is now corrected.

Change-Id: I851526455304fb74ff0a724f4d5318cd89e19589
Signed-off-by: Soby Mathew <soby.mathew@arm.com>

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Merge pull request #1137 from soby-mathew/sm/arm_plat_en_gicv3_save

Enable GICv3 save for ARM platforms

qemu: update deprecated interrupt registering

Registered interrupts are configured in edge detection as the default
previous configuration assumed in previous code.

Not target mask required as Qemu

qemu: update deprecated interrupt registering

Registered interrupts are configured in edge detection as the default
previous configuration assumed in previous code.

Not target mask required as Qemu BL31 will not send/route SGIs.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>

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Fix usage of IMAGE_BLx macros

These macros are only defined for corresponding image,
and they are undefined for other images. It means that we have
to use ifdef or defined() instead of relying on be

Fix usage of IMAGE_BLx macros

These macros are only defined for corresponding image,
and they are undefined for other images. It means that we have
to use ifdef or defined() instead of relying on being 0 by default.

Change-Id: Iad11efab9830ddf471599b46286e1c56581ef5a7
Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>

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Always define ARM_TSP_RAM_LOCATION_ID

ARM_TSP_RAM_LOCATION_ID was defined only in AARCH64, but the macro
was also used in AARCH32, and it meant that it was taking the value 0,
which happened to equa

Always define ARM_TSP_RAM_LOCATION_ID

ARM_TSP_RAM_LOCATION_ID was defined only in AARCH64, but the macro
was also used in AARCH32, and it meant that it was taking the value 0,
which happened to equal ARM_TRUSTED_SRAM_ID.

Change-Id: If9f4dbee1a2ba15e7806f2a03305b554bd327363
Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>

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Merge pull request #1141 from robertovargas-arm/boot_redundancy

Add platform hooks for boot redundancy support

Merge pull request #1144 from geesun/qx/resize_bl2_size

Change the default option of ARM_TSP_RAM_LOCATION and Enlarge the BL2 size on ARM platforms

Merge pull request #1147 from etienne-lms/qemu-optee-load

qemu/optee: load OP-TEE pageable part 2MB above OP-TEE image

Merge pull request #1143 from etienne-lms/qemu-hpen

qemu: fix holding pen mailbox sequence

qemu/optee: load OP-TEE pageable part 2MB above OP-TEE image

OP-TEE dedicates the end of the Qemu secure DRAM as specific out-of-TEE
secure RAM. To support this configuration the trusted firmware sh

qemu/optee: load OP-TEE pageable part 2MB above OP-TEE image

OP-TEE dedicates the end of the Qemu secure DRAM as specific out-of-TEE
secure RAM. To support this configuration the trusted firmware should
not load OP-TEE resources in this area.

To overcome the issue, OP-TEE pageable image is now loaded 2MByte above
the secure RAM base address.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>

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Merge pull request #1138 from michpappas/tf-issues#526_qemu_does_not_support_TBB

qemu: Add support for Trusted Board Boot

qemu: Add support for Trusted Board Boot

This patch adds support for TBB to qemu. An RSA ROT keypair is generated at
build time and is included into BL1/BL2. The key and content certificates
are rea

qemu: Add support for Trusted Board Boot

This patch adds support for TBB to qemu. An RSA ROT keypair is generated at
build time and is included into BL1/BL2. The key and content certificates
are read over semihosting.

Fixes ARM-software/tf-issues#526

Signed-off-by: Michalis Pappas <mpappas@fastmail.fm>

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plat/arm: enlarge the BL2 size on Arm platforms when TBB is enabled

For Trusted Board Boot, BL2 needs more space to support the ECDSA
and ECDSA+RSA algorithms.

Change-Id: Ie7eda9a1315ce836dbc6d18d6

plat/arm: enlarge the BL2 size on Arm platforms when TBB is enabled

For Trusted Board Boot, BL2 needs more space to support the ECDSA
and ECDSA+RSA algorithms.

Change-Id: Ie7eda9a1315ce836dbc6d18d6588f8d17891a92d
Signed-off-by: Qixiang Xu <qixiang.xu@arm.com>

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plat/arm: change the default option of ARM_TSP_RAM_LOCATION

On Arm standard platforms, it runs out of SRAM space when TBB is
enabled, so the TSP default location is changed to dram when TBB
is enabl

plat/arm: change the default option of ARM_TSP_RAM_LOCATION

On Arm standard platforms, it runs out of SRAM space when TBB is
enabled, so the TSP default location is changed to dram when TBB
is enabled.

Change-Id: I516687013ad436ef454d2055d4e6fce06e467044
Signed-off-by: Qixiang Xu <qixiang.xu@arm.com>

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Add platform hooks for boot redundancy support

These hooks are intended to allow one platform to try load
images from alternative places. There is a hook to initialize
the sequence of boot locations

Add platform hooks for boot redundancy support

These hooks are intended to allow one platform to try load
images from alternative places. There is a hook to initialize
the sequence of boot locations and a hook to pass to the next
sequence.

Change-Id: Ia0f84c415208dc4fa4f9d060d58476db23efa5b2
Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>

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qemu: fix holding pen mailbox sequence

Before this change, plat_secondary_cold_boot_setup reads wake up mailbox
as a byte array but through 64bit accesses on unaligned 64bit addresses.
In the other

qemu: fix holding pen mailbox sequence

Before this change, plat_secondary_cold_boot_setup reads wake up mailbox
as a byte array but through 64bit accesses on unaligned 64bit addresses.
In the other hand qemu_pwr_domain_on wakes secondary cores by writing
into a 64bit array.

This change forces the 64bit mailbox format as PLAT_QEMU_HOLD_ENTRY_SIZE
explicitly specifies it.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>

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Merge pull request #1139 from hzhuang1/fix_edmac

Fix edmac

Merge pull request #1131 from jeenu-arm/gic-migrate

Migrate upstream platforms to using interrupt properties

Merge pull request #1130 from jeenu-arm/gic-patches

New GIC APIs and specifying interrupt propertes

uniphier: move ROTPK hash to .rodata section

This is not executable code. It should be put into .rodata instead
of .text section.

This produces more correct BL1 image when SEPARATE_CODE_AND_RODATA

uniphier: move ROTPK hash to .rodata section

This is not executable code. It should be put into .rodata instead
of .text section.

This produces more correct BL1 image when SEPARATE_CODE_AND_RODATA is
defined.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

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HiKey: make RTC out of reset mode

Make RTC out of reset mode since it may be used in UEFI.

Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>

HiKey: init EDMA controller with non secure mode

Init EDMA controller with non secure mode. A lot of peripherals are
depend on EDMA controller. But EDMA controller is in secure mode
by default. And

HiKey: init EDMA controller with non secure mode

Init EDMA controller with non secure mode. A lot of peripherals are
depend on EDMA controller. But EDMA controller is in secure mode
by default. And this operation has to be executed in secure mode.

Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>

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zynqmp: Migrate to using interrupt properties

Change-Id: Ia8503d446cc8b4246013046f6294fea364c9c882
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>

mt8173: Migrate to using interrupt properties

Change-Id: I1463a4f9b74d74d59ac1d37b7b9c8e53416ab904
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>

poplar: Migrate to using interrupt properties

Change-Id: Ibca6ea29be32783de666e0e0a0481668fc11860f
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>