zynqmp: pm: Support ATF PM version check

Add SMC call to query ATF PM version. This version
can be used by Linux to match with expected version.

Signed-off-by: Rajan Vaja <rajanv@xilinx.com>

zynqmp: pm: Update API version to 1.0

With new EEMI APIs addition, version is updated to 1.0

Signed-off-by: Jolly Shah <jollys@xilinx.com>

zynqmp: Use DDR memory when DEBUG is enabled

Define default DDR location to which ATF has to compiled
if DEBUG option is enabled. This is required now, as the ATF cant fit
in OCM with DEBUG option e

zynqmp: Use DDR memory when DEBUG is enabled

Define default DDR location to which ATF has to compiled
if DEBUG option is enabled. This is required now, as the ATF cant fit
in OCM with DEBUG option enabled. The default value is 0x1000 and can be
used till 0x7ffff. User can still override as per wish/requirement
using current commandline options.

Signed-off-by: Jolly Shah <jollys@xilinx.com>

show more ...

zynqmp: pm: Add APIs for pin control queries

Add pin control APIs which driver can use to query
pin information from firmware. Using these APIs,
driver do not need to maintain hard-coded pin databas

zynqmp: pm: Add APIs for pin control queries

Add pin control APIs which driver can use to query
pin information from firmware. Using these APIs,
driver do not need to maintain hard-coded pin database.

Major changes in patch are:
- Add pin database with pins, functions and function groups
information
- Implement APIs for pin information queries
- Update pin control APIs for get/set functions to use new
pin control database. Remove pin database which was added
earlier.

Signed-off-by: Rajan Vaja <rajanv@xilinx.com>
Signed-off-by: Jolly Shah <jollys@xilinx.com>

show more ...

zynqmp: pm: Add IOCTLs for global storage access

Add IOCTLs to read/write global general storage and
persistent global general storage registers access.

Signed-off-by: Rajan Vaja <rajanv@xilinx.com

zynqmp: pm: Add IOCTLs for global storage access

Add IOCTLs to read/write global general storage and
persistent global general storage registers access.

Signed-off-by: Rajan Vaja <rajanv@xilinx.com>
Signed-off-by: Jolly Shah <jollys@xilinx.com>

show more ...

zynqmp: pm: Implement clock APIs

- Add clock entries and information to clock database.
- Implement APIs to provide clock topology and other
information to caller.
- Implement APIs to control cloc

zynqmp: pm: Implement clock APIs

- Add clock entries and information to clock database.
- Implement APIs to provide clock topology and other
information to caller.
- Implement APIs to control clocks and PLLs.

Signed-off-by: Rajan Vaja <rajanv@xilinx.com>
Signed-off-by: Jolly Shah <jollys@xilinx.com>

show more ...

zynqmp: pm: Add clock control EEMI API and ioctl functions

These are empty functions with no logic right now. Code
will be added in subsequent commits.

Signed-off-by: Rajan Vaja <rajanv@xilinx.com>

zynqmp: pm: Add clock control EEMI API and ioctl functions

These are empty functions with no logic right now. Code
will be added in subsequent commits.

Signed-off-by: Rajan Vaja <rajanv@xilinx.com>
Signed-off-by: Jolly Shah <jollys@xilinx.com>

show more ...

zynqmp: pm: Implement IOCTL APIs for device control

Implement ioctl APIs which uses MMIO operations
to configure devices. Below IOCTLs are supported
in this patch:
* Set tap delay bypass
* Set S

zynqmp: pm: Implement IOCTL APIs for device control

Implement ioctl APIs which uses MMIO operations
to configure devices. Below IOCTLs are supported
in this patch:
* Set tap delay bypass
* Set SGMII mode
* SD reset
* Set SD/MMC tap delay

Signed-off-by: Rajan Vaja <rajanv@xilinx.com>
Signed-off-by: Jolly Shah <jollys@xilinx.com>

show more ...

zynqmp: pm: Implement IOCTL APIs for remoteproc

Implement ioctl APIs which uses MMIO operations
to control RPU operations. Below IOCTLs are supported
in this patch:
* Get RPU operation mode
* Se

zynqmp: pm: Implement IOCTL APIs for remoteproc

Implement ioctl APIs which uses MMIO operations
to control RPU operations. Below IOCTLs are supported
in this patch:
* Get RPU operation mode
* Set RPU operation mode
* Configure RPU boot address (OCM/TCM)
* Configure TCM combined mode

Signed-off-by: Rajan Vaja <rajanv@xilinx.com>
Signed-off-by: Jolly Shah <jollys@xilinx.com>

show more ...

zynqmp: pm: Implement pin control APIs for configurations

Implement pin control APIs which uses MMIO operations
to set/get values of configuration parameters.

Signed-off-by: Rajan Vaja <rajanv@xili

zynqmp: pm: Implement pin control APIs for configurations

Implement pin control APIs which uses MMIO operations
to set/get values of configuration parameters.

Signed-off-by: Rajan Vaja <rajanv@xilinx.com>
Signed-off-by: Jolly Shah <jollys@xilinx.com>

show more ...

zynqmp: pm: Implement pin control APIs for get/set functions

Implement pin control APIs which uses MMIO operations
to set/get functions for the given pin.

Signed-off-by: Rajan Vaja <rajanv@xilinx.c

zynqmp: pm: Implement pin control APIs for get/set functions

Implement pin control APIs which uses MMIO operations
to set/get functions for the given pin.

Signed-off-by: Rajan Vaja <rajanv@xilinx.com>
Signed-off-by: Jolly Shah <jollys@xilinx.com>

show more ...

zynqmp: pm: Add wrappers for Pin control APIs

Add wrappers for pin control APIs. Actual implementation of
these APIs would be done in subsequent changes.

Signed-off-by: Rajan Vaja <rajanv@xilinx.co

zynqmp: pm: Add wrappers for Pin control APIs

Add wrappers for pin control APIs. Actual implementation of
these APIs would be done in subsequent changes.

Signed-off-by: Rajan Vaja <rajanv@xilinx.com>
Signed-off-by: Jolly Shah <jollys@xilinx.com>

show more ...

zynqmp: Add new function and node IDs

Add new function and node IDs supported by PMUFW in
function list and node list respectively.

Signed-off-by: Rajan Vaja <rajanv@xilinx.com>
Signed-off-by: Joll

zynqmp: Add new function and node IDs

Add new function and node IDs supported by PMUFW in
function list and node list respectively.

Signed-off-by: Rajan Vaja <rajanv@xilinx.com>
Signed-off-by: Jolly Shah <jollys@xilinx.com>

show more ...

FVP AArch32: Fix flash access in BL32 for mem_protect

The FVP platform port for SP_MIN (BL32) didn't map the flash memory
in BL32 for stroring the mem_protect enable state information leading
to syn

FVP AArch32: Fix flash access in BL32 for mem_protect

The FVP platform port for SP_MIN (BL32) didn't map the flash memory
in BL32 for stroring the mem_protect enable state information leading
to synchronous exception. The patch fixes it by adding the region to
the BL32 mmap tables.

Change-Id: I37eec83c3e1ea43d1b5504d3683eebc32a57eadf
Signed-off-by: Joel Hutton <Joel.Hutton@Arm.com>

show more ...

plat/hikey: boot memory layout to dedicated file

Boot memory layout is specific for a platform, but should not be
mixed up with other platform specific attributes. A separate file is
much cleaner an

plat/hikey: boot memory layout to dedicated file

Boot memory layout is specific for a platform, but should not be
mixed up with other platform specific attributes. A separate file is
much cleaner and better to compare with other platforms. Take a look
at plat/poplar where it is done the same way.

Moved hikey_def.h to system include folder and moved includes from
hikey_def.h to more general platform_def.h.

Signed-off-by: Michael Brandl <git@fineon.pw>

show more ...

Merge pull request #1303 from soby-mathew/sm/fix_juno_fwu

Juno: Fixes for firmware update

tegra: Use SPDX license identifier

Change-Id: I770b2db68c8d115d10067bb557e32b5e269c94a5
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

Merge pull request #1277 from hzhuang1/testing/bl2_el3_v0.6

hikey: migrate to BL2_EL3

Juno: Change the Firmware update detect mechanism

Previously, Juno used to depend on the SSC_GPRETN register to inform
about the reset syndrome. This method was removed when SCP migrated
to the SDS

Juno: Change the Firmware update detect mechanism

Previously, Juno used to depend on the SSC_GPRETN register to inform
about the reset syndrome. This method was removed when SCP migrated
to the SDS framework. But even the SDS framework doesn't report the
reset syndrome correctly and hence Juno failed to enter Firmware
update mode if BL2 authentication failed.

In addition to that, the error code populated in V2M_SYS_NVFLAGS register
does not seem to be retained any more on Juno across resets. This could
be down to the motherboard firmware not doing the necessary to preserve
the value.

Hence this patch modifies the Juno platform to use the same mechanism to
trigger firmware update as FVP which is to corrupt the FIP TOC on
authentication failure. The implementation in `fvp_err.c` is made common
for ARM platforms and is moved to the new `arm_err.c` file in
plat/arm/common folder. The BL1 and BL2 mmap table entries for Juno
are modified to allow write to the Flash memory address.

Change-Id: Ica7d49a3e8a46a90efd4cf340f19fda3b549e945
Signed-off-by: Soby Mathew <soby.mathew@arm.com>

show more ...

Merge pull request #1302 from hzhuang1/fix_build

Fix build with clang on hikey

BL2U: Fix ARM platform timer initilization

This issue was detected when testing FWU on Juno. The Timer
`timer_ops` was not being initialized before being used by
the SDS driver on Juno. This patch a

BL2U: Fix ARM platform timer initilization

This issue was detected when testing FWU on Juno. The Timer
`timer_ops` was not being initialized before being used by
the SDS driver on Juno. This patch adds the call to
`generic_delay_timer_init()` during bl2u_early_platform_setup().
This is done generically for all ARM platforms because the
cost involved is minimal.

Change-Id: I349cf0bd1db68406eb2298b65f9c729f792cabdc
Signed-off-by: Soby Mathew <soby.mathew@arm.com>

show more ...

Merge pull request #1239 from arve-android/trusty-fixes

Trusty fixes

hikey: fix build issue with CLANG

plat/hisilicon/hikey/hikey_bl1_setup.c:565:47:
error: value size does not match register size specified by the
constraint and modifier [-Werror,-Wasm-operand-widths

hikey: fix build issue with CLANG

plat/hisilicon/hikey/hikey_bl1_setup.c:565:47:
error: value size does not match register size specified by the
constraint and modifier [-Werror,-Wasm-operand-widths]
__asm__ volatile ("mrs %0, cpacr_el1" : "=r"(data));

Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>

show more ...

hikey960: fix build issue with CLANG

plat/hisilicon/hikey960/drivers/pwrc/hisi_pwrc.c:290:20:
error: unused function 'hisi_pdc_set_intmask' [-Werror,-Wunused-function]
static inline void hisi_pdc_se

hikey960: fix build issue with CLANG

plat/hisilicon/hikey960/drivers/pwrc/hisi_pwrc.c:290:20:
error: unused function 'hisi_pdc_set_intmask' [-Werror,-Wunused-function]
static inline void hisi_pdc_set_intmask(void *pdc_base_addr,
^
1 error generated.
Makefile:605: recipe for target 'build/hikey960/release/bl31/hisi_pwrc.o' failed
make: *** [build/hikey960/release/bl31/hisi_pwrc.o] Error 1

Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>

show more ...

Merge pull request #1288 from michpappas/tf-issues#558_qemu_separate_code_and_data

qemu: Support SEPARATE_CODE_AND_RODATA