1/* 2 * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <context.h> 10#include <cpu_data.h> 11#include <ea_handle.h> 12#include <interrupt_mgmt.h> 13#include <platform_def.h> 14#include <runtime_svc.h> 15#include <smccc.h> 16 17 .globl runtime_exceptions 18 19 .globl sync_exception_sp_el0 20 .globl irq_sp_el0 21 .globl fiq_sp_el0 22 .globl serror_sp_el0 23 24 .globl sync_exception_sp_elx 25 .globl irq_sp_elx 26 .globl fiq_sp_elx 27 .globl serror_sp_elx 28 29 .globl sync_exception_aarch64 30 .globl irq_aarch64 31 .globl fiq_aarch64 32 .globl serror_aarch64 33 34 .globl sync_exception_aarch32 35 .globl irq_aarch32 36 .globl fiq_aarch32 37 .globl serror_aarch32 38 39 /* 40 * Handle External Abort by delegating to the platform's EA handler. 41 * Once the platform handler returns, the macro exits EL3 and returns to 42 * where the abort was taken from. 43 * 44 * This macro assumes that x30 is available for use. 45 * 46 * 'abort_type' is a constant passed to the platform handler, indicating 47 * the cause of the External Abort. 48 */ 49 .macro handle_ea abort_type 50 /* Save GP registers */ 51 bl save_gp_registers 52 53 /* Setup exception class and syndrome arguments for platform handler */ 54 mov x0, \abort_type 55 mrs x1, esr_el3 56 adr x30, el3_exit 57 b delegate_ea 58 .endm 59 60 /* --------------------------------------------------------------------- 61 * This macro handles Synchronous exceptions. 62 * Only SMC exceptions are supported. 63 * --------------------------------------------------------------------- 64 */ 65 .macro handle_sync_exception 66 /* Enable the SError interrupt */ 67 msr daifclr, #DAIF_ABT_BIT 68 69 str x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR] 70 71#if ENABLE_RUNTIME_INSTRUMENTATION 72 /* 73 * Read the timestamp value and store it in per-cpu data. The value 74 * will be extracted from per-cpu data by the C level SMC handler and 75 * saved to the PMF timestamp region. 76 */ 77 mrs x30, cntpct_el0 78 str x29, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X29] 79 mrs x29, tpidr_el3 80 str x30, [x29, #CPU_DATA_PMF_TS0_OFFSET] 81 ldr x29, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X29] 82#endif 83 84 mrs x30, esr_el3 85 ubfx x30, x30, #ESR_EC_SHIFT, #ESR_EC_LENGTH 86 87 /* Handle SMC exceptions separately from other synchronous exceptions */ 88 cmp x30, #EC_AARCH32_SMC 89 b.eq smc_handler32 90 91 cmp x30, #EC_AARCH64_SMC 92 b.eq smc_handler64 93 94 /* Check for I/D aborts from lower EL */ 95 cmp x30, #EC_IABORT_LOWER_EL 96 b.eq 1f 97 98 cmp x30, #EC_DABORT_LOWER_EL 99 b.ne 2f 100 1011: 102 /* Test for EA bit in the instruction syndrome */ 103 mrs x30, esr_el3 104 tbz x30, #ESR_ISS_EABORT_EA_BIT, 2f 105 handle_ea #ERROR_EA_SYNC 106 1072: 108 /* Other kinds of synchronous exceptions are not handled */ 109 ldr x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR] 110 b report_unhandled_exception 111 .endm 112 113 114 /* --------------------------------------------------------------------- 115 * This macro handles FIQ or IRQ interrupts i.e. EL3, S-EL1 and NS 116 * interrupts. 117 * --------------------------------------------------------------------- 118 */ 119 .macro handle_interrupt_exception label 120 /* Enable the SError interrupt */ 121 msr daifclr, #DAIF_ABT_BIT 122 123 str x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR] 124 bl save_gp_registers 125 126 /* Save the EL3 system registers needed to return from this exception */ 127 mrs x0, spsr_el3 128 mrs x1, elr_el3 129 stp x0, x1, [sp, #CTX_EL3STATE_OFFSET + CTX_SPSR_EL3] 130 131 /* Switch to the runtime stack i.e. SP_EL0 */ 132 ldr x2, [sp, #CTX_EL3STATE_OFFSET + CTX_RUNTIME_SP] 133 mov x20, sp 134 msr spsel, #0 135 mov sp, x2 136 137 /* 138 * Find out whether this is a valid interrupt type. 139 * If the interrupt controller reports a spurious interrupt then return 140 * to where we came from. 141 */ 142 bl plat_ic_get_pending_interrupt_type 143 cmp x0, #INTR_TYPE_INVAL 144 b.eq interrupt_exit_\label 145 146 /* 147 * Get the registered handler for this interrupt type. 148 * A NULL return value could be 'cause of the following conditions: 149 * 150 * a. An interrupt of a type was routed correctly but a handler for its 151 * type was not registered. 152 * 153 * b. An interrupt of a type was not routed correctly so a handler for 154 * its type was not registered. 155 * 156 * c. An interrupt of a type was routed correctly to EL3, but was 157 * deasserted before its pending state could be read. Another 158 * interrupt of a different type pended at the same time and its 159 * type was reported as pending instead. However, a handler for this 160 * type was not registered. 161 * 162 * a. and b. can only happen due to a programming error. The 163 * occurrence of c. could be beyond the control of Trusted Firmware. 164 * It makes sense to return from this exception instead of reporting an 165 * error. 166 */ 167 bl get_interrupt_type_handler 168 cbz x0, interrupt_exit_\label 169 mov x21, x0 170 171 mov x0, #INTR_ID_UNAVAILABLE 172 173 /* Set the current security state in the 'flags' parameter */ 174 mrs x2, scr_el3 175 ubfx x1, x2, #0, #1 176 177 /* Restore the reference to the 'handle' i.e. SP_EL3 */ 178 mov x2, x20 179 180 /* x3 will point to a cookie (not used now) */ 181 mov x3, xzr 182 183 /* Call the interrupt type handler */ 184 blr x21 185 186interrupt_exit_\label: 187 /* Return from exception, possibly in a different security state */ 188 b el3_exit 189 190 .endm 191 192 193vector_base runtime_exceptions 194 195 /* --------------------------------------------------------------------- 196 * Current EL with SP_EL0 : 0x0 - 0x200 197 * --------------------------------------------------------------------- 198 */ 199vector_entry sync_exception_sp_el0 200 /* We don't expect any synchronous exceptions from EL3 */ 201 b report_unhandled_exception 202 check_vector_size sync_exception_sp_el0 203 204vector_entry irq_sp_el0 205 /* 206 * EL3 code is non-reentrant. Any asynchronous exception is a serious 207 * error. Loop infinitely. 208 */ 209 b report_unhandled_interrupt 210 check_vector_size irq_sp_el0 211 212 213vector_entry fiq_sp_el0 214 b report_unhandled_interrupt 215 check_vector_size fiq_sp_el0 216 217 218vector_entry serror_sp_el0 219 b report_unhandled_exception 220 check_vector_size serror_sp_el0 221 222 /* --------------------------------------------------------------------- 223 * Current EL with SP_ELx: 0x200 - 0x400 224 * --------------------------------------------------------------------- 225 */ 226vector_entry sync_exception_sp_elx 227 /* 228 * This exception will trigger if anything went wrong during a previous 229 * exception entry or exit or while handling an earlier unexpected 230 * synchronous exception. There is a high probability that SP_EL3 is 231 * corrupted. 232 */ 233 b report_unhandled_exception 234 check_vector_size sync_exception_sp_elx 235 236vector_entry irq_sp_elx 237 b report_unhandled_interrupt 238 check_vector_size irq_sp_elx 239 240vector_entry fiq_sp_elx 241 b report_unhandled_interrupt 242 check_vector_size fiq_sp_elx 243 244vector_entry serror_sp_elx 245 b report_unhandled_exception 246 check_vector_size serror_sp_elx 247 248 /* --------------------------------------------------------------------- 249 * Lower EL using AArch64 : 0x400 - 0x600 250 * --------------------------------------------------------------------- 251 */ 252vector_entry sync_exception_aarch64 253 /* 254 * This exception vector will be the entry point for SMCs and traps 255 * that are unhandled at lower ELs most commonly. SP_EL3 should point 256 * to a valid cpu context where the general purpose and system register 257 * state can be saved. 258 */ 259 handle_sync_exception 260 check_vector_size sync_exception_aarch64 261 262vector_entry irq_aarch64 263 handle_interrupt_exception irq_aarch64 264 check_vector_size irq_aarch64 265 266vector_entry fiq_aarch64 267 handle_interrupt_exception fiq_aarch64 268 check_vector_size fiq_aarch64 269 270vector_entry serror_aarch64 271 msr daifclr, #DAIF_ABT_BIT 272 273 /* 274 * Explicitly save x30 so as to free up a register and to enable 275 * branching 276 */ 277 str x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR] 278 handle_ea #ERROR_EA_ASYNC 279 check_vector_size serror_aarch64 280 281 /* --------------------------------------------------------------------- 282 * Lower EL using AArch32 : 0x600 - 0x800 283 * --------------------------------------------------------------------- 284 */ 285vector_entry sync_exception_aarch32 286 /* 287 * This exception vector will be the entry point for SMCs and traps 288 * that are unhandled at lower ELs most commonly. SP_EL3 should point 289 * to a valid cpu context where the general purpose and system register 290 * state can be saved. 291 */ 292 handle_sync_exception 293 check_vector_size sync_exception_aarch32 294 295vector_entry irq_aarch32 296 handle_interrupt_exception irq_aarch32 297 check_vector_size irq_aarch32 298 299vector_entry fiq_aarch32 300 handle_interrupt_exception fiq_aarch32 301 check_vector_size fiq_aarch32 302 303vector_entry serror_aarch32 304 msr daifclr, #DAIF_ABT_BIT 305 306 /* 307 * Explicitly save x30 so as to free up a register and to enable 308 * branching 309 */ 310 str x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR] 311 handle_ea #ERROR_EA_ASYNC 312 check_vector_size serror_aarch32 313 314 315 /* --------------------------------------------------------------------- 316 * This macro takes an argument in x16 that is the index in the 317 * 'rt_svc_descs_indices' array, checks that the value in the array is 318 * valid, and loads in x15 the pointer to the handler of that service. 319 * --------------------------------------------------------------------- 320 */ 321 .macro load_rt_svc_desc_pointer 322 /* Load descriptor index from array of indices */ 323 adr x14, rt_svc_descs_indices 324 ldrb w15, [x14, x16] 325 326#if SMCCC_MAJOR_VERSION == 1 327 /* Any index greater than 127 is invalid. Check bit 7. */ 328 tbnz w15, 7, smc_unknown 329#elif SMCCC_MAJOR_VERSION == 2 330 /* Verify that the top 3 bits of the loaded index are 0 (w15 <= 31) */ 331 cmp w15, #31 332 b.hi smc_unknown 333#endif /* SMCCC_MAJOR_VERSION */ 334 335 /* 336 * Get the descriptor using the index 337 * x11 = (base + off), w15 = index 338 * 339 * handler = (base + off) + (index << log2(size)) 340 */ 341 adr x11, (__RT_SVC_DESCS_START__ + RT_SVC_DESC_HANDLE) 342 lsl w10, w15, #RT_SVC_SIZE_LOG2 343 ldr x15, [x11, w10, uxtw] 344 .endm 345 346 /* --------------------------------------------------------------------- 347 * The following code handles secure monitor calls. 348 * Depending upon the execution state from where the SMC has been 349 * invoked, it frees some general purpose registers to perform the 350 * remaining tasks. They involve finding the runtime service handler 351 * that is the target of the SMC & switching to runtime stacks (SP_EL0) 352 * before calling the handler. 353 * 354 * Note that x30 has been explicitly saved and can be used here 355 * --------------------------------------------------------------------- 356 */ 357func smc_handler 358smc_handler32: 359 /* Check whether aarch32 issued an SMC64 */ 360 tbnz x0, #FUNCID_CC_SHIFT, smc_prohibited 361 362smc_handler64: 363 /* 364 * Populate the parameters for the SMC handler. 365 * We already have x0-x4 in place. x5 will point to a cookie (not used 366 * now). x6 will point to the context structure (SP_EL3) and x7 will 367 * contain flags we need to pass to the handler. 368 * 369 * Save x4-x29 and sp_el0. 370 */ 371 stp x4, x5, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X4] 372 stp x6, x7, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X6] 373 stp x8, x9, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X8] 374 stp x10, x11, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X10] 375 stp x12, x13, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X12] 376 stp x14, x15, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X14] 377 stp x16, x17, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X16] 378 stp x18, x19, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X18] 379 stp x20, x21, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X20] 380 stp x22, x23, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X22] 381 stp x24, x25, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X24] 382 stp x26, x27, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X26] 383 stp x28, x29, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X28] 384 mrs x18, sp_el0 385 str x18, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_SP_EL0] 386 387 mov x5, xzr 388 mov x6, sp 389 390#if SMCCC_MAJOR_VERSION == 1 391 392 /* Get the unique owning entity number */ 393 ubfx x16, x0, #FUNCID_OEN_SHIFT, #FUNCID_OEN_WIDTH 394 ubfx x15, x0, #FUNCID_TYPE_SHIFT, #FUNCID_TYPE_WIDTH 395 orr x16, x16, x15, lsl #FUNCID_OEN_WIDTH 396 397 load_rt_svc_desc_pointer 398 399#elif SMCCC_MAJOR_VERSION == 2 400 401 /* Bit 31 must be set */ 402 tbz x0, #FUNCID_TYPE_SHIFT, smc_unknown 403 404 /* 405 * Check MSB of namespace to decide between compatibility/vendor and 406 * SPCI/SPRT 407 */ 408 tbz x0, #(FUNCID_NAMESPACE_SHIFT + 1), compat_or_vendor 409 410 /* Namespaces SPRT and SPCI currently unimplemented */ 411 b smc_unknown 412 413compat_or_vendor: 414 415 /* Namespace is b'00 (compatibility) or b'01 (vendor) */ 416 417 /* 418 * Add the LSB of the namespace (bit [28]) to the OEN [27:24] to create 419 * a 5-bit index into the rt_svc_descs_indices array. 420 * 421 * The low 16 entries of the rt_svc_descs_indices array correspond to 422 * OENs of the compatibility namespace and the top 16 entries of the 423 * array are assigned to the vendor namespace descriptor. 424 */ 425 ubfx x16, x0, #FUNCID_OEN_SHIFT, #(FUNCID_OEN_WIDTH + 1) 426 427 load_rt_svc_desc_pointer 428 429#endif /* SMCCC_MAJOR_VERSION */ 430 431 /* 432 * Restore the saved C runtime stack value which will become the new 433 * SP_EL0 i.e. EL3 runtime stack. It was saved in the 'cpu_context' 434 * structure prior to the last ERET from EL3. 435 */ 436 ldr x12, [x6, #CTX_EL3STATE_OFFSET + CTX_RUNTIME_SP] 437 438 /* Switch to SP_EL0 */ 439 msr spsel, #0 440 441 /* 442 * Save the SPSR_EL3, ELR_EL3, & SCR_EL3 in case there is a world 443 * switch during SMC handling. 444 * TODO: Revisit if all system registers can be saved later. 445 */ 446 mrs x16, spsr_el3 447 mrs x17, elr_el3 448 mrs x18, scr_el3 449 stp x16, x17, [x6, #CTX_EL3STATE_OFFSET + CTX_SPSR_EL3] 450 str x18, [x6, #CTX_EL3STATE_OFFSET + CTX_SCR_EL3] 451 452 /* Copy SCR_EL3.NS bit to the flag to indicate caller's security */ 453 bfi x7, x18, #0, #1 454 455 mov sp, x12 456 457 /* 458 * Call the Secure Monitor Call handler and then drop directly into 459 * el3_exit() which will program any remaining architectural state 460 * prior to issuing the ERET to the desired lower EL. 461 */ 462#if DEBUG 463 cbz x15, rt_svc_fw_critical_error 464#endif 465 blr x15 466 467 b el3_exit 468 469smc_unknown: 470 /* 471 * Unknown SMC call. Populate return value with SMC_UNK, restore 472 * GP registers, and return to caller. 473 */ 474 mov x0, #SMC_UNK 475 str x0, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X0] 476 b restore_gp_registers_eret 477 478smc_prohibited: 479 ldr x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR] 480 mov x0, #SMC_UNK 481 eret 482 483rt_svc_fw_critical_error: 484 /* Switch to SP_ELx */ 485 msr spsel, #1 486 no_ret report_unhandled_exception 487endfunc smc_handler 488 489/* 490 * Delegate External Abort handling to platform's EA handler. This function 491 * assumes that all GP registers have been saved by the caller. 492 * 493 * x0: EA reason 494 * x1: EA syndrome 495 */ 496func delegate_ea 497 /* Save EL3 state */ 498 mrs x2, spsr_el3 499 mrs x3, elr_el3 500 stp x2, x3, [sp, #CTX_EL3STATE_OFFSET + CTX_SPSR_EL3] 501 502 /* 503 * Save ESR as handling might involve lower ELs, and returning back to 504 * EL3 from there would trample the original ESR. 505 */ 506 mrs x4, scr_el3 507 mrs x5, esr_el3 508 stp x4, x5, [sp, #CTX_EL3STATE_OFFSET + CTX_SCR_EL3] 509 510 /* 511 * Setup rest of arguments, and call platform External Abort handler. 512 * 513 * x0: EA reason (already in place) 514 * x1: Exception syndrome (already in place). 515 * x2: Cookie (unused for now). 516 * x3: Context pointer. 517 * x4: Flags (security state from SCR for now). 518 */ 519 mov x2, xzr 520 mov x3, sp 521 ubfx x4, x4, #0, #1 522 523 /* Switch to runtime stack */ 524 ldr x5, [sp, #CTX_EL3STATE_OFFSET + CTX_RUNTIME_SP] 525 msr spsel, #0 526 mov sp, x5 527 528 mov x29, x30 529 bl plat_ea_handler 530 mov x30, x29 531 532 /* Make SP point to context */ 533 msr spsel, #1 534 535 /* Restore EL3 state */ 536 ldp x1, x2, [sp, #CTX_EL3STATE_OFFSET + CTX_SPSR_EL3] 537 msr spsr_el3, x1 538 msr elr_el3, x2 539 540 /* Restore ESR_EL3 and SCR_EL3 */ 541 ldp x3, x4, [sp, #CTX_EL3STATE_OFFSET + CTX_SCR_EL3] 542 msr scr_el3, x3 543 msr esr_el3, x4 544 545 ret 546endfunc delegate_ea 547