1 /* 2 * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch.h> 8 #include <arch_helpers.h> 9 #include <arm_def.h> 10 #include <assert.h> 11 #include <bl_common.h> 12 #include <console.h> 13 #include <debug.h> 14 #include <mmio.h> 15 #include <plat_arm.h> 16 #include <platform.h> 17 #include <ras.h> 18 19 #define BL31_END (uintptr_t)(&__BL31_END__) 20 21 /* 22 * Placeholder variables for copying the arguments that have been passed to 23 * BL31 from BL2. 24 */ 25 static entry_point_info_t bl32_image_ep_info; 26 static entry_point_info_t bl33_image_ep_info; 27 28 29 /* Weak definitions may be overridden in specific ARM standard platform */ 30 #pragma weak bl31_early_platform_setup2 31 #pragma weak bl31_platform_setup 32 #pragma weak bl31_plat_arch_setup 33 #pragma weak bl31_plat_get_next_image_ep_info 34 35 36 /******************************************************************************* 37 * Return a pointer to the 'entry_point_info' structure of the next image for the 38 * security state specified. BL33 corresponds to the non-secure image type 39 * while BL32 corresponds to the secure image type. A NULL pointer is returned 40 * if the image does not exist. 41 ******************************************************************************/ 42 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) 43 { 44 entry_point_info_t *next_image_info; 45 46 assert(sec_state_is_valid(type)); 47 next_image_info = (type == NON_SECURE) 48 ? &bl33_image_ep_info : &bl32_image_ep_info; 49 /* 50 * None of the images on the ARM development platforms can have 0x0 51 * as the entrypoint 52 */ 53 if (next_image_info->pc) 54 return next_image_info; 55 else 56 return NULL; 57 } 58 59 /******************************************************************************* 60 * Perform any BL31 early platform setup common to ARM standard platforms. 61 * Here is an opportunity to copy parameters passed by the calling EL (S-EL1 62 * in BL2 & S-EL3 in BL1) before they are lost (potentially). This needs to be 63 * done before the MMU is initialized so that the memory layout can be used 64 * while creating page tables. BL2 has flushed this information to memory, so 65 * we are guaranteed to pick up good data. 66 ******************************************************************************/ 67 #if LOAD_IMAGE_V2 68 void arm_bl31_early_platform_setup(void *from_bl2, uintptr_t soc_fw_config, 69 uintptr_t hw_config, void *plat_params_from_bl2) 70 #else 71 void arm_bl31_early_platform_setup(bl31_params_t *from_bl2, uintptr_t soc_fw_config, 72 uintptr_t hw_config, void *plat_params_from_bl2) 73 #endif 74 { 75 /* Initialize the console to provide early debug support */ 76 console_init(PLAT_ARM_BOOT_UART_BASE, PLAT_ARM_BOOT_UART_CLK_IN_HZ, 77 ARM_CONSOLE_BAUDRATE); 78 79 #if RESET_TO_BL31 80 /* There are no parameters from BL2 if BL31 is a reset vector */ 81 assert(from_bl2 == NULL); 82 assert(plat_params_from_bl2 == NULL); 83 84 #ifdef BL32_BASE 85 /* Populate entry point information for BL32 */ 86 SET_PARAM_HEAD(&bl32_image_ep_info, 87 PARAM_EP, 88 VERSION_1, 89 0); 90 SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE); 91 bl32_image_ep_info.pc = BL32_BASE; 92 bl32_image_ep_info.spsr = arm_get_spsr_for_bl32_entry(); 93 #endif /* BL32_BASE */ 94 95 /* Populate entry point information for BL33 */ 96 SET_PARAM_HEAD(&bl33_image_ep_info, 97 PARAM_EP, 98 VERSION_1, 99 0); 100 /* 101 * Tell BL31 where the non-trusted software image 102 * is located and the entry state information 103 */ 104 bl33_image_ep_info.pc = plat_get_ns_image_entrypoint(); 105 106 bl33_image_ep_info.spsr = arm_get_spsr_for_bl33_entry(); 107 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); 108 109 #else /* RESET_TO_BL31 */ 110 111 /* 112 * In debug builds, we pass a special value in 'plat_params_from_bl2' 113 * to verify platform parameters from BL2 to BL31. 114 * In release builds, it's not used. 115 */ 116 assert(((unsigned long long)plat_params_from_bl2) == 117 ARM_BL31_PLAT_PARAM_VAL); 118 119 # if LOAD_IMAGE_V2 120 /* 121 * Check params passed from BL2 should not be NULL, 122 */ 123 bl_params_t *params_from_bl2 = (bl_params_t *)from_bl2; 124 assert(params_from_bl2 != NULL); 125 assert(params_from_bl2->h.type == PARAM_BL_PARAMS); 126 assert(params_from_bl2->h.version >= VERSION_2); 127 128 bl_params_node_t *bl_params = params_from_bl2->head; 129 130 /* 131 * Copy BL33 and BL32 (if present), entry point information. 132 * They are stored in Secure RAM, in BL2's address space. 133 */ 134 while (bl_params) { 135 if (bl_params->image_id == BL32_IMAGE_ID) 136 bl32_image_ep_info = *bl_params->ep_info; 137 138 if (bl_params->image_id == BL33_IMAGE_ID) 139 bl33_image_ep_info = *bl_params->ep_info; 140 141 bl_params = bl_params->next_params_info; 142 } 143 144 if (bl33_image_ep_info.pc == 0) 145 panic(); 146 147 # else /* LOAD_IMAGE_V2 */ 148 149 /* 150 * Check params passed from BL2 should not be NULL, 151 */ 152 assert(from_bl2 != NULL); 153 assert(from_bl2->h.type == PARAM_BL31); 154 assert(from_bl2->h.version >= VERSION_1); 155 156 /* Dynamic Config is not supported for LOAD_IMAGE_V1 */ 157 assert(soc_fw_config == 0); 158 assert(hw_config == 0); 159 160 /* 161 * Copy BL32 (if populated by BL2) and BL33 entry point information. 162 * They are stored in Secure RAM, in BL2's address space. 163 */ 164 if (from_bl2->bl32_ep_info) 165 bl32_image_ep_info = *from_bl2->bl32_ep_info; 166 bl33_image_ep_info = *from_bl2->bl33_ep_info; 167 168 # endif /* LOAD_IMAGE_V2 */ 169 #endif /* RESET_TO_BL31 */ 170 } 171 172 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, 173 u_register_t arg2, u_register_t arg3) 174 { 175 arm_bl31_early_platform_setup((void *)arg0, arg1, arg2, (void *)arg3); 176 177 /* 178 * Initialize Interconnect for this cluster during cold boot. 179 * No need for locks as no other CPU is active. 180 */ 181 plat_arm_interconnect_init(); 182 183 /* 184 * Enable Interconnect coherency for the primary CPU's cluster. 185 * Earlier bootloader stages might already do this (e.g. Trusted 186 * Firmware's BL1 does it) but we can't assume so. There is no harm in 187 * executing this code twice anyway. 188 * Platform specific PSCI code will enable coherency for other 189 * clusters. 190 */ 191 plat_arm_interconnect_enter_coherency(); 192 } 193 194 /******************************************************************************* 195 * Perform any BL31 platform setup common to ARM standard platforms 196 ******************************************************************************/ 197 void arm_bl31_platform_setup(void) 198 { 199 /* Initialize the GIC driver, cpu and distributor interfaces */ 200 plat_arm_gic_driver_init(); 201 plat_arm_gic_init(); 202 203 #if RESET_TO_BL31 204 /* 205 * Do initial security configuration to allow DRAM/device access 206 * (if earlier BL has not already done so). 207 */ 208 plat_arm_security_setup(); 209 210 #if defined(PLAT_ARM_MEM_PROT_ADDR) 211 arm_nor_psci_do_dyn_mem_protect(); 212 #endif /* PLAT_ARM_MEM_PROT_ADDR */ 213 214 #endif /* RESET_TO_BL31 */ 215 216 /* Enable and initialize the System level generic timer */ 217 mmio_write_32(ARM_SYS_CNTCTL_BASE + CNTCR_OFF, 218 CNTCR_FCREQ(0) | CNTCR_EN); 219 220 /* Allow access to the System counter timer module */ 221 arm_configure_sys_timer(); 222 223 /* Initialize power controller before setting up topology */ 224 plat_arm_pwrc_setup(); 225 226 #if RAS_EXTENSION 227 ras_init(); 228 #endif 229 } 230 231 /******************************************************************************* 232 * Perform any BL31 platform runtime setup prior to BL31 exit common to ARM 233 * standard platforms 234 ******************************************************************************/ 235 void arm_bl31_plat_runtime_setup(void) 236 { 237 /* Initialize the runtime console */ 238 console_init(PLAT_ARM_BL31_RUN_UART_BASE, PLAT_ARM_BL31_RUN_UART_CLK_IN_HZ, 239 ARM_CONSOLE_BAUDRATE); 240 } 241 242 void bl31_platform_setup(void) 243 { 244 arm_bl31_platform_setup(); 245 } 246 247 void bl31_plat_runtime_setup(void) 248 { 249 arm_bl31_plat_runtime_setup(); 250 } 251 252 /******************************************************************************* 253 * Perform the very early platform specific architectural setup shared between 254 * ARM standard platforms. This only does basic initialization. Later 255 * architectural setup (bl31_arch_setup()) does not do anything platform 256 * specific. 257 ******************************************************************************/ 258 void arm_bl31_plat_arch_setup(void) 259 { 260 arm_setup_page_tables(BL31_BASE, 261 BL31_END - BL31_BASE, 262 BL_CODE_BASE, 263 BL_CODE_END, 264 BL_RO_DATA_BASE, 265 BL_RO_DATA_END 266 #if USE_COHERENT_MEM 267 , BL_COHERENT_RAM_BASE, 268 BL_COHERENT_RAM_END 269 #endif 270 ); 271 enable_mmu_el3(0); 272 } 273 274 void bl31_plat_arch_setup(void) 275 { 276 arm_bl31_plat_arch_setup(); 277 } 278