1 /* 2 * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch.h> 8 #include <arch_helpers.h> 9 #include <arm_def.h> 10 #include <assert.h> 11 #include <bl_common.h> 12 #include <console.h> 13 #include <debug.h> 14 #include <mmio.h> 15 #include <plat_arm.h> 16 #include <platform.h> 17 18 #define BL31_END (uintptr_t)(&__BL31_END__) 19 20 /* 21 * Placeholder variables for copying the arguments that have been passed to 22 * BL31 from BL2. 23 */ 24 static entry_point_info_t bl32_image_ep_info; 25 static entry_point_info_t bl33_image_ep_info; 26 27 28 /* Weak definitions may be overridden in specific ARM standard platform */ 29 #pragma weak bl31_early_platform_setup2 30 #pragma weak bl31_platform_setup 31 #pragma weak bl31_plat_arch_setup 32 #pragma weak bl31_plat_get_next_image_ep_info 33 34 35 /******************************************************************************* 36 * Return a pointer to the 'entry_point_info' structure of the next image for the 37 * security state specified. BL33 corresponds to the non-secure image type 38 * while BL32 corresponds to the secure image type. A NULL pointer is returned 39 * if the image does not exist. 40 ******************************************************************************/ 41 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) 42 { 43 entry_point_info_t *next_image_info; 44 45 assert(sec_state_is_valid(type)); 46 next_image_info = (type == NON_SECURE) 47 ? &bl33_image_ep_info : &bl32_image_ep_info; 48 /* 49 * None of the images on the ARM development platforms can have 0x0 50 * as the entrypoint 51 */ 52 if (next_image_info->pc) 53 return next_image_info; 54 else 55 return NULL; 56 } 57 58 /******************************************************************************* 59 * Perform any BL31 early platform setup common to ARM standard platforms. 60 * Here is an opportunity to copy parameters passed by the calling EL (S-EL1 61 * in BL2 & S-EL3 in BL1) before they are lost (potentially). This needs to be 62 * done before the MMU is initialized so that the memory layout can be used 63 * while creating page tables. BL2 has flushed this information to memory, so 64 * we are guaranteed to pick up good data. 65 ******************************************************************************/ 66 #if LOAD_IMAGE_V2 67 void arm_bl31_early_platform_setup(void *from_bl2, uintptr_t soc_fw_config, 68 uintptr_t hw_config, void *plat_params_from_bl2) 69 #else 70 void arm_bl31_early_platform_setup(bl31_params_t *from_bl2, uintptr_t soc_fw_config, 71 uintptr_t hw_config, void *plat_params_from_bl2) 72 #endif 73 { 74 /* Initialize the console to provide early debug support */ 75 arm_console_boot_init(); 76 77 #if RESET_TO_BL31 78 /* There are no parameters from BL2 if BL31 is a reset vector */ 79 assert(from_bl2 == NULL); 80 assert(plat_params_from_bl2 == NULL); 81 82 #ifdef BL32_BASE 83 /* Populate entry point information for BL32 */ 84 SET_PARAM_HEAD(&bl32_image_ep_info, 85 PARAM_EP, 86 VERSION_1, 87 0); 88 SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE); 89 bl32_image_ep_info.pc = BL32_BASE; 90 bl32_image_ep_info.spsr = arm_get_spsr_for_bl32_entry(); 91 #endif /* BL32_BASE */ 92 93 /* Populate entry point information for BL33 */ 94 SET_PARAM_HEAD(&bl33_image_ep_info, 95 PARAM_EP, 96 VERSION_1, 97 0); 98 /* 99 * Tell BL31 where the non-trusted software image 100 * is located and the entry state information 101 */ 102 bl33_image_ep_info.pc = plat_get_ns_image_entrypoint(); 103 104 bl33_image_ep_info.spsr = arm_get_spsr_for_bl33_entry(); 105 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); 106 107 #else /* RESET_TO_BL31 */ 108 109 /* 110 * In debug builds, we pass a special value in 'plat_params_from_bl2' 111 * to verify platform parameters from BL2 to BL31. 112 * In release builds, it's not used. 113 */ 114 assert(((unsigned long long)plat_params_from_bl2) == 115 ARM_BL31_PLAT_PARAM_VAL); 116 117 # if LOAD_IMAGE_V2 118 /* 119 * Check params passed from BL2 should not be NULL, 120 */ 121 bl_params_t *params_from_bl2 = (bl_params_t *)from_bl2; 122 assert(params_from_bl2 != NULL); 123 assert(params_from_bl2->h.type == PARAM_BL_PARAMS); 124 assert(params_from_bl2->h.version >= VERSION_2); 125 126 bl_params_node_t *bl_params = params_from_bl2->head; 127 128 /* 129 * Copy BL33 and BL32 (if present), entry point information. 130 * They are stored in Secure RAM, in BL2's address space. 131 */ 132 while (bl_params) { 133 if (bl_params->image_id == BL32_IMAGE_ID) 134 bl32_image_ep_info = *bl_params->ep_info; 135 136 if (bl_params->image_id == BL33_IMAGE_ID) 137 bl33_image_ep_info = *bl_params->ep_info; 138 139 bl_params = bl_params->next_params_info; 140 } 141 142 if (bl33_image_ep_info.pc == 0) 143 panic(); 144 145 # else /* LOAD_IMAGE_V2 */ 146 147 /* 148 * Check params passed from BL2 should not be NULL, 149 */ 150 assert(from_bl2 != NULL); 151 assert(from_bl2->h.type == PARAM_BL31); 152 assert(from_bl2->h.version >= VERSION_1); 153 154 /* Dynamic Config is not supported for LOAD_IMAGE_V1 */ 155 assert(soc_fw_config == 0); 156 assert(hw_config == 0); 157 158 /* 159 * Copy BL32 (if populated by BL2) and BL33 entry point information. 160 * They are stored in Secure RAM, in BL2's address space. 161 */ 162 if (from_bl2->bl32_ep_info) 163 bl32_image_ep_info = *from_bl2->bl32_ep_info; 164 bl33_image_ep_info = *from_bl2->bl33_ep_info; 165 166 # endif /* LOAD_IMAGE_V2 */ 167 #endif /* RESET_TO_BL31 */ 168 } 169 170 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, 171 u_register_t arg2, u_register_t arg3) 172 { 173 arm_bl31_early_platform_setup((void *)arg0, arg1, arg2, (void *)arg3); 174 175 /* 176 * Initialize Interconnect for this cluster during cold boot. 177 * No need for locks as no other CPU is active. 178 */ 179 plat_arm_interconnect_init(); 180 181 /* 182 * Enable Interconnect coherency for the primary CPU's cluster. 183 * Earlier bootloader stages might already do this (e.g. Trusted 184 * Firmware's BL1 does it) but we can't assume so. There is no harm in 185 * executing this code twice anyway. 186 * Platform specific PSCI code will enable coherency for other 187 * clusters. 188 */ 189 plat_arm_interconnect_enter_coherency(); 190 } 191 192 /******************************************************************************* 193 * Perform any BL31 platform setup common to ARM standard platforms 194 ******************************************************************************/ 195 void arm_bl31_platform_setup(void) 196 { 197 /* Initialize the GIC driver, cpu and distributor interfaces */ 198 plat_arm_gic_driver_init(); 199 plat_arm_gic_init(); 200 201 #if RESET_TO_BL31 202 /* 203 * Do initial security configuration to allow DRAM/device access 204 * (if earlier BL has not already done so). 205 */ 206 plat_arm_security_setup(); 207 208 #if defined(PLAT_ARM_MEM_PROT_ADDR) 209 arm_nor_psci_do_dyn_mem_protect(); 210 #endif /* PLAT_ARM_MEM_PROT_ADDR */ 211 212 #endif /* RESET_TO_BL31 */ 213 214 /* Enable and initialize the System level generic timer */ 215 mmio_write_32(ARM_SYS_CNTCTL_BASE + CNTCR_OFF, 216 CNTCR_FCREQ(0) | CNTCR_EN); 217 218 /* Allow access to the System counter timer module */ 219 arm_configure_sys_timer(); 220 221 /* Initialize power controller before setting up topology */ 222 plat_arm_pwrc_setup(); 223 } 224 225 /******************************************************************************* 226 * Perform any BL31 platform runtime setup prior to BL31 exit common to ARM 227 * standard platforms 228 * Perform BL31 platform setup 229 ******************************************************************************/ 230 void arm_bl31_plat_runtime_setup(void) 231 { 232 #if MULTI_CONSOLE_API 233 console_switch_state(CONSOLE_FLAG_RUNTIME); 234 #else 235 console_uninit(); 236 #endif 237 238 /* Initialize the runtime console */ 239 arm_console_runtime_init(); 240 } 241 242 void bl31_platform_setup(void) 243 { 244 arm_bl31_platform_setup(); 245 } 246 247 void bl31_plat_runtime_setup(void) 248 { 249 arm_bl31_plat_runtime_setup(); 250 } 251 252 /******************************************************************************* 253 * Perform the very early platform specific architectural setup shared between 254 * ARM standard platforms. This only does basic initialization. Later 255 * architectural setup (bl31_arch_setup()) does not do anything platform 256 * specific. 257 ******************************************************************************/ 258 void arm_bl31_plat_arch_setup(void) 259 { 260 arm_setup_page_tables(BL31_BASE, 261 BL31_END - BL31_BASE, 262 BL_CODE_BASE, 263 BL_CODE_END, 264 BL_RO_DATA_BASE, 265 BL_RO_DATA_END 266 #if USE_COHERENT_MEM 267 , BL_COHERENT_RAM_BASE, 268 BL_COHERENT_RAM_END 269 #endif 270 ); 271 enable_mmu_el3(0); 272 } 273 274 void bl31_plat_arch_setup(void) 275 { 276 arm_bl31_plat_arch_setup(); 277 } 278