plat: rcar: Pass DTB with DRAM layout from BL2 to next stages

Pass DTB containing DRAM layout from BL2 to BL33 via register x3, so
that the BL33 can simply consume it and get accurate DRAM layout in

plat: rcar: Pass DTB with DRAM layout from BL2 to next stages

Pass DTB containing DRAM layout from BL2 to BL33 via register x3, so
that the BL33 can simply consume it and get accurate DRAM layout info.
BL33 is in most usecases U-Boot.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>

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plat: rcar: Use array in the DRAM size reporting

Use array of start-size tuples for the DRAM banks and call single
function which iterates over this array to report the DRAM info.
This is in prepara

plat: rcar: Use array in the DRAM size reporting

Use array of start-size tuples for the DRAM banks and call single
function which iterates over this array to report the DRAM info.
This is in preparation for expanding this to generate FDT for the
next stage.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>

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plat: rcar: Print DRAM configuration after init

Print the DRAM configuration only after the DRAM was initialized. This
will be useful when deduplicating code populating FDT passed to U-Boot,
since i

plat: rcar: Print DRAM configuration after init

Print the DRAM configuration only after the DRAM was initialized. This
will be useful when deduplicating code populating FDT passed to U-Boot,
since it will contain the same macros as bl2_advertise_dram_size().

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>

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plat: rcar: Fill in memory information for M3W, M3N

Make the DRAM configuration debug print consistent for all supported SoCs.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>

plat: rcar: Drop H3 v3.0 check on DRAM debug print

There is nothing preventing H3 older than v3.0 from printing the
DRAM configuration, just like v3.0 and newer. Drop the check and
let all H3 revisi

plat: rcar: Drop H3 v3.0 check on DRAM debug print

There is nothing preventing H3 older than v3.0 from printing the
DRAM configuration, just like v3.0 and newer. Drop the check and
let all H3 revisions print DRAM configuration in BL2.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>

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plat: rcar: Add E3 1GBx4 debug print

RCAR_DRAM_DDR3L_MEMCONF = 2 means E3 with 1GBx4 memory configuration.
Add debug print for this configuration for completeness sake.

Signed-off-by: Marek Vasut <

plat: rcar: Add E3 1GBx4 debug print

RCAR_DRAM_DDR3L_MEMCONF = 2 means E3 with 1GBx4 memory configuration.
Add debug print for this configuration for completeness sake.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>

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plat: rcar: Move DRAM layout print to separate function

Just move the DRAM layout information into separate function,
no functional change.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>

plat/arm/sgi: Use NT_FW_CONFIG instead of HW_CONFIG

With the two new APIs 'plat_arm_sgi_get_platform_id' and
'plat_arm_sgi_get_config_id' that are available now, BL31 need not
depend on hw_config de

plat/arm/sgi: Use NT_FW_CONFIG instead of HW_CONFIG

With the two new APIs 'plat_arm_sgi_get_platform_id' and
'plat_arm_sgi_get_config_id' that are available now, BL31 need not
depend on hw_config device tree to identify the platform. In addition
to this, the existing hardware description in hw_config can be limited
to use by BL33 and not by the operating system.

So the hardware description from hw_config dts can be moved into
nt_fw_config dts and the use of hw_config dts can be removed.

Change-Id: I873b7e1e72823d3ec5d253a848e85ae724f09e49
Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com>

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Merge pull request #1653 from JackyBai/master

Add NXP i.MX8MQ basic support

plat: imx: Add i.MX8MQ basic support

i.MX8MQ is new SOC of NXP's i.MX8M family based on
A53. It can provide industry-leading audio, voice
and video processing for applications that scale
from consum

plat: imx: Add i.MX8MQ basic support

i.MX8MQ is new SOC of NXP's i.MX8M family based on
A53. It can provide industry-leading audio, voice
and video processing for applications that scale
from consumer home audio to industrial building
automation and mobile computers

this patchset add the basic supoort to boot up
the 4 X A53. more feature will be added later.

Signed-off-by: Bai Ping <ping.bai@nxp.com>

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Merge pull request #1703 from oscardagrach/hikey960-dmac-fix

hikey960: initialize EDMAC and channels

Merge pull request #1705 from chandnich/platform-id

plat/arm/sgi: Use platform specific functions to get platform ids

Merge pull request #1702 from MISL-EBU-System-SW/patches-18.12

Update code with latest changes from Marvell LSP 18.12

plat/marvell: update platform LSP version to 18.12.0

Sync the platform code version with current Marvell LSP.

Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>

a8k: pm: extend MSS_TRIGGER_TIMEOUT

Very rarely, during cpuidle operations the following error
is seen: "PM MSG Trigger Timeout".
This is caused by slow handling of message interrutps
in the PM FW r

a8k: pm: extend MSS_TRIGGER_TIMEOUT

Very rarely, during cpuidle operations the following error
is seen: "PM MSG Trigger Timeout".
This is caused by slow handling of message interrutps
in the PM FW running on CM3 (under heavy PM operation load).

This is not a real issue, so we extend the timeout to
avoid the error prints.

Change-Id: I92fd6f2ff1ddf208b216c123880ded28a00b6e0e
Signed-off-by: Igal Liberman <igall@marvell.com>
Reviewed-on: http://vgitil04.il.marvell.com:8080/59670
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
Tested-by: iSoC Platform CI <ykjenk@marvell.com>

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plat/marvell: comphy: Add support for SFI on Lane 4

Add static configuration for SFI+ 10Gbps interface on SERDES
Lane 4.
This is just a copy of Lane 2 static values, not optimized.
Board-to-board ip

plat/marvell: comphy: Add support for SFI on Lane 4

Add static configuration for SFI+ 10Gbps interface on SERDES
Lane 4.
This is just a copy of Lane 2 static values, not optimized.
Board-to-board iperf test shows up to 6Gbps transfer speed.

Change-Id: I024d2ac132f7fa6c342a64367f3dca2123a27e97
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Reviewed-by: Igal Liberman <igall@marvell.com>

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fix: a3900: pm: fix number of CPU power switches.

- Number of open power switches for CPUs should be three
and now two.

- This patch updates the value of open power switches from
0xfd (two powe

fix: a3900: pm: fix number of CPU power switches.

- Number of open power switches for CPUs should be three
and now two.

- This patch updates the value of open power switches from
0xfd (two power-switches) to 0xfc (three power-switches).

Change-Id: I2783ab7f04bbbb6da78eeedcabe4636f9a774512
Signed-off-by: Christine Gharzuzi <chrisg@marvell.com>
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>

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svc: Update the EEPROM AVS values processing

Add support for SVC test builds for tuning AVS values.
Update the SVC procedure and add EEPROM access.
Add support for AP807 AVS values (10 bits wide).

svc: Update the EEPROM AVS values processing

Add support for SVC test builds for tuning AVS values.
Update the SVC procedure and add EEPROM access.
Add support for AP807 AVS values (10 bits wide).

Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>

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ble: ap807: Switch to PLL mode and update CPU frequency

- Update CPU frequency on AP807 to 2GHz for SAR 0x0.
- Increase AVS to 0.88V for 2GHz clock

Change-Id: Ic945b682ab2f8543e34294bfc56c3eae2c5e0

ble: ap807: Switch to PLL mode and update CPU frequency

- Update CPU frequency on AP807 to 2GHz for SAR 0x0.
- Increase AVS to 0.88V for 2GHz clock

Change-Id: Ic945b682ab2f8543e34294bfc56c3eae2c5e0c8e
Signed-off-by: Christine Gharzuzi <chrisg@marvell.com>
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>

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mvebu: cp110: avoid pcie power on/off sequence when called from Linux

In Armada 8K DB boards, PCIe initialization can be executed only once
because PCIe reset performed during chip power on and it c

mvebu: cp110: avoid pcie power on/off sequence when called from Linux

In Armada 8K DB boards, PCIe initialization can be executed only once
because PCIe reset performed during chip power on and it cannot be
executed via GPIO later.
This means that power on can be executed only once, when it's called
from the bootloader.
Power on:
Read bit 21 of the mode, it marks if the caller is
the bootloader or the Linux Kernel.
Power off:
Check if the comphy was already configured to PCIe, if yes,
check if the caller is bootloader, if both conditions are true
(PCIe mode and called by Linux) - skip the power-off.

In addition, fix incorrect documentation describing mode fields -
PCIe width is 3 bits, not 2.

NOTE: with this patch, please use LK4.14.76 (LK4.4.120 may not work
with it).

Change-Id: I4b929011f97a0a1869a51ba378687e78b3eca4ff
Signed-off-by: Igal Liberman <igall@marvell.com>
Reviewed-by: Grzegorz Jaszczyk <jaz@semihalf.com>
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>

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plat: marvell: a3700: do not power off cpu due to errata ref #13

Do not power off the CPU1 since there is no way to wake it up
(wake-up is causing CPU0 reset as well duo to HW bug). Quote from errat

plat: marvell: a3700: do not power off cpu due to errata ref #13

Do not power off the CPU1 since there is no way to wake it up
(wake-up is causing CPU0 reset as well duo to HW bug). Quote from errata
Ref #13 [In power saving mode, both cores must be powered off]:
"When Core 0 is on and Core 1 is in power-off state, a Core 1
wake-up resets Core 0 as well and puts Core 0 back to ROM".

To overcome described HW bug instead of powering the CPU off, let it
reach WFI instruction, which is invoked by generic psci_do_cpu_off
function after platform handler finishes. This will put the core in low
power state and give a chance to wake it up.

Before this change, after running secondary kernel via kexec, only one
core was up, now both cores are up.

Change-Id: I87f144867550728055d9b8a2edb84a14539acab7
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>

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drivers: add tzc380 support

Add tzc380 support.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Bai Ping <ping.bai@nxp.com>

stm32mp: check stm32_sdmmc2_mmc_init return

Signed-off-by: Yann Gautier <yann.gautier@st.com>

Merge pull request #1699 from chandnich/sgi-mt-support

Add support to implement multi-threaded platforms for SGI

plat/arm/sgi: Use platform specific functions to get platform ids

Add two new functions 'plat_arm_sgi_get_platform_id' and
'plat_arm_sgi_get_config_id' which will be implemented by all the
SGI platf

plat/arm/sgi: Use platform specific functions to get platform ids

Add two new functions 'plat_arm_sgi_get_platform_id' and
'plat_arm_sgi_get_config_id' which will be implemented by all the
SGI platforms. These functions can be used to determine the part
number and configuration id of the SGI platforms.

In BL2, these functions are used to populate the 'system-id' node.
In BL31, these functions are used to populate the 'sgi_plat_info_t'
structure with the part number and configuration id of the platform.

Change-Id: I3bacda933527724a3b4074ad4ed5b53a81ea4689
Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com>

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