1 /* 2 * Copyright (c) 2018, Renesas Electronics Corporation. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <desc_image_load.h> 8 #include <arch_helpers.h> 9 #include <bl_common.h> 10 #include <bl1.h> 11 #include <console.h> 12 #include <debug.h> 13 #include <libfdt.h> 14 #include <mmio.h> 15 #include <platform.h> 16 #include <platform_def.h> 17 #include <string.h> 18 #include <xlat_tables_defs.h> 19 20 #include "avs_driver.h" 21 #include "boot_init_dram.h" 22 #include "cpg_registers.h" 23 #include "board.h" 24 #include "emmc_def.h" 25 #include "emmc_hal.h" 26 #include "emmc_std.h" 27 28 #if PMIC_ROHM_BD9571 && RCAR_SYSTEM_RESET_KEEPON_DDR 29 #include "iic_dvfs.h" 30 #endif 31 32 #include "io_common.h" 33 #include "qos_init.h" 34 #include "rcar_def.h" 35 #include "rcar_private.h" 36 #include "rcar_version.h" 37 #include "rom_api.h" 38 39 IMPORT_SYM(unsigned long, __RO_START__, BL2_RO_BASE) 40 IMPORT_SYM(unsigned long, __RO_END__, BL2_RO_LIMIT) 41 42 #if USE_COHERENT_MEM 43 IMPORT_SYM(unsigned long, __COHERENT_RAM_START__, BL2_COHERENT_RAM_BASE) 44 IMPORT_SYM(unsigned long, __COHERENT_RAM_END__, BL2_COHERENT_RAM_LIMIT) 45 #endif 46 47 extern void plat_rcar_gic_driver_init(void); 48 extern void plat_rcar_gic_init(void); 49 extern void bl2_enter_bl31(const struct entry_point_info *bl_ep_info); 50 extern void bl2_system_cpg_init(void); 51 extern void bl2_secure_setting(void); 52 extern void bl2_cpg_init(void); 53 extern void rcar_io_emmc_setup(void); 54 extern void rcar_io_setup(void); 55 extern void rcar_swdt_release(void); 56 extern void rcar_swdt_init(void); 57 extern void rcar_rpc_init(void); 58 extern void rcar_pfc_init(void); 59 extern void rcar_dma_init(void); 60 61 /* R-Car Gen3 product check */ 62 #if (RCAR_LSI == RCAR_H3) || (RCAR_LSI == RCAR_H3N) 63 #define TARGET_PRODUCT RCAR_PRODUCT_H3 64 #define TARGET_NAME "R-Car H3" 65 #elif RCAR_LSI == RCAR_M3 66 #define TARGET_PRODUCT RCAR_PRODUCT_M3 67 #define TARGET_NAME "R-Car M3" 68 #elif RCAR_LSI == RCAR_M3N 69 #define TARGET_PRODUCT RCAR_PRODUCT_M3N 70 #define TARGET_NAME "R-Car M3N" 71 #elif RCAR_LSI == RCAR_E3 72 #define TARGET_PRODUCT RCAR_PRODUCT_E3 73 #define TARGET_NAME "R-Car E3" 74 #endif 75 76 #if (RCAR_LSI == RCAR_E3) 77 #define GPIO_INDT (GPIO_INDT6) 78 #define GPIO_BKUP_TRG_SHIFT ((uint32_t)1U<<13U) 79 #else 80 #define GPIO_INDT (GPIO_INDT1) 81 #define GPIO_BKUP_TRG_SHIFT ((uint32_t)1U<<8U) 82 #endif 83 84 CASSERT((PARAMS_BASE + sizeof(bl2_to_bl31_params_mem_t) + 0x100) 85 < (RCAR_SHARED_MEM_BASE + RCAR_SHARED_MEM_SIZE), 86 assert_bl31_params_do_not_fit_in_shared_memory); 87 88 static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE); 89 90 /* FDT with DRAM configuration */ 91 uint64_t fdt_blob[PAGE_SIZE_4KB / sizeof(uint64_t)]; 92 static void *fdt = (void *)fdt_blob; 93 94 static void unsigned_num_print(unsigned long long int unum, unsigned int radix, 95 char *string) 96 { 97 /* Just need enough space to store 64 bit decimal integer */ 98 char num_buf[20]; 99 int i = 0; 100 unsigned int rem; 101 102 do { 103 rem = unum % radix; 104 if (rem < 0xa) 105 num_buf[i] = '0' + rem; 106 else 107 num_buf[i] = 'a' + (rem - 0xa); 108 i++; 109 unum /= radix; 110 } while (unum > 0U); 111 112 while (--i >= 0) 113 *string++ = num_buf[i]; 114 } 115 116 #if (RCAR_LOSSY_ENABLE == 1) 117 typedef struct bl2_lossy_info { 118 uint32_t magic; 119 uint32_t a0; 120 uint32_t b0; 121 } bl2_lossy_info_t; 122 123 static void bl2_lossy_setting(uint32_t no, uint64_t start_addr, 124 uint64_t end_addr, uint32_t format, 125 uint32_t enable) 126 { 127 bl2_lossy_info_t info; 128 uint32_t reg; 129 130 reg = format | (start_addr >> 20); 131 mmio_write_32(AXI_DCMPAREACRA0 + 0x8 * no, reg); 132 mmio_write_32(AXI_DCMPAREACRB0 + 0x8 * no, end_addr >> 20); 133 mmio_write_32(AXI_DCMPAREACRA0 + 0x8 * no, reg | enable); 134 135 info.magic = 0x12345678U; 136 info.a0 = mmio_read_32(AXI_DCMPAREACRA0 + 0x8 * no); 137 info.b0 = mmio_read_32(AXI_DCMPAREACRB0 + 0x8 * no); 138 139 mmio_write_32(LOSSY_PARAMS_BASE + sizeof(info) * no, info.magic); 140 mmio_write_32(LOSSY_PARAMS_BASE + sizeof(info) * no + 0x4, info.a0); 141 mmio_write_32(LOSSY_PARAMS_BASE + sizeof(info) * no + 0x8, info.b0); 142 143 NOTICE(" Entry %d: DCMPAREACRAx:0x%x DCMPAREACRBx:0x%x\n", no, 144 mmio_read_32(AXI_DCMPAREACRA0 + 0x8 * no), 145 mmio_read_32(AXI_DCMPAREACRB0 + 0x8 * no)); 146 } 147 #endif 148 149 void bl2_plat_flush_bl31_params(void) 150 { 151 uint32_t product_cut, product, cut; 152 uint32_t boot_dev, boot_cpu; 153 uint32_t lcs, reg, val; 154 155 reg = mmio_read_32(RCAR_MODEMR); 156 boot_dev = reg & MODEMR_BOOT_DEV_MASK; 157 158 if (boot_dev == MODEMR_BOOT_DEV_EMMC_25X1 || 159 boot_dev == MODEMR_BOOT_DEV_EMMC_50X8) 160 emmc_terminate(); 161 162 if ((reg & MODEMR_BOOT_CPU_MASK) != MODEMR_BOOT_CPU_CR7) 163 bl2_secure_setting(); 164 165 reg = mmio_read_32(RCAR_PRR); 166 product_cut = reg & (RCAR_PRODUCT_MASK | RCAR_CUT_MASK); 167 product = reg & RCAR_PRODUCT_MASK; 168 cut = reg & RCAR_CUT_MASK; 169 170 if (product == RCAR_PRODUCT_M3) 171 goto tlb; 172 173 if (product == RCAR_PRODUCT_H3 && RCAR_CUT_VER20 > cut) 174 goto tlb; 175 176 /* Disable MFIS write protection */ 177 mmio_write_32(MFISWPCNTR, MFISWPCNTR_PASSWORD | 1); 178 179 tlb: 180 reg = mmio_read_32(RCAR_MODEMR); 181 boot_cpu = reg & MODEMR_BOOT_CPU_MASK; 182 if (boot_cpu != MODEMR_BOOT_CPU_CA57 && 183 boot_cpu != MODEMR_BOOT_CPU_CA53) 184 goto mmu; 185 186 if (product_cut == RCAR_PRODUCT_H3_CUT20) { 187 mmio_write_32(IPMMUVI0_IMSCTLR, IMSCTLR_DISCACHE); 188 mmio_write_32(IPMMUVI1_IMSCTLR, IMSCTLR_DISCACHE); 189 mmio_write_32(IPMMUPV0_IMSCTLR, IMSCTLR_DISCACHE); 190 mmio_write_32(IPMMUPV1_IMSCTLR, IMSCTLR_DISCACHE); 191 mmio_write_32(IPMMUPV2_IMSCTLR, IMSCTLR_DISCACHE); 192 mmio_write_32(IPMMUPV3_IMSCTLR, IMSCTLR_DISCACHE); 193 } else if (product_cut == (RCAR_PRODUCT_M3N | RCAR_CUT_VER10) || 194 product_cut == (RCAR_PRODUCT_M3N | RCAR_CUT_VER11)) { 195 mmio_write_32(IPMMUVI0_IMSCTLR, IMSCTLR_DISCACHE); 196 mmio_write_32(IPMMUPV0_IMSCTLR, IMSCTLR_DISCACHE); 197 } else if (product_cut == (RCAR_PRODUCT_E3 | RCAR_CUT_VER10)) { 198 mmio_write_32(IPMMUVI0_IMSCTLR, IMSCTLR_DISCACHE); 199 mmio_write_32(IPMMUPV0_IMSCTLR, IMSCTLR_DISCACHE); 200 } 201 202 if (product_cut == (RCAR_PRODUCT_H3_CUT20) || 203 product_cut == (RCAR_PRODUCT_M3N | RCAR_CUT_VER10) || 204 product_cut == (RCAR_PRODUCT_M3N | RCAR_CUT_VER11) || 205 product_cut == (RCAR_PRODUCT_E3 | RCAR_CUT_VER10)) { 206 mmio_write_32(IPMMUHC_IMSCTLR, IMSCTLR_DISCACHE); 207 mmio_write_32(IPMMURT_IMSCTLR, IMSCTLR_DISCACHE); 208 mmio_write_32(IPMMUMP_IMSCTLR, IMSCTLR_DISCACHE); 209 210 mmio_write_32(IPMMUDS0_IMSCTLR, IMSCTLR_DISCACHE); 211 mmio_write_32(IPMMUDS1_IMSCTLR, IMSCTLR_DISCACHE); 212 } 213 214 mmu: 215 mmio_write_32(IPMMUMM_IMSCTLR, IPMMUMM_IMSCTLR_ENABLE); 216 mmio_write_32(IPMMUMM_IMAUXCTLR, IPMMUMM_IMAUXCTLR_NMERGE40_BIT); 217 218 val = rcar_rom_get_lcs(&lcs); 219 if (val) { 220 ERROR("BL2: Failed to get the LCS. (%d)\n", val); 221 panic(); 222 } 223 224 if (lcs == LCS_SE) 225 mmio_clrbits_32(P_ARMREG_SEC_CTRL, P_ARMREG_SEC_CTRL_PROT); 226 227 rcar_swdt_release(); 228 bl2_system_cpg_init(); 229 230 #if RCAR_BL2_DCACHE == 1 231 /* Disable data cache (clean and invalidate) */ 232 disable_mmu_el3(); 233 #endif 234 } 235 236 static uint32_t is_ddr_backup_mode(void) 237 { 238 #if RCAR_SYSTEM_SUSPEND 239 static uint32_t reason = RCAR_COLD_BOOT; 240 static uint32_t once; 241 242 #if PMIC_ROHM_BD9571 && RCAR_SYSTEM_RESET_KEEPON_DDR 243 uint8_t data; 244 #endif 245 if (once) 246 return reason; 247 248 once = 1; 249 if ((mmio_read_32(GPIO_INDT) & GPIO_BKUP_TRG_SHIFT) == 0) 250 return reason; 251 252 #if PMIC_ROHM_BD9571 && RCAR_SYSTEM_RESET_KEEPON_DDR 253 if (rcar_iic_dvfs_receive(PMIC, REG_KEEP10, &data)) { 254 ERROR("BL2: REG Keep10 READ ERROR.\n"); 255 panic(); 256 } 257 258 if (KEEP10_MAGIC != data) 259 reason = RCAR_WARM_BOOT; 260 #else 261 reason = RCAR_WARM_BOOT; 262 #endif 263 return reason; 264 #else 265 return RCAR_COLD_BOOT; 266 #endif 267 } 268 269 int bl2_plat_handle_pre_image_load(unsigned int image_id) 270 { 271 u_register_t *boot_kind = (void *) BOOT_KIND_BASE; 272 bl_mem_params_node_t *bl_mem_params; 273 274 if (image_id != BL31_IMAGE_ID) 275 return 0; 276 277 bl_mem_params = get_bl_mem_params_node(image_id); 278 279 if (is_ddr_backup_mode() == RCAR_COLD_BOOT) 280 goto cold_boot; 281 282 *boot_kind = RCAR_WARM_BOOT; 283 flush_dcache_range(BOOT_KIND_BASE, sizeof(*boot_kind)); 284 285 console_flush(); 286 bl2_plat_flush_bl31_params(); 287 288 /* will not return */ 289 bl2_enter_bl31(&bl_mem_params->ep_info); 290 291 cold_boot: 292 *boot_kind = RCAR_COLD_BOOT; 293 flush_dcache_range(BOOT_KIND_BASE, sizeof(*boot_kind)); 294 295 return 0; 296 } 297 298 int bl2_plat_handle_post_image_load(unsigned int image_id) 299 { 300 static bl2_to_bl31_params_mem_t *params; 301 bl_mem_params_node_t *bl_mem_params; 302 303 if (!params) { 304 params = (bl2_to_bl31_params_mem_t *) PARAMS_BASE; 305 memset((void *)PARAMS_BASE, 0, sizeof(*params)); 306 } 307 308 bl_mem_params = get_bl_mem_params_node(image_id); 309 310 switch (image_id) { 311 case BL31_IMAGE_ID: 312 break; 313 case BL32_IMAGE_ID: 314 memcpy(¶ms->bl32_ep_info, &bl_mem_params->ep_info, 315 sizeof(entry_point_info_t)); 316 break; 317 case BL33_IMAGE_ID: 318 memcpy(¶ms->bl33_ep_info, &bl_mem_params->ep_info, 319 sizeof(entry_point_info_t)); 320 break; 321 } 322 323 return 0; 324 } 325 326 meminfo_t *bl2_plat_sec_mem_layout(void) 327 { 328 return &bl2_tzram_layout; 329 } 330 331 static void bl2_advertise_dram_entries(uint64_t dram_config[8]) 332 { 333 char nodename[32] = { 0 }; 334 uint64_t start, size; 335 uint64_t fdtsize; 336 int ret, node, chan; 337 338 for (chan = 0; chan < 4; chan++) { 339 start = dram_config[2 * chan]; 340 size = dram_config[2 * chan + 1]; 341 if (!size) 342 continue; 343 344 NOTICE("BL2: CH%d: %llx - %llx, %lld GiB\n", 345 chan, start, start + size - 1, size >> 30); 346 } 347 348 /* 349 * We add the DT nodes in reverse order here. The fdt_add_subnode() 350 * adds the DT node before the first existing DT node, so we have 351 * to add them in reverse order to get nodes sorted by address in 352 * the resulting DT. 353 */ 354 for (chan = 3; chan >= 0; chan--) { 355 start = dram_config[2 * chan]; 356 size = dram_config[2 * chan + 1]; 357 if (!size) 358 continue; 359 360 /* 361 * Channel 0 is mapped in 32bit space and the first 362 * 128 MiB are reserved 363 */ 364 if (chan == 0) { 365 start = 0x48000000; 366 size -= 0x8000000; 367 } 368 369 fdtsize = cpu_to_fdt64(size); 370 371 snprintf(nodename, sizeof(nodename), "memory@"); 372 unsigned_num_print(start, 16, nodename + strlen(nodename)); 373 node = ret = fdt_add_subnode(fdt, 0, nodename); 374 if (ret < 0) 375 goto err; 376 377 ret = fdt_setprop_string(fdt, node, "device_type", "memory"); 378 if (ret < 0) 379 goto err; 380 381 ret = fdt_setprop_u64(fdt, node, "reg", start); 382 if (ret < 0) 383 goto err; 384 385 ret = fdt_appendprop(fdt, node, "reg", &fdtsize, 386 sizeof(fdtsize)); 387 if (ret < 0) 388 goto err; 389 } 390 391 return; 392 err: 393 NOTICE("BL2: Cannot add memory node to FDT (ret=%i)\n", ret); 394 panic(); 395 } 396 397 static void bl2_advertise_dram_size(uint32_t product) 398 { 399 uint64_t dram_config[8] = { 400 [0] = 0x400000000ULL, 401 [2] = 0x500000000ULL, 402 [4] = 0x600000000ULL, 403 [6] = 0x700000000ULL, 404 }; 405 406 switch (product) { 407 case RCAR_PRODUCT_H3: 408 #if (RCAR_DRAM_LPDDR4_MEMCONF == 0) 409 /* 4GB(1GBx4) */ 410 dram_config[1] = 0x40000000ULL; 411 dram_config[3] = 0x40000000ULL; 412 dram_config[5] = 0x40000000ULL; 413 dram_config[7] = 0x40000000ULL; 414 #elif (RCAR_DRAM_LPDDR4_MEMCONF == 1) && \ 415 (RCAR_DRAM_CHANNEL == 5) && \ 416 (RCAR_DRAM_SPLIT == 2) 417 /* 4GB(2GBx2 2ch split) */ 418 dram_config[1] = 0x80000000ULL; 419 dram_config[3] = 0x80000000ULL; 420 #elif (RCAR_DRAM_LPDDR4_MEMCONF == 1) && (RCAR_DRAM_CHANNEL == 15) 421 /* 8GB(2GBx4: default) */ 422 dram_config[1] = 0x80000000ULL; 423 dram_config[3] = 0x80000000ULL; 424 dram_config[5] = 0x80000000ULL; 425 dram_config[7] = 0x80000000ULL; 426 #endif /* RCAR_DRAM_LPDDR4_MEMCONF == 0 */ 427 break; 428 429 case RCAR_PRODUCT_M3: 430 /* 4GB(2GBx2 2ch split) */ 431 dram_config[1] = 0x80000000ULL; 432 dram_config[5] = 0x80000000ULL; 433 break; 434 435 case RCAR_PRODUCT_M3N: 436 /* 2GB(1GBx2) */ 437 dram_config[1] = 0x80000000ULL; 438 break; 439 440 case RCAR_PRODUCT_E3: 441 #if (RCAR_DRAM_DDR3L_MEMCONF == 0) 442 /* 1GB(512MBx2) */ 443 dram_config[1] = 0x40000000ULL; 444 #elif (RCAR_DRAM_DDR3L_MEMCONF == 1) 445 /* 2GB(512MBx4) */ 446 dram_config[1] = 0x80000000ULL; 447 #elif (RCAR_DRAM_DDR3L_MEMCONF == 2) 448 /* 4GB(1GBx4) */ 449 dram_config[1] = 0x100000000ULL; 450 #endif /* RCAR_DRAM_DDR3L_MEMCONF == 0 */ 451 break; 452 } 453 454 bl2_advertise_dram_entries(dram_config); 455 } 456 457 void bl2_el3_early_platform_setup(u_register_t arg1, u_register_t arg2, 458 u_register_t arg3, u_register_t arg4) 459 { 460 uint32_t reg, midr, lcs, boot_dev, boot_cpu, sscg, type, rev; 461 uint32_t product, product_cut, major, minor; 462 int32_t ret; 463 const char *str; 464 const char *unknown = "unknown"; 465 const char *cpu_ca57 = "CA57"; 466 const char *cpu_ca53 = "CA53"; 467 const char *product_m3n = "M3N"; 468 const char *product_h3 = "H3"; 469 const char *product_m3 = "M3"; 470 const char *product_e3 = "E3"; 471 const char *lcs_secure = "SE"; 472 const char *lcs_cm = "CM"; 473 const char *lcs_dm = "DM"; 474 const char *lcs_sd = "SD"; 475 const char *lcs_fa = "FA"; 476 const char *sscg_off = "PLL1 nonSSCG Clock select"; 477 const char *sscg_on = "PLL1 SSCG Clock select"; 478 const char *boot_hyper80 = "HyperFlash(80MHz)"; 479 const char *boot_qspi40 = "QSPI Flash(40MHz)"; 480 const char *boot_qspi80 = "QSPI Flash(80MHz)"; 481 const char *boot_emmc25x1 = "eMMC(25MHz x1)"; 482 const char *boot_emmc50x8 = "eMMC(50MHz x8)"; 483 #if RCAR_LSI == RCAR_E3 484 const char *boot_hyper160 = "HyperFlash(150MHz)"; 485 #else 486 const char *boot_hyper160 = "HyperFlash(160MHz)"; 487 #endif 488 489 reg = mmio_read_32(RCAR_MODEMR); 490 boot_dev = reg & MODEMR_BOOT_DEV_MASK; 491 boot_cpu = reg & MODEMR_BOOT_CPU_MASK; 492 493 bl2_cpg_init(); 494 495 if (boot_cpu == MODEMR_BOOT_CPU_CA57 || 496 boot_cpu == MODEMR_BOOT_CPU_CA53) { 497 rcar_pfc_init(); 498 /* console configuration (platform specific) done in driver */ 499 console_init(0, 0, 0); 500 } 501 502 plat_rcar_gic_driver_init(); 503 plat_rcar_gic_init(); 504 rcar_swdt_init(); 505 506 /* FIQ interrupts are taken to EL3 */ 507 write_scr_el3(read_scr_el3() | SCR_FIQ_BIT); 508 509 write_daifclr(DAIF_FIQ_BIT); 510 511 reg = read_midr(); 512 midr = reg & (MIDR_PN_MASK << MIDR_PN_SHIFT); 513 switch (midr) { 514 case MIDR_CA57: 515 str = cpu_ca57; 516 break; 517 case MIDR_CA53: 518 str = cpu_ca53; 519 break; 520 default: 521 str = unknown; 522 break; 523 } 524 525 NOTICE("BL2: R-Car Gen3 Initial Program Loader(%s) Rev.%s\n", str, 526 version_of_renesas); 527 528 reg = mmio_read_32(RCAR_PRR); 529 product_cut = reg & (RCAR_PRODUCT_MASK | RCAR_CUT_MASK); 530 product = reg & RCAR_PRODUCT_MASK; 531 532 switch (product) { 533 case RCAR_PRODUCT_H3: 534 str = product_h3; 535 break; 536 case RCAR_PRODUCT_M3: 537 str = product_m3; 538 break; 539 case RCAR_PRODUCT_M3N: 540 str = product_m3n; 541 break; 542 case RCAR_PRODUCT_E3: 543 str = product_e3; 544 break; 545 default: 546 str = unknown; 547 break; 548 } 549 550 if (RCAR_PRODUCT_M3_CUT11 == product_cut) { 551 NOTICE("BL2: PRR is R-Car %s Ver.1.1 / Ver.1.2\n", str); 552 } else { 553 major = (reg & RCAR_MAJOR_MASK) >> RCAR_MAJOR_SHIFT; 554 major = major + RCAR_MAJOR_OFFSET; 555 minor = reg & RCAR_MINOR_MASK; 556 NOTICE("BL2: PRR is R-Car %s Ver.%d.%d\n", str, major, minor); 557 } 558 559 if (product == RCAR_PRODUCT_E3) { 560 reg = mmio_read_32(RCAR_MODEMR); 561 sscg = reg & RCAR_SSCG_MASK; 562 str = sscg == RCAR_SSCG_ENABLE ? sscg_on : sscg_off; 563 NOTICE("BL2: %s\n", str); 564 } 565 566 rcar_get_board_type(&type, &rev); 567 568 switch (type) { 569 case BOARD_SALVATOR_X: 570 case BOARD_KRIEK: 571 case BOARD_STARTER_KIT: 572 case BOARD_SALVATOR_XS: 573 case BOARD_EBISU: 574 case BOARD_STARTER_KIT_PRE: 575 case BOARD_EBISU_4D: 576 break; 577 default: 578 type = BOARD_UNKNOWN; 579 break; 580 } 581 582 if (type == BOARD_UNKNOWN || rev == BOARD_REV_UNKNOWN) 583 NOTICE("BL2: Board is %s Rev.---\n", GET_BOARD_NAME(type)); 584 else { 585 NOTICE("BL2: Board is %s Rev.%d.%d\n", 586 GET_BOARD_NAME(type), 587 GET_BOARD_MAJOR(rev), GET_BOARD_MINOR(rev)); 588 } 589 590 #if RCAR_LSI != RCAR_AUTO 591 if (product != TARGET_PRODUCT) { 592 ERROR("BL2: IPL was been built for the %s.\n", TARGET_NAME); 593 ERROR("BL2: Please write the correct IPL to flash memory.\n"); 594 panic(); 595 } 596 #endif 597 rcar_avs_init(); 598 rcar_avs_setting(); 599 600 switch (boot_dev) { 601 case MODEMR_BOOT_DEV_HYPERFLASH160: 602 str = boot_hyper160; 603 break; 604 case MODEMR_BOOT_DEV_HYPERFLASH80: 605 str = boot_hyper80; 606 break; 607 case MODEMR_BOOT_DEV_QSPI_FLASH40: 608 str = boot_qspi40; 609 break; 610 case MODEMR_BOOT_DEV_QSPI_FLASH80: 611 str = boot_qspi80; 612 break; 613 case MODEMR_BOOT_DEV_EMMC_25X1: 614 str = boot_emmc25x1; 615 break; 616 case MODEMR_BOOT_DEV_EMMC_50X8: 617 str = boot_emmc50x8; 618 break; 619 default: 620 str = unknown; 621 break; 622 } 623 NOTICE("BL2: Boot device is %s\n", str); 624 625 rcar_avs_setting(); 626 reg = rcar_rom_get_lcs(&lcs); 627 if (reg) { 628 str = unknown; 629 goto lcm_state; 630 } 631 632 switch (lcs) { 633 case LCS_CM: 634 str = lcs_cm; 635 break; 636 case LCS_DM: 637 str = lcs_dm; 638 break; 639 case LCS_SD: 640 str = lcs_sd; 641 break; 642 case LCS_SE: 643 str = lcs_secure; 644 break; 645 case LCS_FA: 646 str = lcs_fa; 647 break; 648 default: 649 str = unknown; 650 break; 651 } 652 653 lcm_state: 654 NOTICE("BL2: LCM state is %s\n", str); 655 656 rcar_avs_end(); 657 is_ddr_backup_mode(); 658 659 bl2_tzram_layout.total_base = BL31_BASE; 660 bl2_tzram_layout.total_size = BL31_LIMIT - BL31_BASE; 661 662 if (boot_cpu == MODEMR_BOOT_CPU_CA57 || 663 boot_cpu == MODEMR_BOOT_CPU_CA53) { 664 ret = rcar_dram_init(); 665 if (ret) { 666 NOTICE("BL2: Failed to DRAM initialize (%d).\n", ret); 667 panic(); 668 } 669 rcar_qos_init(); 670 } 671 672 /* Set up FDT */ 673 ret = fdt_create_empty_tree(fdt, sizeof(fdt_blob)); 674 if (ret) { 675 NOTICE("BL2: Cannot allocate FDT for U-Boot (ret=%i)\n", ret); 676 panic(); 677 } 678 679 /* Print DRAM layout */ 680 bl2_advertise_dram_size(product); 681 682 if (boot_dev == MODEMR_BOOT_DEV_EMMC_25X1 || 683 boot_dev == MODEMR_BOOT_DEV_EMMC_50X8) { 684 if (rcar_emmc_init() != EMMC_SUCCESS) { 685 NOTICE("BL2: Failed to eMMC driver initialize.\n"); 686 panic(); 687 } 688 rcar_emmc_memcard_power(EMMC_POWER_ON); 689 if (rcar_emmc_mount() != EMMC_SUCCESS) { 690 NOTICE("BL2: Failed to eMMC mount operation.\n"); 691 panic(); 692 } 693 } else { 694 rcar_rpc_init(); 695 rcar_dma_init(); 696 } 697 698 reg = mmio_read_32(RST_WDTRSTCR); 699 reg &= ~WDTRSTCR_RWDT_RSTMSK; 700 reg |= WDTRSTCR_PASSWORD; 701 mmio_write_32(RST_WDTRSTCR, reg); 702 703 mmio_write_32(CPG_CPGWPR, CPGWPR_PASSWORD); 704 mmio_write_32(CPG_CPGWPCR, CPGWPCR_PASSWORD); 705 706 reg = mmio_read_32(RCAR_PRR); 707 if ((reg & RCAR_CPU_MASK_CA57) == RCAR_CPU_HAVE_CA57) 708 mmio_write_32(CPG_CA57DBGRCR, 709 DBGCPUPREN | mmio_read_32(CPG_CA57DBGRCR)); 710 711 if ((reg & RCAR_CPU_MASK_CA53) == RCAR_CPU_HAVE_CA53) 712 mmio_write_32(CPG_CA53DBGRCR, 713 DBGCPUPREN | mmio_read_32(CPG_CA53DBGRCR)); 714 715 if (product_cut == RCAR_PRODUCT_H3_CUT10) { 716 reg = mmio_read_32(CPG_PLL2CR); 717 reg &= ~((uint32_t) 1 << 5); 718 mmio_write_32(CPG_PLL2CR, reg); 719 720 reg = mmio_read_32(CPG_PLL4CR); 721 reg &= ~((uint32_t) 1 << 5); 722 mmio_write_32(CPG_PLL4CR, reg); 723 724 reg = mmio_read_32(CPG_PLL0CR); 725 reg &= ~((uint32_t) 1 << 12); 726 mmio_write_32(CPG_PLL0CR, reg); 727 } 728 #if (RCAR_LOSSY_ENABLE == 1) 729 NOTICE("BL2: Lossy Decomp areas\n"); 730 bl2_lossy_setting(0, LOSSY_ST_ADDR0, LOSSY_END_ADDR0, 731 LOSSY_FMT0, LOSSY_ENA_DIS0); 732 bl2_lossy_setting(1, LOSSY_ST_ADDR1, LOSSY_END_ADDR1, 733 LOSSY_FMT1, LOSSY_ENA_DIS1); 734 bl2_lossy_setting(2, LOSSY_ST_ADDR2, LOSSY_END_ADDR2, 735 LOSSY_FMT2, LOSSY_ENA_DIS2); 736 #endif 737 738 fdt_pack(fdt); 739 NOTICE("BL2: FDT at %p\n", fdt); 740 741 if (boot_dev == MODEMR_BOOT_DEV_EMMC_25X1 || 742 boot_dev == MODEMR_BOOT_DEV_EMMC_50X8) 743 rcar_io_emmc_setup(); 744 else 745 rcar_io_setup(); 746 } 747 748 void bl2_el3_plat_arch_setup(void) 749 { 750 #if RCAR_BL2_DCACHE == 1 751 NOTICE("BL2: D-Cache enable\n"); 752 rcar_configure_mmu_el3(BL2_BASE, 753 RCAR_SYSRAM_LIMIT - BL2_BASE, 754 BL2_RO_BASE, BL2_RO_LIMIT 755 #if USE_COHERENT_MEM 756 , BL2_COHERENT_RAM_BASE, BL2_COHERENT_RAM_LIMIT 757 #endif 758 ); 759 #endif 760 } 761 762 void bl2_platform_setup(void) 763 { 764 765 } 766