1 /* 2 * Copyright (c) 2018, Renesas Electronics Corporation. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <desc_image_load.h> 8 #include <arch_helpers.h> 9 #include <bl_common.h> 10 #include <bl1.h> 11 #include <console.h> 12 #include <debug.h> 13 #include <mmio.h> 14 #include <platform.h> 15 #include <platform_def.h> 16 #include <string.h> 17 18 #include "avs_driver.h" 19 #include "boot_init_dram.h" 20 #include "cpg_registers.h" 21 #include "board.h" 22 #include "emmc_def.h" 23 #include "emmc_hal.h" 24 #include "emmc_std.h" 25 26 #if PMIC_ROHM_BD9571 && RCAR_SYSTEM_RESET_KEEPON_DDR 27 #include "iic_dvfs.h" 28 #endif 29 30 #include "io_common.h" 31 #include "qos_init.h" 32 #include "rcar_def.h" 33 #include "rcar_private.h" 34 #include "rcar_version.h" 35 #include "rom_api.h" 36 37 IMPORT_SYM(unsigned long, __RO_START__, BL2_RO_BASE) 38 IMPORT_SYM(unsigned long, __RO_END__, BL2_RO_LIMIT) 39 40 #if USE_COHERENT_MEM 41 IMPORT_SYM(unsigned long, __COHERENT_RAM_START__, BL2_COHERENT_RAM_BASE) 42 IMPORT_SYM(unsigned long, __COHERENT_RAM_END__, BL2_COHERENT_RAM_LIMIT) 43 #endif 44 45 extern void plat_rcar_gic_driver_init(void); 46 extern void plat_rcar_gic_init(void); 47 extern void bl2_enter_bl31(const struct entry_point_info *bl_ep_info); 48 extern void bl2_system_cpg_init(void); 49 extern void bl2_secure_setting(void); 50 extern void bl2_cpg_init(void); 51 extern void rcar_io_emmc_setup(void); 52 extern void rcar_io_setup(void); 53 extern void rcar_swdt_release(void); 54 extern void rcar_swdt_init(void); 55 extern void rcar_rpc_init(void); 56 extern void rcar_pfc_init(void); 57 extern void rcar_dma_init(void); 58 59 /* R-Car Gen3 product check */ 60 #if (RCAR_LSI == RCAR_H3) || (RCAR_LSI == RCAR_H3N) 61 #define TARGET_PRODUCT RCAR_PRODUCT_H3 62 #define TARGET_NAME "R-Car H3" 63 #elif RCAR_LSI == RCAR_M3 64 #define TARGET_PRODUCT RCAR_PRODUCT_M3 65 #define TARGET_NAME "R-Car M3" 66 #elif RCAR_LSI == RCAR_M3N 67 #define TARGET_PRODUCT RCAR_PRODUCT_M3N 68 #define TARGET_NAME "R-Car M3N" 69 #elif RCAR_LSI == RCAR_E3 70 #define TARGET_PRODUCT RCAR_PRODUCT_E3 71 #define TARGET_NAME "R-Car E3" 72 #endif 73 74 #if (RCAR_LSI == RCAR_E3) 75 #define GPIO_INDT (GPIO_INDT6) 76 #define GPIO_BKUP_TRG_SHIFT ((uint32_t)1U<<13U) 77 #else 78 #define GPIO_INDT (GPIO_INDT1) 79 #define GPIO_BKUP_TRG_SHIFT ((uint32_t)1U<<8U) 80 #endif 81 82 CASSERT((PARAMS_BASE + sizeof(bl2_to_bl31_params_mem_t) + 0x100) 83 < (RCAR_SHARED_MEM_BASE + RCAR_SHARED_MEM_SIZE), 84 assert_bl31_params_do_not_fit_in_shared_memory); 85 86 static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE); 87 88 #if (RCAR_LOSSY_ENABLE == 1) 89 typedef struct bl2_lossy_info { 90 uint32_t magic; 91 uint32_t a0; 92 uint32_t b0; 93 } bl2_lossy_info_t; 94 95 static void bl2_lossy_setting(uint32_t no, uint64_t start_addr, 96 uint64_t end_addr, uint32_t format, 97 uint32_t enable) 98 { 99 bl2_lossy_info_t info; 100 uint32_t reg; 101 102 reg = format | (start_addr >> 20); 103 mmio_write_32(AXI_DCMPAREACRA0 + 0x8 * no, reg); 104 mmio_write_32(AXI_DCMPAREACRB0 + 0x8 * no, end_addr >> 20); 105 mmio_write_32(AXI_DCMPAREACRA0 + 0x8 * no, reg | enable); 106 107 info.magic = 0x12345678U; 108 info.a0 = mmio_read_32(AXI_DCMPAREACRA0 + 0x8 * no); 109 info.b0 = mmio_read_32(AXI_DCMPAREACRB0 + 0x8 * no); 110 111 mmio_write_32(LOSSY_PARAMS_BASE + sizeof(info) * no, info.magic); 112 mmio_write_32(LOSSY_PARAMS_BASE + sizeof(info) * no + 0x4, info.a0); 113 mmio_write_32(LOSSY_PARAMS_BASE + sizeof(info) * no + 0x8, info.b0); 114 115 NOTICE(" Entry %d: DCMPAREACRAx:0x%x DCMPAREACRBx:0x%x\n", no, 116 mmio_read_32(AXI_DCMPAREACRA0 + 0x8 * no), 117 mmio_read_32(AXI_DCMPAREACRB0 + 0x8 * no)); 118 } 119 #endif 120 121 void bl2_plat_flush_bl31_params(void) 122 { 123 uint32_t product_cut, product, cut; 124 uint32_t boot_dev, boot_cpu; 125 uint32_t lcs, reg, val; 126 127 reg = mmio_read_32(RCAR_MODEMR); 128 boot_dev = reg & MODEMR_BOOT_DEV_MASK; 129 130 if (boot_dev == MODEMR_BOOT_DEV_EMMC_25X1 || 131 boot_dev == MODEMR_BOOT_DEV_EMMC_50X8) 132 emmc_terminate(); 133 134 if ((reg & MODEMR_BOOT_CPU_MASK) != MODEMR_BOOT_CPU_CR7) 135 bl2_secure_setting(); 136 137 reg = mmio_read_32(RCAR_PRR); 138 product_cut = reg & (RCAR_PRODUCT_MASK | RCAR_CUT_MASK); 139 product = reg & RCAR_PRODUCT_MASK; 140 cut = reg & RCAR_CUT_MASK; 141 142 if (product == RCAR_PRODUCT_M3) 143 goto tlb; 144 145 if (product == RCAR_PRODUCT_H3 && RCAR_CUT_VER20 > cut) 146 goto tlb; 147 148 /* Disable MFIS write protection */ 149 mmio_write_32(MFISWPCNTR, MFISWPCNTR_PASSWORD | 1); 150 151 tlb: 152 reg = mmio_read_32(RCAR_MODEMR); 153 boot_cpu = reg & MODEMR_BOOT_CPU_MASK; 154 if (boot_cpu != MODEMR_BOOT_CPU_CA57 && 155 boot_cpu != MODEMR_BOOT_CPU_CA53) 156 goto mmu; 157 158 if (product_cut == RCAR_PRODUCT_H3_CUT20) { 159 mmio_write_32(IPMMUVI0_IMSCTLR, IMSCTLR_DISCACHE); 160 mmio_write_32(IPMMUVI1_IMSCTLR, IMSCTLR_DISCACHE); 161 mmio_write_32(IPMMUPV0_IMSCTLR, IMSCTLR_DISCACHE); 162 mmio_write_32(IPMMUPV1_IMSCTLR, IMSCTLR_DISCACHE); 163 mmio_write_32(IPMMUPV2_IMSCTLR, IMSCTLR_DISCACHE); 164 mmio_write_32(IPMMUPV3_IMSCTLR, IMSCTLR_DISCACHE); 165 } else if (product_cut == (RCAR_PRODUCT_M3N | RCAR_CUT_VER10) || 166 product_cut == (RCAR_PRODUCT_M3N | RCAR_CUT_VER11)) { 167 mmio_write_32(IPMMUVI0_IMSCTLR, IMSCTLR_DISCACHE); 168 mmio_write_32(IPMMUPV0_IMSCTLR, IMSCTLR_DISCACHE); 169 } else if (product_cut == (RCAR_PRODUCT_E3 | RCAR_CUT_VER10)) { 170 mmio_write_32(IPMMUVI0_IMSCTLR, IMSCTLR_DISCACHE); 171 mmio_write_32(IPMMUPV0_IMSCTLR, IMSCTLR_DISCACHE); 172 } 173 174 if (product_cut == (RCAR_PRODUCT_H3_CUT20) || 175 product_cut == (RCAR_PRODUCT_M3N | RCAR_CUT_VER10) || 176 product_cut == (RCAR_PRODUCT_M3N | RCAR_CUT_VER11) || 177 product_cut == (RCAR_PRODUCT_E3 | RCAR_CUT_VER10)) { 178 mmio_write_32(IPMMUHC_IMSCTLR, IMSCTLR_DISCACHE); 179 mmio_write_32(IPMMURT_IMSCTLR, IMSCTLR_DISCACHE); 180 mmio_write_32(IPMMUMP_IMSCTLR, IMSCTLR_DISCACHE); 181 182 mmio_write_32(IPMMUDS0_IMSCTLR, IMSCTLR_DISCACHE); 183 mmio_write_32(IPMMUDS1_IMSCTLR, IMSCTLR_DISCACHE); 184 } 185 186 mmu: 187 mmio_write_32(IPMMUMM_IMSCTLR, IPMMUMM_IMSCTLR_ENABLE); 188 mmio_write_32(IPMMUMM_IMAUXCTLR, IPMMUMM_IMAUXCTLR_NMERGE40_BIT); 189 190 val = rcar_rom_get_lcs(&lcs); 191 if (val) { 192 ERROR("BL2: Failed to get the LCS. (%d)\n", val); 193 panic(); 194 } 195 196 if (lcs == LCS_SE) 197 mmio_clrbits_32(P_ARMREG_SEC_CTRL, P_ARMREG_SEC_CTRL_PROT); 198 199 rcar_swdt_release(); 200 bl2_system_cpg_init(); 201 202 #if RCAR_BL2_DCACHE == 1 203 /* Disable data cache (clean and invalidate) */ 204 disable_mmu_el3(); 205 #endif 206 } 207 208 static uint32_t is_ddr_backup_mode(void) 209 { 210 #if RCAR_SYSTEM_SUSPEND 211 static uint32_t reason = RCAR_COLD_BOOT; 212 static uint32_t once; 213 214 #if PMIC_ROHM_BD9571 && RCAR_SYSTEM_RESET_KEEPON_DDR 215 uint8_t data; 216 #endif 217 if (once) 218 return reason; 219 220 once = 1; 221 if ((mmio_read_32(GPIO_INDT) & GPIO_BKUP_TRG_SHIFT) == 0) 222 return reason; 223 224 #if PMIC_ROHM_BD9571 && RCAR_SYSTEM_RESET_KEEPON_DDR 225 if (rcar_iic_dvfs_receive(PMIC, REG_KEEP10, &data)) { 226 ERROR("BL2: REG Keep10 READ ERROR.\n"); 227 panic(); 228 } 229 230 if (KEEP10_MAGIC != data) 231 reason = RCAR_WARM_BOOT; 232 #else 233 reason = RCAR_WARM_BOOT; 234 #endif 235 return reason; 236 #else 237 return RCAR_COLD_BOOT; 238 #endif 239 } 240 241 int bl2_plat_handle_pre_image_load(unsigned int image_id) 242 { 243 u_register_t *boot_kind = (void *) BOOT_KIND_BASE; 244 bl_mem_params_node_t *bl_mem_params; 245 246 if (image_id != BL31_IMAGE_ID) 247 return 0; 248 249 bl_mem_params = get_bl_mem_params_node(image_id); 250 251 if (is_ddr_backup_mode() == RCAR_COLD_BOOT) 252 goto cold_boot; 253 254 *boot_kind = RCAR_WARM_BOOT; 255 flush_dcache_range(BOOT_KIND_BASE, sizeof(*boot_kind)); 256 257 console_flush(); 258 bl2_plat_flush_bl31_params(); 259 260 /* will not return */ 261 bl2_enter_bl31(&bl_mem_params->ep_info); 262 263 cold_boot: 264 *boot_kind = RCAR_COLD_BOOT; 265 flush_dcache_range(BOOT_KIND_BASE, sizeof(*boot_kind)); 266 267 return 0; 268 } 269 270 int bl2_plat_handle_post_image_load(unsigned int image_id) 271 { 272 static bl2_to_bl31_params_mem_t *params; 273 bl_mem_params_node_t *bl_mem_params; 274 275 if (!params) { 276 params = (bl2_to_bl31_params_mem_t *) PARAMS_BASE; 277 memset((void *)PARAMS_BASE, 0, sizeof(*params)); 278 } 279 280 bl_mem_params = get_bl_mem_params_node(image_id); 281 282 switch (image_id) { 283 case BL31_IMAGE_ID: 284 break; 285 case BL32_IMAGE_ID: 286 memcpy(¶ms->bl32_ep_info, &bl_mem_params->ep_info, 287 sizeof(entry_point_info_t)); 288 break; 289 case BL33_IMAGE_ID: 290 memcpy(¶ms->bl33_ep_info, &bl_mem_params->ep_info, 291 sizeof(entry_point_info_t)); 292 break; 293 } 294 295 return 0; 296 } 297 298 meminfo_t *bl2_plat_sec_mem_layout(void) 299 { 300 return &bl2_tzram_layout; 301 } 302 303 static void bl2_advertise_dram_size(uint32_t product, uint32_t cut) 304 { 305 /* Later than H3 Ver.3.0 */ 306 if (product == RCAR_PRODUCT_H3 && cut >= RCAR_CUT_VER30) { 307 #if (RCAR_DRAM_LPDDR4_MEMCONF == 0) 308 /* 4GB(1GBx4) */ 309 NOTICE("BL2: CH0: 0x400000000 - 0x43fffffff, 1 GiB\n"); 310 NOTICE("BL2: CH1: 0x500000000 - 0x53fffffff, 1 GiB\n"); 311 NOTICE("BL2: CH2: 0x600000000 - 0x63fffffff, 1 GiB\n"); 312 NOTICE("BL2: CH3: 0x700000000 - 0x73fffffff, 1 GiB\n"); 313 #elif (RCAR_DRAM_LPDDR4_MEMCONF == 1) && \ 314 (RCAR_DRAM_CHANNEL == 5) && \ 315 (RCAR_DRAM_SPLIT == 2) 316 /* 4GB(2GBx2 2ch split) */ 317 NOTICE("BL2: CH0: 0x400000000 - 0x47fffffff, 2 GiB\n"); 318 NOTICE("BL2: CH1: 0x500000000 - 0x57fffffff, 2 GiB\n"); 319 #elif (RCAR_DRAM_LPDDR4_MEMCONF == 1) && (RCAR_DRAM_CHANNEL == 15) 320 /* 8GB(2GBx4: default) */ 321 NOTICE("BL2: CH0: 0x400000000 - 0x47fffffff, 2 GiB\n"); 322 NOTICE("BL2: CH1: 0x500000000 - 0x57fffffff, 2 GiB\n"); 323 NOTICE("BL2: CH2: 0x600000000 - 0x67fffffff, 2 GiB\n"); 324 NOTICE("BL2: CH3: 0x700000000 - 0x77fffffff, 2 GiB\n"); 325 #endif /* RCAR_DRAM_LPDDR4_MEMCONF == 0 */ 326 } 327 328 if (product == RCAR_PRODUCT_E3) { 329 #if (RCAR_DRAM_DDR3L_MEMCONF == 0) 330 /* 1GB(512MBx2) */ 331 NOTICE("BL2: 0x400000000 - 0x43fffffff, 1 GiB\n"); 332 #elif (RCAR_DRAM_DDR3L_MEMCONF == 1) 333 /* 2GB(512MBx4) */ 334 NOTICE("BL2: 0x400000000 - 0x47fffffff, 2 GiB\n"); 335 #elif (RCAR_DRAM_DDR3L_MEMCONF == 2) 336 /* 4GB(1GBx4) */ 337 NOTICE("BL2: 0x400000000 - 0x4ffffffff, 4 GiB\n"); 338 #endif /* RCAR_DRAM_DDR3L_MEMCONF == 0 */ 339 } 340 } 341 342 void bl2_el3_early_platform_setup(u_register_t arg1, u_register_t arg2, 343 u_register_t arg3, u_register_t arg4) 344 { 345 uint32_t reg, midr, lcs, boot_dev, boot_cpu, sscg, type, rev; 346 uint32_t cut, product, product_cut, major, minor; 347 int32_t ret; 348 const char *str; 349 const char *unknown = "unknown"; 350 const char *cpu_ca57 = "CA57"; 351 const char *cpu_ca53 = "CA53"; 352 const char *product_m3n = "M3N"; 353 const char *product_h3 = "H3"; 354 const char *product_m3 = "M3"; 355 const char *product_e3 = "E3"; 356 const char *lcs_secure = "SE"; 357 const char *lcs_cm = "CM"; 358 const char *lcs_dm = "DM"; 359 const char *lcs_sd = "SD"; 360 const char *lcs_fa = "FA"; 361 const char *sscg_off = "PLL1 nonSSCG Clock select"; 362 const char *sscg_on = "PLL1 SSCG Clock select"; 363 const char *boot_hyper80 = "HyperFlash(80MHz)"; 364 const char *boot_qspi40 = "QSPI Flash(40MHz)"; 365 const char *boot_qspi80 = "QSPI Flash(80MHz)"; 366 const char *boot_emmc25x1 = "eMMC(25MHz x1)"; 367 const char *boot_emmc50x8 = "eMMC(50MHz x8)"; 368 #if RCAR_LSI == RCAR_E3 369 const char *boot_hyper160 = "HyperFlash(150MHz)"; 370 #else 371 const char *boot_hyper160 = "HyperFlash(160MHz)"; 372 #endif 373 374 reg = mmio_read_32(RCAR_MODEMR); 375 boot_dev = reg & MODEMR_BOOT_DEV_MASK; 376 boot_cpu = reg & MODEMR_BOOT_CPU_MASK; 377 378 bl2_cpg_init(); 379 380 if (boot_cpu == MODEMR_BOOT_CPU_CA57 || 381 boot_cpu == MODEMR_BOOT_CPU_CA53) { 382 rcar_pfc_init(); 383 /* console configuration (platform specific) done in driver */ 384 console_init(0, 0, 0); 385 } 386 387 plat_rcar_gic_driver_init(); 388 plat_rcar_gic_init(); 389 rcar_swdt_init(); 390 391 /* FIQ interrupts are taken to EL3 */ 392 write_scr_el3(read_scr_el3() | SCR_FIQ_BIT); 393 394 write_daifclr(DAIF_FIQ_BIT); 395 396 reg = read_midr(); 397 midr = reg & (MIDR_PN_MASK << MIDR_PN_SHIFT); 398 switch (midr) { 399 case MIDR_CA57: 400 str = cpu_ca57; 401 break; 402 case MIDR_CA53: 403 str = cpu_ca53; 404 break; 405 default: 406 str = unknown; 407 break; 408 } 409 410 NOTICE("BL2: R-Car Gen3 Initial Program Loader(%s) Rev.%s\n", str, 411 version_of_renesas); 412 413 reg = mmio_read_32(RCAR_PRR); 414 product_cut = reg & (RCAR_PRODUCT_MASK | RCAR_CUT_MASK); 415 product = reg & RCAR_PRODUCT_MASK; 416 cut = reg & RCAR_CUT_MASK; 417 418 switch (product) { 419 case RCAR_PRODUCT_H3: 420 str = product_h3; 421 break; 422 case RCAR_PRODUCT_M3: 423 str = product_m3; 424 break; 425 case RCAR_PRODUCT_M3N: 426 str = product_m3n; 427 break; 428 case RCAR_PRODUCT_E3: 429 str = product_e3; 430 break; 431 default: 432 str = unknown; 433 break; 434 } 435 436 if (RCAR_PRODUCT_M3_CUT11 == product_cut) { 437 NOTICE("BL2: PRR is R-Car %s Ver.1.1 / Ver.1.2\n", str); 438 } else { 439 major = (reg & RCAR_MAJOR_MASK) >> RCAR_MAJOR_SHIFT; 440 major = major + RCAR_MAJOR_OFFSET; 441 minor = reg & RCAR_MINOR_MASK; 442 NOTICE("BL2: PRR is R-Car %s Ver.%d.%d\n", str, major, minor); 443 } 444 445 if (product == RCAR_PRODUCT_E3) { 446 reg = mmio_read_32(RCAR_MODEMR); 447 sscg = reg & RCAR_SSCG_MASK; 448 str = sscg == RCAR_SSCG_ENABLE ? sscg_on : sscg_off; 449 NOTICE("BL2: %s\n", str); 450 } 451 452 rcar_get_board_type(&type, &rev); 453 454 switch (type) { 455 case BOARD_SALVATOR_X: 456 case BOARD_KRIEK: 457 case BOARD_STARTER_KIT: 458 case BOARD_SALVATOR_XS: 459 case BOARD_EBISU: 460 case BOARD_STARTER_KIT_PRE: 461 case BOARD_EBISU_4D: 462 break; 463 default: 464 type = BOARD_UNKNOWN; 465 break; 466 } 467 468 if (type == BOARD_UNKNOWN || rev == BOARD_REV_UNKNOWN) 469 NOTICE("BL2: Board is %s Rev.---\n", GET_BOARD_NAME(type)); 470 else { 471 NOTICE("BL2: Board is %s Rev.%d.%d\n", 472 GET_BOARD_NAME(type), 473 GET_BOARD_MAJOR(rev), GET_BOARD_MINOR(rev)); 474 } 475 476 #if RCAR_LSI != RCAR_AUTO 477 if (product != TARGET_PRODUCT) { 478 ERROR("BL2: IPL was been built for the %s.\n", TARGET_NAME); 479 ERROR("BL2: Please write the correct IPL to flash memory.\n"); 480 panic(); 481 } 482 #endif 483 rcar_avs_init(); 484 rcar_avs_setting(); 485 486 switch (boot_dev) { 487 case MODEMR_BOOT_DEV_HYPERFLASH160: 488 str = boot_hyper160; 489 break; 490 case MODEMR_BOOT_DEV_HYPERFLASH80: 491 str = boot_hyper80; 492 break; 493 case MODEMR_BOOT_DEV_QSPI_FLASH40: 494 str = boot_qspi40; 495 break; 496 case MODEMR_BOOT_DEV_QSPI_FLASH80: 497 str = boot_qspi80; 498 break; 499 case MODEMR_BOOT_DEV_EMMC_25X1: 500 str = boot_emmc25x1; 501 break; 502 case MODEMR_BOOT_DEV_EMMC_50X8: 503 str = boot_emmc50x8; 504 break; 505 default: 506 str = unknown; 507 break; 508 } 509 NOTICE("BL2: Boot device is %s\n", str); 510 511 rcar_avs_setting(); 512 reg = rcar_rom_get_lcs(&lcs); 513 if (reg) { 514 str = unknown; 515 goto lcm_state; 516 } 517 518 switch (lcs) { 519 case LCS_CM: 520 str = lcs_cm; 521 break; 522 case LCS_DM: 523 str = lcs_dm; 524 break; 525 case LCS_SD: 526 str = lcs_sd; 527 break; 528 case LCS_SE: 529 str = lcs_secure; 530 break; 531 case LCS_FA: 532 str = lcs_fa; 533 break; 534 default: 535 str = unknown; 536 break; 537 } 538 539 lcm_state: 540 NOTICE("BL2: LCM state is %s\n", str); 541 542 rcar_avs_end(); 543 is_ddr_backup_mode(); 544 545 bl2_tzram_layout.total_base = BL31_BASE; 546 bl2_tzram_layout.total_size = BL31_LIMIT - BL31_BASE; 547 548 /* Print DRAM layout */ 549 bl2_advertise_dram_size(product, cut); 550 551 if (boot_cpu == MODEMR_BOOT_CPU_CA57 || 552 boot_cpu == MODEMR_BOOT_CPU_CA53) { 553 ret = rcar_dram_init(); 554 if (ret) { 555 NOTICE("BL2: Failed to DRAM initialize (%d).\n", ret); 556 panic(); 557 } 558 rcar_qos_init(); 559 } 560 561 if (boot_dev == MODEMR_BOOT_DEV_EMMC_25X1 || 562 boot_dev == MODEMR_BOOT_DEV_EMMC_50X8) { 563 if (rcar_emmc_init() != EMMC_SUCCESS) { 564 NOTICE("BL2: Failed to eMMC driver initialize.\n"); 565 panic(); 566 } 567 rcar_emmc_memcard_power(EMMC_POWER_ON); 568 if (rcar_emmc_mount() != EMMC_SUCCESS) { 569 NOTICE("BL2: Failed to eMMC mount operation.\n"); 570 panic(); 571 } 572 } else { 573 rcar_rpc_init(); 574 rcar_dma_init(); 575 } 576 577 reg = mmio_read_32(RST_WDTRSTCR); 578 reg &= ~WDTRSTCR_RWDT_RSTMSK; 579 reg |= WDTRSTCR_PASSWORD; 580 mmio_write_32(RST_WDTRSTCR, reg); 581 582 mmio_write_32(CPG_CPGWPR, CPGWPR_PASSWORD); 583 mmio_write_32(CPG_CPGWPCR, CPGWPCR_PASSWORD); 584 585 reg = mmio_read_32(RCAR_PRR); 586 if ((reg & RCAR_CPU_MASK_CA57) == RCAR_CPU_HAVE_CA57) 587 mmio_write_32(CPG_CA57DBGRCR, 588 DBGCPUPREN | mmio_read_32(CPG_CA57DBGRCR)); 589 590 if ((reg & RCAR_CPU_MASK_CA53) == RCAR_CPU_HAVE_CA53) 591 mmio_write_32(CPG_CA53DBGRCR, 592 DBGCPUPREN | mmio_read_32(CPG_CA53DBGRCR)); 593 594 if (product_cut == RCAR_PRODUCT_H3_CUT10) { 595 reg = mmio_read_32(CPG_PLL2CR); 596 reg &= ~((uint32_t) 1 << 5); 597 mmio_write_32(CPG_PLL2CR, reg); 598 599 reg = mmio_read_32(CPG_PLL4CR); 600 reg &= ~((uint32_t) 1 << 5); 601 mmio_write_32(CPG_PLL4CR, reg); 602 603 reg = mmio_read_32(CPG_PLL0CR); 604 reg &= ~((uint32_t) 1 << 12); 605 mmio_write_32(CPG_PLL0CR, reg); 606 } 607 #if (RCAR_LOSSY_ENABLE == 1) 608 NOTICE("BL2: Lossy Decomp areas\n"); 609 bl2_lossy_setting(0, LOSSY_ST_ADDR0, LOSSY_END_ADDR0, 610 LOSSY_FMT0, LOSSY_ENA_DIS0); 611 bl2_lossy_setting(1, LOSSY_ST_ADDR1, LOSSY_END_ADDR1, 612 LOSSY_FMT1, LOSSY_ENA_DIS1); 613 bl2_lossy_setting(2, LOSSY_ST_ADDR2, LOSSY_END_ADDR2, 614 LOSSY_FMT2, LOSSY_ENA_DIS2); 615 #endif 616 617 if (boot_dev == MODEMR_BOOT_DEV_EMMC_25X1 || 618 boot_dev == MODEMR_BOOT_DEV_EMMC_50X8) 619 rcar_io_emmc_setup(); 620 else 621 rcar_io_setup(); 622 } 623 624 void bl2_el3_plat_arch_setup(void) 625 { 626 #if RCAR_BL2_DCACHE == 1 627 NOTICE("BL2: D-Cache enable\n"); 628 rcar_configure_mmu_el3(BL2_BASE, 629 RCAR_SYSRAM_LIMIT - BL2_BASE, 630 BL2_RO_BASE, BL2_RO_LIMIT 631 #if USE_COHERENT_MEM 632 , BL2_COHERENT_RAM_BASE, BL2_COHERENT_RAM_LIMIT 633 #endif 634 ); 635 #endif 636 } 637 638 void bl2_platform_setup(void) 639 { 640 641 } 642