1 /* 2 * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch_helpers.h> 8 #include <assert.h> 9 #include <bl_common.h> 10 #include <console.h> 11 #include <context.h> 12 #include <context_mgmt.h> 13 #include <debug.h> 14 #include <gpc.h> 15 #include <imx_uart.h> 16 #include <stdbool.h> 17 #include <mmio.h> 18 #include <platform.h> 19 #include <platform_def.h> 20 #include <plat_imx8.h> 21 #include <xlat_tables.h> 22 #include <tzc380.h> 23 24 IMPORT_SYM(uintptr_t, __COHERENT_RAM_START__, BL31_COHERENT_RAM_START); 25 IMPORT_SYM(uintptr_t, __COHERENT_RAM_END__, BL31_COHERENT_RAM_END); 26 IMPORT_SYM(uintptr_t, __RO_START__, BL31_RO_START); 27 IMPORT_SYM(uintptr_t, __RO_END__, BL31_RO_END); 28 IMPORT_SYM(uintptr_t, __RW_START__, BL31_RW_START); 29 IMPORT_SYM(uintptr_t, __RW_END__, BL31_RW_END); 30 31 static const mmap_region_t imx_mmap[] = { 32 MAP_REGION_FLAT(GPV_BASE, GPV_SIZE, MT_DEVICE | MT_RW), /* GPV map */ 33 MAP_REGION_FLAT(IMX_AIPS_BASE, IMX_AIPS_SIZE, MT_DEVICE | MT_RW), /* AIPS map */ 34 MAP_REGION_FLAT(IMX_GIC_BASE, IMX_GIC_SIZE, MT_DEVICE | MT_RW), /* GIC map */ 35 {0}, 36 }; 37 38 static entry_point_info_t bl32_image_ep_info; 39 static entry_point_info_t bl33_image_ep_info; 40 41 /* get SPSR for BL33 entry */ 42 static uint32_t get_spsr_for_bl33_entry(void) 43 { 44 unsigned long el_status; 45 unsigned long mode; 46 uint32_t spsr; 47 48 /* figure out what mode we enter the non-secure world */ 49 el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT; 50 el_status &= ID_AA64PFR0_ELX_MASK; 51 52 mode = (el_status) ? MODE_EL2 : MODE_EL1; 53 54 spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); 55 return spsr; 56 } 57 58 static void bl31_tz380_setup(void) 59 { 60 unsigned int val; 61 62 val = mmio_read_32(IMX_IOMUX_GPR_BASE + IOMUXC_GPR10); 63 if ((val & GPR_TZASC_EN) != GPR_TZASC_EN) 64 return; 65 66 tzc380_init(IMX_TZASC_BASE); 67 /* 68 * Need to substact offset 0x40000000 from CPU address when 69 * programming tzasc region for i.mx8mq. Enable 1G-5G S/NS RW 70 */ 71 tzc380_configure_region(0, 0x00000000, TZC_ATTR_REGION_SIZE(TZC_REGION_SIZE_4G) | 72 TZC_ATTR_REGION_EN_MASK | TZC_ATTR_SP_ALL); 73 } 74 75 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, 76 u_register_t arg2, u_register_t arg3) 77 { 78 int i; 79 /* enable CSU NS access permission */ 80 for (i = 0; i < 64; i++) { 81 mmio_write_32(IMX_CSU_BASE + i * 4, 0xffffffff); 82 } 83 84 #if DEBUG_CONSOLE 85 static console_uart_t console; 86 87 console_uart_register(IMX_BOOT_UART_BASE, IMX_BOOT_UART_CLK_IN_HZ, 88 IMX_CONSOLE_BAUDRATE, &console); 89 #endif 90 /* 91 * tell BL3-1 where the non-secure software image is located 92 * and the entry state information. 93 */ 94 bl33_image_ep_info.pc = PLAT_NS_IMAGE_OFFSET; 95 bl33_image_ep_info.spsr = get_spsr_for_bl33_entry(); 96 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); 97 98 bl31_tz380_setup(); 99 } 100 101 void bl31_plat_arch_setup(void) 102 { 103 mmap_add_region(BL31_RO_START, BL31_RO_START, (BL31_RO_END - BL31_RO_START), 104 MT_MEMORY | MT_RO | MT_SECURE); 105 mmap_add_region(BL31_RW_START, BL31_RW_START, (BL31_RW_END - BL31_RW_START), 106 MT_MEMORY | MT_RW | MT_SECURE); 107 108 mmap_add(imx_mmap); 109 110 #if USE_COHERENT_MEM 111 mmap_add_region(BL31_COHERENT_RAM_START, BL31_COHERENT_RAM_START, 112 BL31_COHERENT_RAM_END - BL31_COHERENT_RAM_START, 113 MT_DEVICE | MT_RW | MT_SECURE); 114 #endif 115 /* setup xlat table */ 116 init_xlat_tables(); 117 /* enable the MMU */ 118 enable_mmu_el3(0); 119 } 120 121 void bl31_platform_setup(void) 122 { 123 /* init the GICv3 cpu and distributor interface */ 124 plat_gic_driver_init(); 125 plat_gic_init(); 126 127 /* gpc init */ 128 imx_gpc_init(); 129 } 130 131 entry_point_info_t *bl31_plat_get_next_image_ep_info(unsigned int type) 132 { 133 if (type == NON_SECURE) 134 return &bl33_image_ep_info; 135 if (type == SECURE) 136 return &bl32_image_ep_info; 137 138 return NULL; 139 } 140 141 unsigned int plat_get_syscnt_freq2(void) 142 { 143 return COUNTER_FREQUENCY; 144 } 145 146 void bl31_plat_runtime_setup(void) 147 { 148 return; 149 } 150