rcar_gen3: plat: Add E3 rev. 1.1 support

Add support for R-Car E3 silicon rev. 1.1

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>

rcar_gen3: plat: Add missing platform auto-detection name

Add missing TARGET_NAME for the case where RCAR_LSI is set to AUTO,
which is platform auto-detection.

Signed-off-by: Marek Vasut <marek.vas

rcar_gen3: plat: Add missing platform auto-detection name

Add missing TARGET_NAME for the case where RCAR_LSI is set to AUTO,
which is platform auto-detection.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>

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rcar_gen3: plat: Clean up rcar_pwrc_code_copy_to_system_ram()

Call the function only from architecture setup and at the end of
suspend cycle instead of calling it all over the place.

Signed-off-by:

rcar_gen3: plat: Clean up rcar_pwrc_code_copy_to_system_ram()

Call the function only from architecture setup and at the end of
suspend cycle instead of calling it all over the place.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>

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rcar_gen3: plat: Fix BL2 size check

Rename BL2_LIMIT to BL2_IMAGE_LIMIT and BL2_SYSRAM_LIMIT to BL2_LIMIT to
correctly set BL2_LIMIT value. Set correct DEVICE_SRAM_BASE to match the
hardware. Use BL

rcar_gen3: plat: Fix BL2 size check

Rename BL2_LIMIT to BL2_IMAGE_LIMIT and BL2_SYSRAM_LIMIT to BL2_LIMIT to
correctly set BL2_LIMIT value. Set correct DEVICE_SRAM_BASE to match the
hardware. Use BL2_END in rcar_configure_mmu_el3() to mark the cacheable
BL2 area.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>

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rcar_gen3: plat: Staticize memory maps

Staticize the platform memory map tables as they are only used within
the platform_common.c file.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>

rcar_gen3: plat: Function cleanup

Replace foo_t with struct foo.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>

rcar_gen3: plat: Fix cache line size

The CPU has cache line size of 64 Bytes, fix the cache line size.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>

rcar_gen3: plat: Disable SVE

Apply 3872fc2d1fc5 ("Do not enable SVE on pre-v8.2 platforms") to
R-Car Gen3 too.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>

rcar_gen3: plat: Add missing dependency to rcar_srecord

Add missing dependency on the bl2.elf and bl31.elf into the rcar_srecord
target, which uses those ELF files to generate the SRECs.

Signed-off

rcar_gen3: plat: Add missing dependency to rcar_srecord

Add missing dependency on the bl2.elf and bl31.elf into the rcar_srecord
target, which uses those ELF files to generate the SRECs.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>

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rcar_gen3: plat: Rename H3 label

Rename the H3 label to avoid confusing clang, which generates an error
if the label is just H3. Rename it to RCARH3.

Signed-off-by: Marek Vasut <marek.vasut+renesas

rcar_gen3: plat: Rename H3 label

Rename the H3 label to avoid confusing clang, which generates an error
if the label is just H3. Rename it to RCARH3.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>

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Merge pull request #1740 from soby-mathew/sm/restrict_pie_to_fvp

plat/arm: Restrict PIE support to FVP

Merge pull request #1742 from sandrine-bailleux-arm/sb/fix-arm-mk

Fix a variable expansion in Arm platform makefiles

Merge pull request #1741 from deepan02/deepan02-arm-uart-definations

plat/arm/n1sdp: define the uart constants for N1SDP

Merge pull request #1739 from Yann-lms/includes

stm32mp1: do not include platform header files directly in drivers

Merge pull request #1732 from jollysxilinx/integration

plat: xilinx: Clock and PLL EEMI API Support

plat/arm/n1sdp: define the uart constants for N1SDP

This patch removes the dependency of the N1SDP on soc
css defines in order to let the N1SDP platform port
define the uart related constants.

Chan

plat/arm/n1sdp: define the uart constants for N1SDP

This patch removes the dependency of the N1SDP on soc
css defines in order to let the N1SDP platform port
define the uart related constants.

Change-Id: If13796f278586a01512ee99615502b30e478189e
Signed-off-by: Deepak Pandey <Deepak.Pandey@arm.com>

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Fix a variable expansion in Arm platform makefiles

The top level makefile defines the PLAT variable, not PLATFORM.
This mistake was causing an empty variable expansion and showing an
incomplete erro

Fix a variable expansion in Arm platform makefiles

The top level makefile defines the PLAT variable, not PLATFORM.
This mistake was causing an empty variable expansion and showing an
incomplete error message.

Change-Id: I5da1275c73c61a7c1823643a76300f255841719d
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>

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plat/arm: Restrict PIE support to FVP

The patch SHA 55cf015c enabled PIE support when RESET_TO_BL31=1 for
all ARM platforms. But it seems n1sdp platform doesn't work with PIE
support yet. Hence rest

plat/arm: Restrict PIE support to FVP

The patch SHA 55cf015c enabled PIE support when RESET_TO_BL31=1 for
all ARM platforms. But it seems n1sdp platform doesn't work with PIE
support yet. Hence restrict the ENABLE_PIE=1 to fvp platform.

Change-Id: If44e42528e4b0b57c69084503f346576fe0748bd
Signed-off-by: Soby Mathew <soby.mathew@arm.com>

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Merge pull request #1735 from antonio-nino-diaz-arm/an/load-image-v2

plat/arm: Remove comment that mentions LOAD_IMAGE_V2

stm32mp1: do not include platform header files directly in drivers

Instead, only platform_def.h is included.
The required files to be included are added in stm32mp1_def.h.

Signed-off-by: Yann Gauti

stm32mp1: do not include platform header files directly in drivers

Instead, only platform_def.h is included.
The required files to be included are added in stm32mp1_def.h.

Signed-off-by: Yann Gautier <yann.gautier@st.com>

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zynqmp: pm: Invalidate unused APLL_TO_LPD clock

This clock does not drive any clock in LPD so there is no need for
Linux to try to initialize it.

Signed-off-by: Mirela Simonovic <mirela.simonovic@a

zynqmp: pm: Invalidate unused APLL_TO_LPD clock

This clock does not drive any clock in LPD so there is no need for
Linux to try to initialize it.

Signed-off-by: Mirela Simonovic <mirela.simonovic@aggios.com>
Acked-by: Will Wong <WILLW@xilinx.com>
Signed-off-by: Jolly Shah <jollys@xilinx.com>

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zynqmp: pm: Invalidate several clocks that Linux doesn't need to control

Linux has no reason to use these system and debug clocks and therefore
shouldn't access them. These clocks are marked as inva

zynqmp: pm: Invalidate several clocks that Linux doesn't need to control

Linux has no reason to use these system and debug clocks and therefore
shouldn't access them. These clocks are marked as invalid in order to
prevent Linux from registering and querying them.

Note that despite clocks being marked as invalid a security issue
still remains in place as there is nothing that prevents the
non-secure world from gating these clocks and that way causing
damage to the system.

Signed-off-by: Mirela Simonovic <mirela.simonovic@aggios.com>
Acked-by: Will Wong <WILLW@xilinx.com>
Signed-off-by: Jolly Shah <jollys@xilinx.com>

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zynqmp: pm: Add ACPU_FULL and ACPU_HALF clocks in the invalid list

These clocks are marked as invalid in order to prevent Linux from
registering them.

Note that despite clocks being marked as inval

zynqmp: pm: Add ACPU_FULL and ACPU_HALF clocks in the invalid list

These clocks are marked as invalid in order to prevent Linux from
registering them.

Note that despite clocks being marked as invalid a security issue
still remains in place as there is nothing that prevents the
non-secure world from gating these clocks and that way halt
the whole APU subsystem.

Signed-off-by: Mirela Simonovic <mirela.simonovic@aggios.com>
Acked-by: Will Wong <WILLW@xilinx.com>
Signed-off-by: Jolly Shah <jollys@xilinx.com>

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zynqmp: pm: Fix model of ACPU clocks

In the existing model for ACPU clock the mux, divider, and gate were
represented as one clock and ACPU_HALF was modelled as child of
ACPU clock. This is not corr

zynqmp: pm: Fix model of ACPU clocks

In the existing model for ACPU clock the mux, divider, and gate were
represented as one clock and ACPU_HALF was modelled as child of
ACPU clock. This is not correct. ACPU clock model contains only
mux and the divider, and it has 2 children: ACPU_FULL and ACPU_HALF
clocks which have only gates. The models of ACPU and ACPU_HALF clocks
are fixed and ACPU_FULL clock is added.

Signed-off-by: Mirela Simonovic <mirela.simonovic@aggios.com>
Acked-by: Will Wong <WILLW@xilinx.com>
Signed-off-by: Jolly Shah <jollys@xilinx.com>

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zynqmp: pm: Reimplement clock get parent EEMI API

Clock get parent EEMI API is reimplemented to use system-level clock
and pll EEMI APIs rather than direct MMIO read/write accesses to clock
and pll

zynqmp: pm: Reimplement clock get parent EEMI API

Clock get parent EEMI API is reimplemented to use system-level clock
and pll EEMI APIs rather than direct MMIO read/write accesses to clock
and pll control registers.
Since linux still uses clock set parent API to get pre_src, post_src, div2
and bypasss, in the implementation of pm_clock_get_parent() we need to
workaround this by distinguishing two cases:
1) if the given clock ID corresponds to a PLL-related clock ID (*_PRE_SRC,
*_POST_SRC, *_INT_MUX or *_PLL clock IDs); or
2) given clock ID is truly an on-chip clock.
For case 1) we'll map the call onto PLL-specific EEMI API with the
respective parameter ID. For case 2) the call is passed to the PMU.

Signed-off-by: Mirela Simonovic <mirela.simonovic@aggios.com>
Acked-by: Will Wong <WILLW@xilinx.com>
Signed-off-by: Jolly Shah <jollys@xilinx.com>

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