1 /* 2 * Copyright (c) 2018, Renesas Electronics Corporation. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <string.h> 8 9 #include <libfdt.h> 10 11 #include <platform_def.h> 12 13 #include <arch_helpers.h> 14 #include <bl1/bl1.h> 15 #include <common/bl_common.h> 16 #include <common/debug.h> 17 #include <common/desc_image_load.h> 18 #include <drivers/console.h> 19 #include <lib/mmio.h> 20 #include <lib/xlat_tables/xlat_tables_defs.h> 21 #include <plat/common/platform.h> 22 23 #include "avs_driver.h" 24 #include "boot_init_dram.h" 25 #include "cpg_registers.h" 26 #include "board.h" 27 #include "emmc_def.h" 28 #include "emmc_hal.h" 29 #include "emmc_std.h" 30 31 #if PMIC_ROHM_BD9571 && RCAR_SYSTEM_RESET_KEEPON_DDR 32 #include "iic_dvfs.h" 33 #endif 34 35 #include "io_common.h" 36 #include "qos_init.h" 37 #include "rcar_def.h" 38 #include "rcar_private.h" 39 #include "rcar_version.h" 40 #include "rom_api.h" 41 42 IMPORT_SYM(unsigned long, __RO_START__, BL2_RO_BASE) 43 IMPORT_SYM(unsigned long, __RO_END__, BL2_RO_LIMIT) 44 45 #if USE_COHERENT_MEM 46 IMPORT_SYM(unsigned long, __COHERENT_RAM_START__, BL2_COHERENT_RAM_BASE) 47 IMPORT_SYM(unsigned long, __COHERENT_RAM_END__, BL2_COHERENT_RAM_LIMIT) 48 #endif 49 50 extern void plat_rcar_gic_driver_init(void); 51 extern void plat_rcar_gic_init(void); 52 extern void bl2_enter_bl31(const struct entry_point_info *bl_ep_info); 53 extern void bl2_system_cpg_init(void); 54 extern void bl2_secure_setting(void); 55 extern void bl2_cpg_init(void); 56 extern void rcar_io_emmc_setup(void); 57 extern void rcar_io_setup(void); 58 extern void rcar_swdt_release(void); 59 extern void rcar_swdt_init(void); 60 extern void rcar_rpc_init(void); 61 extern void rcar_pfc_init(void); 62 extern void rcar_dma_init(void); 63 64 /* R-Car Gen3 product check */ 65 #if (RCAR_LSI == RCAR_H3) || (RCAR_LSI == RCAR_H3N) 66 #define TARGET_PRODUCT RCAR_PRODUCT_H3 67 #define TARGET_NAME "R-Car H3" 68 #elif RCAR_LSI == RCAR_M3 69 #define TARGET_PRODUCT RCAR_PRODUCT_M3 70 #define TARGET_NAME "R-Car M3" 71 #elif RCAR_LSI == RCAR_M3N 72 #define TARGET_PRODUCT RCAR_PRODUCT_M3N 73 #define TARGET_NAME "R-Car M3N" 74 #elif RCAR_LSI == RCAR_E3 75 #define TARGET_PRODUCT RCAR_PRODUCT_E3 76 #define TARGET_NAME "R-Car E3" 77 #elif RCAR_LSI == RCAR_AUTO 78 #define TARGET_NAME "R-Car H3/M3/M3N" 79 #endif 80 81 #if (RCAR_LSI == RCAR_E3) 82 #define GPIO_INDT (GPIO_INDT6) 83 #define GPIO_BKUP_TRG_SHIFT ((uint32_t)1U<<13U) 84 #else 85 #define GPIO_INDT (GPIO_INDT1) 86 #define GPIO_BKUP_TRG_SHIFT ((uint32_t)1U<<8U) 87 #endif 88 89 CASSERT((PARAMS_BASE + sizeof(bl2_to_bl31_params_mem_t) + 0x100) 90 < (RCAR_SHARED_MEM_BASE + RCAR_SHARED_MEM_SIZE), 91 assert_bl31_params_do_not_fit_in_shared_memory); 92 93 static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE); 94 95 /* FDT with DRAM configuration */ 96 uint64_t fdt_blob[PAGE_SIZE_4KB / sizeof(uint64_t)]; 97 static void *fdt = (void *)fdt_blob; 98 99 static void unsigned_num_print(unsigned long long int unum, unsigned int radix, 100 char *string) 101 { 102 /* Just need enough space to store 64 bit decimal integer */ 103 char num_buf[20]; 104 int i = 0; 105 unsigned int rem; 106 107 do { 108 rem = unum % radix; 109 if (rem < 0xa) 110 num_buf[i] = '0' + rem; 111 else 112 num_buf[i] = 'a' + (rem - 0xa); 113 i++; 114 unum /= radix; 115 } while (unum > 0U); 116 117 while (--i >= 0) 118 *string++ = num_buf[i]; 119 } 120 121 #if (RCAR_LOSSY_ENABLE == 1) 122 typedef struct bl2_lossy_info { 123 uint32_t magic; 124 uint32_t a0; 125 uint32_t b0; 126 } bl2_lossy_info_t; 127 128 static void bl2_lossy_gen_fdt(uint32_t no, uint64_t start_addr, 129 uint64_t end_addr, uint32_t format, 130 uint32_t enable, int fcnlnode) 131 { 132 const uint64_t fcnlsize = cpu_to_fdt64(end_addr - start_addr); 133 char nodename[40] = { 0 }; 134 int ret, node; 135 136 /* Ignore undefined addresses */ 137 if (start_addr == 0 && end_addr == 0) 138 return; 139 140 snprintf(nodename, sizeof(nodename), "lossy-decompression@"); 141 unsigned_num_print(start_addr, 16, nodename + strlen(nodename)); 142 143 node = ret = fdt_add_subnode(fdt, fcnlnode, nodename); 144 if (ret < 0) { 145 NOTICE("BL2: Cannot create FCNL node (ret=%i)\n", ret); 146 panic(); 147 } 148 149 ret = fdt_setprop_string(fdt, node, "compatible", 150 "renesas,lossy-decompression"); 151 if (ret < 0) { 152 NOTICE("BL2: Cannot add FCNL compat string (ret=%i)\n", ret); 153 panic(); 154 } 155 156 ret = fdt_appendprop_string(fdt, node, "compatible", 157 "shared-dma-pool"); 158 if (ret < 0) { 159 NOTICE("BL2: Cannot append FCNL compat string (ret=%i)\n", ret); 160 panic(); 161 } 162 163 ret = fdt_setprop_u64(fdt, node, "reg", start_addr); 164 if (ret < 0) { 165 NOTICE("BL2: Cannot add FCNL reg prop (ret=%i)\n", ret); 166 panic(); 167 } 168 169 ret = fdt_appendprop(fdt, node, "reg", &fcnlsize, sizeof(fcnlsize)); 170 if (ret < 0) { 171 NOTICE("BL2: Cannot append FCNL reg size prop (ret=%i)\n", ret); 172 panic(); 173 } 174 175 ret = fdt_setprop(fdt, node, "no-map", NULL, 0); 176 if (ret < 0) { 177 NOTICE("BL2: Cannot add FCNL no-map prop (ret=%i)\n", ret); 178 panic(); 179 } 180 181 ret = fdt_setprop_u32(fdt, node, "renesas,formats", format); 182 if (ret < 0) { 183 NOTICE("BL2: Cannot add FCNL formats prop (ret=%i)\n", ret); 184 panic(); 185 } 186 } 187 188 static void bl2_lossy_setting(uint32_t no, uint64_t start_addr, 189 uint64_t end_addr, uint32_t format, 190 uint32_t enable, int fcnlnode) 191 { 192 bl2_lossy_info_t info; 193 uint32_t reg; 194 195 bl2_lossy_gen_fdt(no, start_addr, end_addr, format, enable, fcnlnode); 196 197 reg = format | (start_addr >> 20); 198 mmio_write_32(AXI_DCMPAREACRA0 + 0x8 * no, reg); 199 mmio_write_32(AXI_DCMPAREACRB0 + 0x8 * no, end_addr >> 20); 200 mmio_write_32(AXI_DCMPAREACRA0 + 0x8 * no, reg | enable); 201 202 info.magic = 0x12345678U; 203 info.a0 = mmio_read_32(AXI_DCMPAREACRA0 + 0x8 * no); 204 info.b0 = mmio_read_32(AXI_DCMPAREACRB0 + 0x8 * no); 205 206 mmio_write_32(LOSSY_PARAMS_BASE + sizeof(info) * no, info.magic); 207 mmio_write_32(LOSSY_PARAMS_BASE + sizeof(info) * no + 0x4, info.a0); 208 mmio_write_32(LOSSY_PARAMS_BASE + sizeof(info) * no + 0x8, info.b0); 209 210 NOTICE(" Entry %d: DCMPAREACRAx:0x%x DCMPAREACRBx:0x%x\n", no, 211 mmio_read_32(AXI_DCMPAREACRA0 + 0x8 * no), 212 mmio_read_32(AXI_DCMPAREACRB0 + 0x8 * no)); 213 } 214 #endif 215 216 void bl2_plat_flush_bl31_params(void) 217 { 218 uint32_t product_cut, product, cut; 219 uint32_t boot_dev, boot_cpu; 220 uint32_t lcs, reg, val; 221 222 reg = mmio_read_32(RCAR_MODEMR); 223 boot_dev = reg & MODEMR_BOOT_DEV_MASK; 224 225 if (boot_dev == MODEMR_BOOT_DEV_EMMC_25X1 || 226 boot_dev == MODEMR_BOOT_DEV_EMMC_50X8) 227 emmc_terminate(); 228 229 if ((reg & MODEMR_BOOT_CPU_MASK) != MODEMR_BOOT_CPU_CR7) 230 bl2_secure_setting(); 231 232 reg = mmio_read_32(RCAR_PRR); 233 product_cut = reg & (RCAR_PRODUCT_MASK | RCAR_CUT_MASK); 234 product = reg & RCAR_PRODUCT_MASK; 235 cut = reg & RCAR_CUT_MASK; 236 237 if (product == RCAR_PRODUCT_M3) 238 goto tlb; 239 240 if (product == RCAR_PRODUCT_H3 && RCAR_CUT_VER20 > cut) 241 goto tlb; 242 243 /* Disable MFIS write protection */ 244 mmio_write_32(MFISWPCNTR, MFISWPCNTR_PASSWORD | 1); 245 246 tlb: 247 reg = mmio_read_32(RCAR_MODEMR); 248 boot_cpu = reg & MODEMR_BOOT_CPU_MASK; 249 if (boot_cpu != MODEMR_BOOT_CPU_CA57 && 250 boot_cpu != MODEMR_BOOT_CPU_CA53) 251 goto mmu; 252 253 if (product_cut == RCAR_PRODUCT_H3_CUT20) { 254 mmio_write_32(IPMMUVI0_IMSCTLR, IMSCTLR_DISCACHE); 255 mmio_write_32(IPMMUVI1_IMSCTLR, IMSCTLR_DISCACHE); 256 mmio_write_32(IPMMUPV0_IMSCTLR, IMSCTLR_DISCACHE); 257 mmio_write_32(IPMMUPV1_IMSCTLR, IMSCTLR_DISCACHE); 258 mmio_write_32(IPMMUPV2_IMSCTLR, IMSCTLR_DISCACHE); 259 mmio_write_32(IPMMUPV3_IMSCTLR, IMSCTLR_DISCACHE); 260 } else if (product_cut == (RCAR_PRODUCT_M3N | RCAR_CUT_VER10) || 261 product_cut == (RCAR_PRODUCT_M3N | RCAR_CUT_VER11)) { 262 mmio_write_32(IPMMUVI0_IMSCTLR, IMSCTLR_DISCACHE); 263 mmio_write_32(IPMMUPV0_IMSCTLR, IMSCTLR_DISCACHE); 264 } else if (product_cut == (RCAR_PRODUCT_E3 | RCAR_CUT_VER10)) { 265 mmio_write_32(IPMMUVI0_IMSCTLR, IMSCTLR_DISCACHE); 266 mmio_write_32(IPMMUPV0_IMSCTLR, IMSCTLR_DISCACHE); 267 } 268 269 if (product_cut == (RCAR_PRODUCT_H3_CUT20) || 270 product_cut == (RCAR_PRODUCT_M3N | RCAR_CUT_VER10) || 271 product_cut == (RCAR_PRODUCT_M3N | RCAR_CUT_VER11) || 272 product_cut == (RCAR_PRODUCT_E3 | RCAR_CUT_VER10)) { 273 mmio_write_32(IPMMUHC_IMSCTLR, IMSCTLR_DISCACHE); 274 mmio_write_32(IPMMURT_IMSCTLR, IMSCTLR_DISCACHE); 275 mmio_write_32(IPMMUMP_IMSCTLR, IMSCTLR_DISCACHE); 276 277 mmio_write_32(IPMMUDS0_IMSCTLR, IMSCTLR_DISCACHE); 278 mmio_write_32(IPMMUDS1_IMSCTLR, IMSCTLR_DISCACHE); 279 } 280 281 mmu: 282 mmio_write_32(IPMMUMM_IMSCTLR, IPMMUMM_IMSCTLR_ENABLE); 283 mmio_write_32(IPMMUMM_IMAUXCTLR, IPMMUMM_IMAUXCTLR_NMERGE40_BIT); 284 285 val = rcar_rom_get_lcs(&lcs); 286 if (val) { 287 ERROR("BL2: Failed to get the LCS. (%d)\n", val); 288 panic(); 289 } 290 291 if (lcs == LCS_SE) 292 mmio_clrbits_32(P_ARMREG_SEC_CTRL, P_ARMREG_SEC_CTRL_PROT); 293 294 rcar_swdt_release(); 295 bl2_system_cpg_init(); 296 297 #if RCAR_BL2_DCACHE == 1 298 /* Disable data cache (clean and invalidate) */ 299 disable_mmu_el3(); 300 #endif 301 } 302 303 static uint32_t is_ddr_backup_mode(void) 304 { 305 #if RCAR_SYSTEM_SUSPEND 306 static uint32_t reason = RCAR_COLD_BOOT; 307 static uint32_t once; 308 309 #if PMIC_ROHM_BD9571 && RCAR_SYSTEM_RESET_KEEPON_DDR 310 uint8_t data; 311 #endif 312 if (once) 313 return reason; 314 315 once = 1; 316 if ((mmio_read_32(GPIO_INDT) & GPIO_BKUP_TRG_SHIFT) == 0) 317 return reason; 318 319 #if PMIC_ROHM_BD9571 && RCAR_SYSTEM_RESET_KEEPON_DDR 320 if (rcar_iic_dvfs_receive(PMIC, REG_KEEP10, &data)) { 321 ERROR("BL2: REG Keep10 READ ERROR.\n"); 322 panic(); 323 } 324 325 if (KEEP10_MAGIC != data) 326 reason = RCAR_WARM_BOOT; 327 #else 328 reason = RCAR_WARM_BOOT; 329 #endif 330 return reason; 331 #else 332 return RCAR_COLD_BOOT; 333 #endif 334 } 335 336 int bl2_plat_handle_pre_image_load(unsigned int image_id) 337 { 338 u_register_t *boot_kind = (void *) BOOT_KIND_BASE; 339 bl_mem_params_node_t *bl_mem_params; 340 341 if (image_id != BL31_IMAGE_ID) 342 return 0; 343 344 bl_mem_params = get_bl_mem_params_node(image_id); 345 346 if (is_ddr_backup_mode() == RCAR_COLD_BOOT) 347 goto cold_boot; 348 349 *boot_kind = RCAR_WARM_BOOT; 350 flush_dcache_range(BOOT_KIND_BASE, sizeof(*boot_kind)); 351 352 console_flush(); 353 bl2_plat_flush_bl31_params(); 354 355 /* will not return */ 356 bl2_enter_bl31(&bl_mem_params->ep_info); 357 358 cold_boot: 359 *boot_kind = RCAR_COLD_BOOT; 360 flush_dcache_range(BOOT_KIND_BASE, sizeof(*boot_kind)); 361 362 return 0; 363 } 364 365 int bl2_plat_handle_post_image_load(unsigned int image_id) 366 { 367 static bl2_to_bl31_params_mem_t *params; 368 bl_mem_params_node_t *bl_mem_params; 369 370 if (!params) { 371 params = (bl2_to_bl31_params_mem_t *) PARAMS_BASE; 372 memset((void *)PARAMS_BASE, 0, sizeof(*params)); 373 } 374 375 bl_mem_params = get_bl_mem_params_node(image_id); 376 377 switch (image_id) { 378 case BL31_IMAGE_ID: 379 break; 380 case BL32_IMAGE_ID: 381 memcpy(¶ms->bl32_ep_info, &bl_mem_params->ep_info, 382 sizeof(entry_point_info_t)); 383 break; 384 case BL33_IMAGE_ID: 385 memcpy(¶ms->bl33_ep_info, &bl_mem_params->ep_info, 386 sizeof(entry_point_info_t)); 387 break; 388 } 389 390 return 0; 391 } 392 393 struct meminfo *bl2_plat_sec_mem_layout(void) 394 { 395 return &bl2_tzram_layout; 396 } 397 398 static void bl2_populate_compatible_string(void *fdt) 399 { 400 uint32_t board_type; 401 uint32_t board_rev; 402 uint32_t reg; 403 int ret; 404 405 /* Populate compatible string */ 406 rcar_get_board_type(&board_type, &board_rev); 407 switch (board_type) { 408 case BOARD_SALVATOR_X: 409 ret = fdt_setprop_string(fdt, 0, "compatible", 410 "renesas,salvator-x"); 411 break; 412 case BOARD_SALVATOR_XS: 413 ret = fdt_setprop_string(fdt, 0, "compatible", 414 "renesas,salvator-xs"); 415 break; 416 case BOARD_STARTER_KIT: 417 ret = fdt_setprop_string(fdt, 0, "compatible", 418 "renesas,m3ulcb"); 419 break; 420 case BOARD_STARTER_KIT_PRE: 421 ret = fdt_setprop_string(fdt, 0, "compatible", 422 "renesas,h3ulcb"); 423 break; 424 case BOARD_EBISU: 425 case BOARD_EBISU_4D: 426 ret = fdt_setprop_string(fdt, 0, "compatible", 427 "renesas,ebisu"); 428 break; 429 default: 430 NOTICE("BL2: Cannot set compatible string, board unsupported\n"); 431 panic(); 432 } 433 434 if (ret < 0) { 435 NOTICE("BL2: Cannot set compatible string (ret=%i)\n", ret); 436 panic(); 437 } 438 439 reg = mmio_read_32(RCAR_PRR); 440 switch (reg & RCAR_PRODUCT_MASK) { 441 case RCAR_PRODUCT_H3: 442 ret = fdt_appendprop_string(fdt, 0, "compatible", 443 "renesas,r8a7795"); 444 break; 445 case RCAR_PRODUCT_M3: 446 ret = fdt_appendprop_string(fdt, 0, "compatible", 447 "renesas,r8a7796"); 448 break; 449 case RCAR_PRODUCT_M3N: 450 ret = fdt_appendprop_string(fdt, 0, "compatible", 451 "renesas,r8a77965"); 452 break; 453 case RCAR_PRODUCT_E3: 454 ret = fdt_appendprop_string(fdt, 0, "compatible", 455 "renesas,r8a77990"); 456 break; 457 default: 458 NOTICE("BL2: Cannot set compatible string, SoC unsupported\n"); 459 panic(); 460 } 461 462 if (ret < 0) { 463 NOTICE("BL2: Cannot set compatible string (ret=%i)\n", ret); 464 panic(); 465 } 466 } 467 468 static void bl2_advertise_dram_entries(uint64_t dram_config[8]) 469 { 470 char nodename[32] = { 0 }; 471 uint64_t start, size; 472 uint64_t fdtsize; 473 int ret, node, chan; 474 475 for (chan = 0; chan < 4; chan++) { 476 start = dram_config[2 * chan]; 477 size = dram_config[2 * chan + 1]; 478 if (!size) 479 continue; 480 481 NOTICE("BL2: CH%d: %llx - %llx, %lld GiB\n", 482 chan, start, start + size - 1, size >> 30); 483 } 484 485 /* 486 * We add the DT nodes in reverse order here. The fdt_add_subnode() 487 * adds the DT node before the first existing DT node, so we have 488 * to add them in reverse order to get nodes sorted by address in 489 * the resulting DT. 490 */ 491 for (chan = 3; chan >= 0; chan--) { 492 start = dram_config[2 * chan]; 493 size = dram_config[2 * chan + 1]; 494 if (!size) 495 continue; 496 497 /* 498 * Channel 0 is mapped in 32bit space and the first 499 * 128 MiB are reserved 500 */ 501 if (chan == 0) { 502 start = 0x48000000; 503 size -= 0x8000000; 504 } 505 506 fdtsize = cpu_to_fdt64(size); 507 508 snprintf(nodename, sizeof(nodename), "memory@"); 509 unsigned_num_print(start, 16, nodename + strlen(nodename)); 510 node = ret = fdt_add_subnode(fdt, 0, nodename); 511 if (ret < 0) 512 goto err; 513 514 ret = fdt_setprop_string(fdt, node, "device_type", "memory"); 515 if (ret < 0) 516 goto err; 517 518 ret = fdt_setprop_u64(fdt, node, "reg", start); 519 if (ret < 0) 520 goto err; 521 522 ret = fdt_appendprop(fdt, node, "reg", &fdtsize, 523 sizeof(fdtsize)); 524 if (ret < 0) 525 goto err; 526 } 527 528 return; 529 err: 530 NOTICE("BL2: Cannot add memory node to FDT (ret=%i)\n", ret); 531 panic(); 532 } 533 534 static void bl2_advertise_dram_size(uint32_t product) 535 { 536 uint64_t dram_config[8] = { 537 [0] = 0x400000000ULL, 538 [2] = 0x500000000ULL, 539 [4] = 0x600000000ULL, 540 [6] = 0x700000000ULL, 541 }; 542 543 switch (product) { 544 case RCAR_PRODUCT_H3: 545 #if (RCAR_DRAM_LPDDR4_MEMCONF == 0) 546 /* 4GB(1GBx4) */ 547 dram_config[1] = 0x40000000ULL; 548 dram_config[3] = 0x40000000ULL; 549 dram_config[5] = 0x40000000ULL; 550 dram_config[7] = 0x40000000ULL; 551 #elif (RCAR_DRAM_LPDDR4_MEMCONF == 1) && \ 552 (RCAR_DRAM_CHANNEL == 5) && \ 553 (RCAR_DRAM_SPLIT == 2) 554 /* 4GB(2GBx2 2ch split) */ 555 dram_config[1] = 0x80000000ULL; 556 dram_config[3] = 0x80000000ULL; 557 #elif (RCAR_DRAM_LPDDR4_MEMCONF == 1) && (RCAR_DRAM_CHANNEL == 15) 558 /* 8GB(2GBx4: default) */ 559 dram_config[1] = 0x80000000ULL; 560 dram_config[3] = 0x80000000ULL; 561 dram_config[5] = 0x80000000ULL; 562 dram_config[7] = 0x80000000ULL; 563 #endif /* RCAR_DRAM_LPDDR4_MEMCONF == 0 */ 564 break; 565 566 case RCAR_PRODUCT_M3: 567 /* 4GB(2GBx2 2ch split) */ 568 dram_config[1] = 0x80000000ULL; 569 dram_config[5] = 0x80000000ULL; 570 break; 571 572 case RCAR_PRODUCT_M3N: 573 /* 2GB(1GBx2) */ 574 dram_config[1] = 0x80000000ULL; 575 break; 576 577 case RCAR_PRODUCT_E3: 578 #if (RCAR_DRAM_DDR3L_MEMCONF == 0) 579 /* 1GB(512MBx2) */ 580 dram_config[1] = 0x40000000ULL; 581 #elif (RCAR_DRAM_DDR3L_MEMCONF == 1) 582 /* 2GB(512MBx4) */ 583 dram_config[1] = 0x80000000ULL; 584 #elif (RCAR_DRAM_DDR3L_MEMCONF == 2) 585 /* 4GB(1GBx4) */ 586 dram_config[1] = 0x100000000ULL; 587 #endif /* RCAR_DRAM_DDR3L_MEMCONF == 0 */ 588 break; 589 } 590 591 bl2_advertise_dram_entries(dram_config); 592 } 593 594 void bl2_el3_early_platform_setup(u_register_t arg1, u_register_t arg2, 595 u_register_t arg3, u_register_t arg4) 596 { 597 uint32_t reg, midr, lcs, boot_dev, boot_cpu, sscg, type, rev; 598 uint32_t product, product_cut, major, minor; 599 int32_t ret; 600 const char *str; 601 const char *unknown = "unknown"; 602 const char *cpu_ca57 = "CA57"; 603 const char *cpu_ca53 = "CA53"; 604 const char *product_m3n = "M3N"; 605 const char *product_h3 = "H3"; 606 const char *product_m3 = "M3"; 607 const char *product_e3 = "E3"; 608 const char *lcs_secure = "SE"; 609 const char *lcs_cm = "CM"; 610 const char *lcs_dm = "DM"; 611 const char *lcs_sd = "SD"; 612 const char *lcs_fa = "FA"; 613 const char *sscg_off = "PLL1 nonSSCG Clock select"; 614 const char *sscg_on = "PLL1 SSCG Clock select"; 615 const char *boot_hyper80 = "HyperFlash(80MHz)"; 616 const char *boot_qspi40 = "QSPI Flash(40MHz)"; 617 const char *boot_qspi80 = "QSPI Flash(80MHz)"; 618 const char *boot_emmc25x1 = "eMMC(25MHz x1)"; 619 const char *boot_emmc50x8 = "eMMC(50MHz x8)"; 620 #if RCAR_LSI == RCAR_E3 621 const char *boot_hyper160 = "HyperFlash(150MHz)"; 622 #else 623 const char *boot_hyper160 = "HyperFlash(160MHz)"; 624 #endif 625 #if (RCAR_LOSSY_ENABLE == 1) 626 int fcnlnode; 627 #endif 628 629 reg = mmio_read_32(RCAR_MODEMR); 630 boot_dev = reg & MODEMR_BOOT_DEV_MASK; 631 boot_cpu = reg & MODEMR_BOOT_CPU_MASK; 632 633 bl2_cpg_init(); 634 635 if (boot_cpu == MODEMR_BOOT_CPU_CA57 || 636 boot_cpu == MODEMR_BOOT_CPU_CA53) { 637 rcar_pfc_init(); 638 /* console configuration (platform specific) done in driver */ 639 console_init(0, 0, 0); 640 } 641 642 plat_rcar_gic_driver_init(); 643 plat_rcar_gic_init(); 644 rcar_swdt_init(); 645 646 /* FIQ interrupts are taken to EL3 */ 647 write_scr_el3(read_scr_el3() | SCR_FIQ_BIT); 648 649 write_daifclr(DAIF_FIQ_BIT); 650 651 reg = read_midr(); 652 midr = reg & (MIDR_PN_MASK << MIDR_PN_SHIFT); 653 switch (midr) { 654 case MIDR_CA57: 655 str = cpu_ca57; 656 break; 657 case MIDR_CA53: 658 str = cpu_ca53; 659 break; 660 default: 661 str = unknown; 662 break; 663 } 664 665 NOTICE("BL2: R-Car Gen3 Initial Program Loader(%s) Rev.%s\n", str, 666 version_of_renesas); 667 668 reg = mmio_read_32(RCAR_PRR); 669 product_cut = reg & (RCAR_PRODUCT_MASK | RCAR_CUT_MASK); 670 product = reg & RCAR_PRODUCT_MASK; 671 672 switch (product) { 673 case RCAR_PRODUCT_H3: 674 str = product_h3; 675 break; 676 case RCAR_PRODUCT_M3: 677 str = product_m3; 678 break; 679 case RCAR_PRODUCT_M3N: 680 str = product_m3n; 681 break; 682 case RCAR_PRODUCT_E3: 683 str = product_e3; 684 break; 685 default: 686 str = unknown; 687 break; 688 } 689 690 if (RCAR_PRODUCT_M3_CUT11 == product_cut) { 691 NOTICE("BL2: PRR is R-Car %s Ver.1.1 / Ver.1.2\n", str); 692 } else { 693 major = (reg & RCAR_MAJOR_MASK) >> RCAR_MAJOR_SHIFT; 694 major = major + RCAR_MAJOR_OFFSET; 695 minor = reg & RCAR_MINOR_MASK; 696 NOTICE("BL2: PRR is R-Car %s Ver.%d.%d\n", str, major, minor); 697 } 698 699 if (product == RCAR_PRODUCT_E3) { 700 reg = mmio_read_32(RCAR_MODEMR); 701 sscg = reg & RCAR_SSCG_MASK; 702 str = sscg == RCAR_SSCG_ENABLE ? sscg_on : sscg_off; 703 NOTICE("BL2: %s\n", str); 704 } 705 706 rcar_get_board_type(&type, &rev); 707 708 switch (type) { 709 case BOARD_SALVATOR_X: 710 case BOARD_KRIEK: 711 case BOARD_STARTER_KIT: 712 case BOARD_SALVATOR_XS: 713 case BOARD_EBISU: 714 case BOARD_STARTER_KIT_PRE: 715 case BOARD_EBISU_4D: 716 break; 717 default: 718 type = BOARD_UNKNOWN; 719 break; 720 } 721 722 if (type == BOARD_UNKNOWN || rev == BOARD_REV_UNKNOWN) 723 NOTICE("BL2: Board is %s Rev.---\n", GET_BOARD_NAME(type)); 724 else { 725 NOTICE("BL2: Board is %s Rev.%d.%d\n", 726 GET_BOARD_NAME(type), 727 GET_BOARD_MAJOR(rev), GET_BOARD_MINOR(rev)); 728 } 729 730 #if RCAR_LSI != RCAR_AUTO 731 if (product != TARGET_PRODUCT) { 732 ERROR("BL2: IPL was been built for the %s.\n", TARGET_NAME); 733 ERROR("BL2: Please write the correct IPL to flash memory.\n"); 734 panic(); 735 } 736 #endif 737 rcar_avs_init(); 738 rcar_avs_setting(); 739 740 switch (boot_dev) { 741 case MODEMR_BOOT_DEV_HYPERFLASH160: 742 str = boot_hyper160; 743 break; 744 case MODEMR_BOOT_DEV_HYPERFLASH80: 745 str = boot_hyper80; 746 break; 747 case MODEMR_BOOT_DEV_QSPI_FLASH40: 748 str = boot_qspi40; 749 break; 750 case MODEMR_BOOT_DEV_QSPI_FLASH80: 751 str = boot_qspi80; 752 break; 753 case MODEMR_BOOT_DEV_EMMC_25X1: 754 str = boot_emmc25x1; 755 break; 756 case MODEMR_BOOT_DEV_EMMC_50X8: 757 str = boot_emmc50x8; 758 break; 759 default: 760 str = unknown; 761 break; 762 } 763 NOTICE("BL2: Boot device is %s\n", str); 764 765 rcar_avs_setting(); 766 reg = rcar_rom_get_lcs(&lcs); 767 if (reg) { 768 str = unknown; 769 goto lcm_state; 770 } 771 772 switch (lcs) { 773 case LCS_CM: 774 str = lcs_cm; 775 break; 776 case LCS_DM: 777 str = lcs_dm; 778 break; 779 case LCS_SD: 780 str = lcs_sd; 781 break; 782 case LCS_SE: 783 str = lcs_secure; 784 break; 785 case LCS_FA: 786 str = lcs_fa; 787 break; 788 default: 789 str = unknown; 790 break; 791 } 792 793 lcm_state: 794 NOTICE("BL2: LCM state is %s\n", str); 795 796 rcar_avs_end(); 797 is_ddr_backup_mode(); 798 799 bl2_tzram_layout.total_base = BL31_BASE; 800 bl2_tzram_layout.total_size = BL31_LIMIT - BL31_BASE; 801 802 if (boot_cpu == MODEMR_BOOT_CPU_CA57 || 803 boot_cpu == MODEMR_BOOT_CPU_CA53) { 804 ret = rcar_dram_init(); 805 if (ret) { 806 NOTICE("BL2: Failed to DRAM initialize (%d).\n", ret); 807 panic(); 808 } 809 rcar_qos_init(); 810 } 811 812 /* Set up FDT */ 813 ret = fdt_create_empty_tree(fdt, sizeof(fdt_blob)); 814 if (ret) { 815 NOTICE("BL2: Cannot allocate FDT for U-Boot (ret=%i)\n", ret); 816 panic(); 817 } 818 819 /* Add platform compatible string */ 820 bl2_populate_compatible_string(fdt); 821 822 /* Print DRAM layout */ 823 bl2_advertise_dram_size(product); 824 825 if (boot_dev == MODEMR_BOOT_DEV_EMMC_25X1 || 826 boot_dev == MODEMR_BOOT_DEV_EMMC_50X8) { 827 if (rcar_emmc_init() != EMMC_SUCCESS) { 828 NOTICE("BL2: Failed to eMMC driver initialize.\n"); 829 panic(); 830 } 831 rcar_emmc_memcard_power(EMMC_POWER_ON); 832 if (rcar_emmc_mount() != EMMC_SUCCESS) { 833 NOTICE("BL2: Failed to eMMC mount operation.\n"); 834 panic(); 835 } 836 } else { 837 rcar_rpc_init(); 838 rcar_dma_init(); 839 } 840 841 reg = mmio_read_32(RST_WDTRSTCR); 842 reg &= ~WDTRSTCR_RWDT_RSTMSK; 843 reg |= WDTRSTCR_PASSWORD; 844 mmio_write_32(RST_WDTRSTCR, reg); 845 846 mmio_write_32(CPG_CPGWPR, CPGWPR_PASSWORD); 847 mmio_write_32(CPG_CPGWPCR, CPGWPCR_PASSWORD); 848 849 reg = mmio_read_32(RCAR_PRR); 850 if ((reg & RCAR_CPU_MASK_CA57) == RCAR_CPU_HAVE_CA57) 851 mmio_write_32(CPG_CA57DBGRCR, 852 DBGCPUPREN | mmio_read_32(CPG_CA57DBGRCR)); 853 854 if ((reg & RCAR_CPU_MASK_CA53) == RCAR_CPU_HAVE_CA53) 855 mmio_write_32(CPG_CA53DBGRCR, 856 DBGCPUPREN | mmio_read_32(CPG_CA53DBGRCR)); 857 858 if (product_cut == RCAR_PRODUCT_H3_CUT10) { 859 reg = mmio_read_32(CPG_PLL2CR); 860 reg &= ~((uint32_t) 1 << 5); 861 mmio_write_32(CPG_PLL2CR, reg); 862 863 reg = mmio_read_32(CPG_PLL4CR); 864 reg &= ~((uint32_t) 1 << 5); 865 mmio_write_32(CPG_PLL4CR, reg); 866 867 reg = mmio_read_32(CPG_PLL0CR); 868 reg &= ~((uint32_t) 1 << 12); 869 mmio_write_32(CPG_PLL0CR, reg); 870 } 871 #if (RCAR_LOSSY_ENABLE == 1) 872 NOTICE("BL2: Lossy Decomp areas\n"); 873 874 fcnlnode = fdt_add_subnode(fdt, 0, "reserved-memory"); 875 if (fcnlnode < 0) { 876 NOTICE("BL2: Cannot create reserved mem node (ret=%i)\n", 877 fcnlnode); 878 panic(); 879 } 880 881 bl2_lossy_setting(0, LOSSY_ST_ADDR0, LOSSY_END_ADDR0, 882 LOSSY_FMT0, LOSSY_ENA_DIS0, fcnlnode); 883 bl2_lossy_setting(1, LOSSY_ST_ADDR1, LOSSY_END_ADDR1, 884 LOSSY_FMT1, LOSSY_ENA_DIS1, fcnlnode); 885 bl2_lossy_setting(2, LOSSY_ST_ADDR2, LOSSY_END_ADDR2, 886 LOSSY_FMT2, LOSSY_ENA_DIS2, fcnlnode); 887 #endif 888 889 fdt_pack(fdt); 890 NOTICE("BL2: FDT at %p\n", fdt); 891 892 if (boot_dev == MODEMR_BOOT_DEV_EMMC_25X1 || 893 boot_dev == MODEMR_BOOT_DEV_EMMC_50X8) 894 rcar_io_emmc_setup(); 895 else 896 rcar_io_setup(); 897 } 898 899 void bl2_el3_plat_arch_setup(void) 900 { 901 #if RCAR_BL2_DCACHE == 1 902 NOTICE("BL2: D-Cache enable\n"); 903 rcar_configure_mmu_el3(BL2_BASE, 904 BL2_END - BL2_BASE, 905 BL2_RO_BASE, BL2_RO_LIMIT 906 #if USE_COHERENT_MEM 907 , BL2_COHERENT_RAM_BASE, BL2_COHERENT_RAM_LIMIT 908 #endif 909 ); 910 #endif 911 } 912 913 void bl2_platform_setup(void) 914 { 915 916 } 917