1 /* 2 * Copyright (c) 2018, Renesas Electronics Corporation. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <string.h> 8 9 #include <libfdt.h> 10 11 #include <platform_def.h> 12 13 #include <arch_helpers.h> 14 #include <bl1/bl1.h> 15 #include <common/bl_common.h> 16 #include <common/debug.h> 17 #include <common/desc_image_load.h> 18 #include <drivers/console.h> 19 #include <lib/mmio.h> 20 #include <lib/xlat_tables/xlat_tables_defs.h> 21 #include <plat/common/platform.h> 22 23 #include "avs_driver.h" 24 #include "boot_init_dram.h" 25 #include "cpg_registers.h" 26 #include "board.h" 27 #include "emmc_def.h" 28 #include "emmc_hal.h" 29 #include "emmc_std.h" 30 31 #if PMIC_ROHM_BD9571 && RCAR_SYSTEM_RESET_KEEPON_DDR 32 #include "iic_dvfs.h" 33 #endif 34 35 #include "io_common.h" 36 #include "qos_init.h" 37 #include "rcar_def.h" 38 #include "rcar_private.h" 39 #include "rcar_version.h" 40 #include "rom_api.h" 41 42 IMPORT_SYM(unsigned long, __RO_START__, BL2_RO_BASE) 43 IMPORT_SYM(unsigned long, __RO_END__, BL2_RO_LIMIT) 44 45 #if USE_COHERENT_MEM 46 IMPORT_SYM(unsigned long, __COHERENT_RAM_START__, BL2_COHERENT_RAM_BASE) 47 IMPORT_SYM(unsigned long, __COHERENT_RAM_END__, BL2_COHERENT_RAM_LIMIT) 48 #endif 49 50 extern void plat_rcar_gic_driver_init(void); 51 extern void plat_rcar_gic_init(void); 52 extern void bl2_enter_bl31(const struct entry_point_info *bl_ep_info); 53 extern void bl2_system_cpg_init(void); 54 extern void bl2_secure_setting(void); 55 extern void bl2_cpg_init(void); 56 extern void rcar_io_emmc_setup(void); 57 extern void rcar_io_setup(void); 58 extern void rcar_swdt_release(void); 59 extern void rcar_swdt_init(void); 60 extern void rcar_rpc_init(void); 61 extern void rcar_pfc_init(void); 62 extern void rcar_dma_init(void); 63 64 /* R-Car Gen3 product check */ 65 #if (RCAR_LSI == RCAR_H3) || (RCAR_LSI == RCAR_H3N) 66 #define TARGET_PRODUCT RCAR_PRODUCT_H3 67 #define TARGET_NAME "R-Car H3" 68 #elif RCAR_LSI == RCAR_M3 69 #define TARGET_PRODUCT RCAR_PRODUCT_M3 70 #define TARGET_NAME "R-Car M3" 71 #elif RCAR_LSI == RCAR_M3N 72 #define TARGET_PRODUCT RCAR_PRODUCT_M3N 73 #define TARGET_NAME "R-Car M3N" 74 #elif RCAR_LSI == RCAR_E3 75 #define TARGET_PRODUCT RCAR_PRODUCT_E3 76 #define TARGET_NAME "R-Car E3" 77 #elif RCAR_LSI == RCAR_AUTO 78 #define TARGET_NAME "R-Car H3/M3/M3N" 79 #endif 80 81 #if (RCAR_LSI == RCAR_E3) 82 #define GPIO_INDT (GPIO_INDT6) 83 #define GPIO_BKUP_TRG_SHIFT ((uint32_t)1U<<13U) 84 #else 85 #define GPIO_INDT (GPIO_INDT1) 86 #define GPIO_BKUP_TRG_SHIFT ((uint32_t)1U<<8U) 87 #endif 88 89 CASSERT((PARAMS_BASE + sizeof(bl2_to_bl31_params_mem_t) + 0x100) 90 < (RCAR_SHARED_MEM_BASE + RCAR_SHARED_MEM_SIZE), 91 assert_bl31_params_do_not_fit_in_shared_memory); 92 93 static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE); 94 95 /* FDT with DRAM configuration */ 96 uint64_t fdt_blob[PAGE_SIZE_4KB / sizeof(uint64_t)]; 97 static void *fdt = (void *)fdt_blob; 98 99 static void unsigned_num_print(unsigned long long int unum, unsigned int radix, 100 char *string) 101 { 102 /* Just need enough space to store 64 bit decimal integer */ 103 char num_buf[20]; 104 int i = 0; 105 unsigned int rem; 106 107 do { 108 rem = unum % radix; 109 if (rem < 0xa) 110 num_buf[i] = '0' + rem; 111 else 112 num_buf[i] = 'a' + (rem - 0xa); 113 i++; 114 unum /= radix; 115 } while (unum > 0U); 116 117 while (--i >= 0) 118 *string++ = num_buf[i]; 119 } 120 121 #if (RCAR_LOSSY_ENABLE == 1) 122 typedef struct bl2_lossy_info { 123 uint32_t magic; 124 uint32_t a0; 125 uint32_t b0; 126 } bl2_lossy_info_t; 127 128 static void bl2_lossy_gen_fdt(uint32_t no, uint64_t start_addr, 129 uint64_t end_addr, uint32_t format, 130 uint32_t enable, int fcnlnode) 131 { 132 const uint64_t fcnlsize = cpu_to_fdt64(end_addr - start_addr); 133 char nodename[40] = { 0 }; 134 int ret, node; 135 136 /* Ignore undefined addresses */ 137 if (start_addr == 0 && end_addr == 0) 138 return; 139 140 snprintf(nodename, sizeof(nodename), "lossy-decompression@"); 141 unsigned_num_print(start_addr, 16, nodename + strlen(nodename)); 142 143 node = ret = fdt_add_subnode(fdt, fcnlnode, nodename); 144 if (ret < 0) { 145 NOTICE("BL2: Cannot create FCNL node (ret=%i)\n", ret); 146 panic(); 147 } 148 149 ret = fdt_setprop_string(fdt, node, "compatible", 150 "renesas,lossy-decompression"); 151 if (ret < 0) { 152 NOTICE("BL2: Cannot add FCNL compat string (ret=%i)\n", ret); 153 panic(); 154 } 155 156 ret = fdt_appendprop_string(fdt, node, "compatible", 157 "shared-dma-pool"); 158 if (ret < 0) { 159 NOTICE("BL2: Cannot append FCNL compat string (ret=%i)\n", ret); 160 panic(); 161 } 162 163 ret = fdt_setprop_u64(fdt, node, "reg", start_addr); 164 if (ret < 0) { 165 NOTICE("BL2: Cannot add FCNL reg prop (ret=%i)\n", ret); 166 panic(); 167 } 168 169 ret = fdt_appendprop(fdt, node, "reg", &fcnlsize, sizeof(fcnlsize)); 170 if (ret < 0) { 171 NOTICE("BL2: Cannot append FCNL reg size prop (ret=%i)\n", ret); 172 panic(); 173 } 174 175 ret = fdt_setprop(fdt, node, "no-map", NULL, 0); 176 if (ret < 0) { 177 NOTICE("BL2: Cannot add FCNL no-map prop (ret=%i)\n", ret); 178 panic(); 179 } 180 181 ret = fdt_setprop_u32(fdt, node, "renesas,formats", format); 182 if (ret < 0) { 183 NOTICE("BL2: Cannot add FCNL formats prop (ret=%i)\n", ret); 184 panic(); 185 } 186 } 187 188 static void bl2_lossy_setting(uint32_t no, uint64_t start_addr, 189 uint64_t end_addr, uint32_t format, 190 uint32_t enable, int fcnlnode) 191 { 192 bl2_lossy_info_t info; 193 uint32_t reg; 194 195 bl2_lossy_gen_fdt(no, start_addr, end_addr, format, enable, fcnlnode); 196 197 reg = format | (start_addr >> 20); 198 mmio_write_32(AXI_DCMPAREACRA0 + 0x8 * no, reg); 199 mmio_write_32(AXI_DCMPAREACRB0 + 0x8 * no, end_addr >> 20); 200 mmio_write_32(AXI_DCMPAREACRA0 + 0x8 * no, reg | enable); 201 202 info.magic = 0x12345678U; 203 info.a0 = mmio_read_32(AXI_DCMPAREACRA0 + 0x8 * no); 204 info.b0 = mmio_read_32(AXI_DCMPAREACRB0 + 0x8 * no); 205 206 mmio_write_32(LOSSY_PARAMS_BASE + sizeof(info) * no, info.magic); 207 mmio_write_32(LOSSY_PARAMS_BASE + sizeof(info) * no + 0x4, info.a0); 208 mmio_write_32(LOSSY_PARAMS_BASE + sizeof(info) * no + 0x8, info.b0); 209 210 NOTICE(" Entry %d: DCMPAREACRAx:0x%x DCMPAREACRBx:0x%x\n", no, 211 mmio_read_32(AXI_DCMPAREACRA0 + 0x8 * no), 212 mmio_read_32(AXI_DCMPAREACRB0 + 0x8 * no)); 213 } 214 #endif 215 216 void bl2_plat_flush_bl31_params(void) 217 { 218 uint32_t product_cut, product, cut; 219 uint32_t boot_dev, boot_cpu; 220 uint32_t lcs, reg, val; 221 222 reg = mmio_read_32(RCAR_MODEMR); 223 boot_dev = reg & MODEMR_BOOT_DEV_MASK; 224 225 if (boot_dev == MODEMR_BOOT_DEV_EMMC_25X1 || 226 boot_dev == MODEMR_BOOT_DEV_EMMC_50X8) 227 emmc_terminate(); 228 229 if ((reg & MODEMR_BOOT_CPU_MASK) != MODEMR_BOOT_CPU_CR7) 230 bl2_secure_setting(); 231 232 reg = mmio_read_32(RCAR_PRR); 233 product_cut = reg & (RCAR_PRODUCT_MASK | RCAR_CUT_MASK); 234 product = reg & RCAR_PRODUCT_MASK; 235 cut = reg & RCAR_CUT_MASK; 236 237 if (product == RCAR_PRODUCT_M3) 238 goto tlb; 239 240 if (product == RCAR_PRODUCT_H3 && RCAR_CUT_VER20 > cut) 241 goto tlb; 242 243 /* Disable MFIS write protection */ 244 mmio_write_32(MFISWPCNTR, MFISWPCNTR_PASSWORD | 1); 245 246 tlb: 247 reg = mmio_read_32(RCAR_MODEMR); 248 boot_cpu = reg & MODEMR_BOOT_CPU_MASK; 249 if (boot_cpu != MODEMR_BOOT_CPU_CA57 && 250 boot_cpu != MODEMR_BOOT_CPU_CA53) 251 goto mmu; 252 253 if (product_cut == RCAR_PRODUCT_H3_CUT20) { 254 mmio_write_32(IPMMUVI0_IMSCTLR, IMSCTLR_DISCACHE); 255 mmio_write_32(IPMMUVI1_IMSCTLR, IMSCTLR_DISCACHE); 256 mmio_write_32(IPMMUPV0_IMSCTLR, IMSCTLR_DISCACHE); 257 mmio_write_32(IPMMUPV1_IMSCTLR, IMSCTLR_DISCACHE); 258 mmio_write_32(IPMMUPV2_IMSCTLR, IMSCTLR_DISCACHE); 259 mmio_write_32(IPMMUPV3_IMSCTLR, IMSCTLR_DISCACHE); 260 } else if (product_cut == (RCAR_PRODUCT_M3N | RCAR_CUT_VER10) || 261 product_cut == (RCAR_PRODUCT_M3N | RCAR_CUT_VER11)) { 262 mmio_write_32(IPMMUVI0_IMSCTLR, IMSCTLR_DISCACHE); 263 mmio_write_32(IPMMUPV0_IMSCTLR, IMSCTLR_DISCACHE); 264 } else if ((product_cut == (RCAR_PRODUCT_E3 | RCAR_CUT_VER10)) || 265 (product_cut == (RCAR_PRODUCT_E3 | RCAR_CUT_VER11))) { 266 mmio_write_32(IPMMUVI0_IMSCTLR, IMSCTLR_DISCACHE); 267 mmio_write_32(IPMMUPV0_IMSCTLR, IMSCTLR_DISCACHE); 268 } 269 270 if (product_cut == (RCAR_PRODUCT_H3_CUT20) || 271 product_cut == (RCAR_PRODUCT_M3N | RCAR_CUT_VER10) || 272 product_cut == (RCAR_PRODUCT_M3N | RCAR_CUT_VER11) || 273 product_cut == (RCAR_PRODUCT_E3 | RCAR_CUT_VER10)) { 274 mmio_write_32(IPMMUHC_IMSCTLR, IMSCTLR_DISCACHE); 275 mmio_write_32(IPMMURT_IMSCTLR, IMSCTLR_DISCACHE); 276 mmio_write_32(IPMMUMP_IMSCTLR, IMSCTLR_DISCACHE); 277 278 mmio_write_32(IPMMUDS0_IMSCTLR, IMSCTLR_DISCACHE); 279 mmio_write_32(IPMMUDS1_IMSCTLR, IMSCTLR_DISCACHE); 280 } 281 282 mmu: 283 mmio_write_32(IPMMUMM_IMSCTLR, IPMMUMM_IMSCTLR_ENABLE); 284 mmio_write_32(IPMMUMM_IMAUXCTLR, IPMMUMM_IMAUXCTLR_NMERGE40_BIT); 285 286 val = rcar_rom_get_lcs(&lcs); 287 if (val) { 288 ERROR("BL2: Failed to get the LCS. (%d)\n", val); 289 panic(); 290 } 291 292 if (lcs == LCS_SE) 293 mmio_clrbits_32(P_ARMREG_SEC_CTRL, P_ARMREG_SEC_CTRL_PROT); 294 295 rcar_swdt_release(); 296 bl2_system_cpg_init(); 297 298 #if RCAR_BL2_DCACHE == 1 299 /* Disable data cache (clean and invalidate) */ 300 disable_mmu_el3(); 301 #endif 302 } 303 304 static uint32_t is_ddr_backup_mode(void) 305 { 306 #if RCAR_SYSTEM_SUSPEND 307 static uint32_t reason = RCAR_COLD_BOOT; 308 static uint32_t once; 309 310 #if PMIC_ROHM_BD9571 && RCAR_SYSTEM_RESET_KEEPON_DDR 311 uint8_t data; 312 #endif 313 if (once) 314 return reason; 315 316 once = 1; 317 if ((mmio_read_32(GPIO_INDT) & GPIO_BKUP_TRG_SHIFT) == 0) 318 return reason; 319 320 #if PMIC_ROHM_BD9571 && RCAR_SYSTEM_RESET_KEEPON_DDR 321 if (rcar_iic_dvfs_receive(PMIC, REG_KEEP10, &data)) { 322 ERROR("BL2: REG Keep10 READ ERROR.\n"); 323 panic(); 324 } 325 326 if (KEEP10_MAGIC != data) 327 reason = RCAR_WARM_BOOT; 328 #else 329 reason = RCAR_WARM_BOOT; 330 #endif 331 return reason; 332 #else 333 return RCAR_COLD_BOOT; 334 #endif 335 } 336 337 int bl2_plat_handle_pre_image_load(unsigned int image_id) 338 { 339 u_register_t *boot_kind = (void *) BOOT_KIND_BASE; 340 bl_mem_params_node_t *bl_mem_params; 341 342 if (image_id != BL31_IMAGE_ID) 343 return 0; 344 345 bl_mem_params = get_bl_mem_params_node(image_id); 346 347 if (is_ddr_backup_mode() == RCAR_COLD_BOOT) 348 goto cold_boot; 349 350 *boot_kind = RCAR_WARM_BOOT; 351 flush_dcache_range(BOOT_KIND_BASE, sizeof(*boot_kind)); 352 353 console_flush(); 354 bl2_plat_flush_bl31_params(); 355 356 /* will not return */ 357 bl2_enter_bl31(&bl_mem_params->ep_info); 358 359 cold_boot: 360 *boot_kind = RCAR_COLD_BOOT; 361 flush_dcache_range(BOOT_KIND_BASE, sizeof(*boot_kind)); 362 363 return 0; 364 } 365 366 int bl2_plat_handle_post_image_load(unsigned int image_id) 367 { 368 static bl2_to_bl31_params_mem_t *params; 369 bl_mem_params_node_t *bl_mem_params; 370 371 if (!params) { 372 params = (bl2_to_bl31_params_mem_t *) PARAMS_BASE; 373 memset((void *)PARAMS_BASE, 0, sizeof(*params)); 374 } 375 376 bl_mem_params = get_bl_mem_params_node(image_id); 377 378 switch (image_id) { 379 case BL31_IMAGE_ID: 380 break; 381 case BL32_IMAGE_ID: 382 memcpy(¶ms->bl32_ep_info, &bl_mem_params->ep_info, 383 sizeof(entry_point_info_t)); 384 break; 385 case BL33_IMAGE_ID: 386 memcpy(¶ms->bl33_ep_info, &bl_mem_params->ep_info, 387 sizeof(entry_point_info_t)); 388 break; 389 } 390 391 return 0; 392 } 393 394 struct meminfo *bl2_plat_sec_mem_layout(void) 395 { 396 return &bl2_tzram_layout; 397 } 398 399 static void bl2_populate_compatible_string(void *fdt) 400 { 401 uint32_t board_type; 402 uint32_t board_rev; 403 uint32_t reg; 404 int ret; 405 406 /* Populate compatible string */ 407 rcar_get_board_type(&board_type, &board_rev); 408 switch (board_type) { 409 case BOARD_SALVATOR_X: 410 ret = fdt_setprop_string(fdt, 0, "compatible", 411 "renesas,salvator-x"); 412 break; 413 case BOARD_SALVATOR_XS: 414 ret = fdt_setprop_string(fdt, 0, "compatible", 415 "renesas,salvator-xs"); 416 break; 417 case BOARD_STARTER_KIT: 418 ret = fdt_setprop_string(fdt, 0, "compatible", 419 "renesas,m3ulcb"); 420 break; 421 case BOARD_STARTER_KIT_PRE: 422 ret = fdt_setprop_string(fdt, 0, "compatible", 423 "renesas,h3ulcb"); 424 break; 425 case BOARD_EBISU: 426 case BOARD_EBISU_4D: 427 ret = fdt_setprop_string(fdt, 0, "compatible", 428 "renesas,ebisu"); 429 break; 430 default: 431 NOTICE("BL2: Cannot set compatible string, board unsupported\n"); 432 panic(); 433 } 434 435 if (ret < 0) { 436 NOTICE("BL2: Cannot set compatible string (ret=%i)\n", ret); 437 panic(); 438 } 439 440 reg = mmio_read_32(RCAR_PRR); 441 switch (reg & RCAR_PRODUCT_MASK) { 442 case RCAR_PRODUCT_H3: 443 ret = fdt_appendprop_string(fdt, 0, "compatible", 444 "renesas,r8a7795"); 445 break; 446 case RCAR_PRODUCT_M3: 447 ret = fdt_appendprop_string(fdt, 0, "compatible", 448 "renesas,r8a7796"); 449 break; 450 case RCAR_PRODUCT_M3N: 451 ret = fdt_appendprop_string(fdt, 0, "compatible", 452 "renesas,r8a77965"); 453 break; 454 case RCAR_PRODUCT_E3: 455 ret = fdt_appendprop_string(fdt, 0, "compatible", 456 "renesas,r8a77990"); 457 break; 458 default: 459 NOTICE("BL2: Cannot set compatible string, SoC unsupported\n"); 460 panic(); 461 } 462 463 if (ret < 0) { 464 NOTICE("BL2: Cannot set compatible string (ret=%i)\n", ret); 465 panic(); 466 } 467 } 468 469 static void bl2_advertise_dram_entries(uint64_t dram_config[8]) 470 { 471 char nodename[32] = { 0 }; 472 uint64_t start, size; 473 uint64_t fdtsize; 474 int ret, node, chan; 475 476 for (chan = 0; chan < 4; chan++) { 477 start = dram_config[2 * chan]; 478 size = dram_config[2 * chan + 1]; 479 if (!size) 480 continue; 481 482 NOTICE("BL2: CH%d: %llx - %llx, %lld GiB\n", 483 chan, start, start + size - 1, size >> 30); 484 } 485 486 /* 487 * We add the DT nodes in reverse order here. The fdt_add_subnode() 488 * adds the DT node before the first existing DT node, so we have 489 * to add them in reverse order to get nodes sorted by address in 490 * the resulting DT. 491 */ 492 for (chan = 3; chan >= 0; chan--) { 493 start = dram_config[2 * chan]; 494 size = dram_config[2 * chan + 1]; 495 if (!size) 496 continue; 497 498 /* 499 * Channel 0 is mapped in 32bit space and the first 500 * 128 MiB are reserved 501 */ 502 if (chan == 0) { 503 start = 0x48000000; 504 size -= 0x8000000; 505 } 506 507 fdtsize = cpu_to_fdt64(size); 508 509 snprintf(nodename, sizeof(nodename), "memory@"); 510 unsigned_num_print(start, 16, nodename + strlen(nodename)); 511 node = ret = fdt_add_subnode(fdt, 0, nodename); 512 if (ret < 0) 513 goto err; 514 515 ret = fdt_setprop_string(fdt, node, "device_type", "memory"); 516 if (ret < 0) 517 goto err; 518 519 ret = fdt_setprop_u64(fdt, node, "reg", start); 520 if (ret < 0) 521 goto err; 522 523 ret = fdt_appendprop(fdt, node, "reg", &fdtsize, 524 sizeof(fdtsize)); 525 if (ret < 0) 526 goto err; 527 } 528 529 return; 530 err: 531 NOTICE("BL2: Cannot add memory node to FDT (ret=%i)\n", ret); 532 panic(); 533 } 534 535 static void bl2_advertise_dram_size(uint32_t product) 536 { 537 uint64_t dram_config[8] = { 538 [0] = 0x400000000ULL, 539 [2] = 0x500000000ULL, 540 [4] = 0x600000000ULL, 541 [6] = 0x700000000ULL, 542 }; 543 544 switch (product) { 545 case RCAR_PRODUCT_H3: 546 #if (RCAR_DRAM_LPDDR4_MEMCONF == 0) 547 /* 4GB(1GBx4) */ 548 dram_config[1] = 0x40000000ULL; 549 dram_config[3] = 0x40000000ULL; 550 dram_config[5] = 0x40000000ULL; 551 dram_config[7] = 0x40000000ULL; 552 #elif (RCAR_DRAM_LPDDR4_MEMCONF == 1) && \ 553 (RCAR_DRAM_CHANNEL == 5) && \ 554 (RCAR_DRAM_SPLIT == 2) 555 /* 4GB(2GBx2 2ch split) */ 556 dram_config[1] = 0x80000000ULL; 557 dram_config[3] = 0x80000000ULL; 558 #elif (RCAR_DRAM_LPDDR4_MEMCONF == 1) && (RCAR_DRAM_CHANNEL == 15) 559 /* 8GB(2GBx4: default) */ 560 dram_config[1] = 0x80000000ULL; 561 dram_config[3] = 0x80000000ULL; 562 dram_config[5] = 0x80000000ULL; 563 dram_config[7] = 0x80000000ULL; 564 #endif /* RCAR_DRAM_LPDDR4_MEMCONF == 0 */ 565 break; 566 567 case RCAR_PRODUCT_M3: 568 /* 4GB(2GBx2 2ch split) */ 569 dram_config[1] = 0x80000000ULL; 570 dram_config[5] = 0x80000000ULL; 571 break; 572 573 case RCAR_PRODUCT_M3N: 574 /* 2GB(1GBx2) */ 575 dram_config[1] = 0x80000000ULL; 576 break; 577 578 case RCAR_PRODUCT_E3: 579 #if (RCAR_DRAM_DDR3L_MEMCONF == 0) 580 /* 1GB(512MBx2) */ 581 dram_config[1] = 0x40000000ULL; 582 #elif (RCAR_DRAM_DDR3L_MEMCONF == 1) 583 /* 2GB(512MBx4) */ 584 dram_config[1] = 0x80000000ULL; 585 #elif (RCAR_DRAM_DDR3L_MEMCONF == 2) 586 /* 4GB(1GBx4) */ 587 dram_config[1] = 0x100000000ULL; 588 #endif /* RCAR_DRAM_DDR3L_MEMCONF == 0 */ 589 break; 590 } 591 592 bl2_advertise_dram_entries(dram_config); 593 } 594 595 void bl2_el3_early_platform_setup(u_register_t arg1, u_register_t arg2, 596 u_register_t arg3, u_register_t arg4) 597 { 598 uint32_t reg, midr, lcs, boot_dev, boot_cpu, sscg, type, rev; 599 uint32_t product, product_cut, major, minor; 600 int32_t ret; 601 const char *str; 602 const char *unknown = "unknown"; 603 const char *cpu_ca57 = "CA57"; 604 const char *cpu_ca53 = "CA53"; 605 const char *product_m3n = "M3N"; 606 const char *product_h3 = "H3"; 607 const char *product_m3 = "M3"; 608 const char *product_e3 = "E3"; 609 const char *lcs_secure = "SE"; 610 const char *lcs_cm = "CM"; 611 const char *lcs_dm = "DM"; 612 const char *lcs_sd = "SD"; 613 const char *lcs_fa = "FA"; 614 const char *sscg_off = "PLL1 nonSSCG Clock select"; 615 const char *sscg_on = "PLL1 SSCG Clock select"; 616 const char *boot_hyper80 = "HyperFlash(80MHz)"; 617 const char *boot_qspi40 = "QSPI Flash(40MHz)"; 618 const char *boot_qspi80 = "QSPI Flash(80MHz)"; 619 const char *boot_emmc25x1 = "eMMC(25MHz x1)"; 620 const char *boot_emmc50x8 = "eMMC(50MHz x8)"; 621 #if RCAR_LSI == RCAR_E3 622 const char *boot_hyper160 = "HyperFlash(150MHz)"; 623 #else 624 const char *boot_hyper160 = "HyperFlash(160MHz)"; 625 #endif 626 #if (RCAR_LOSSY_ENABLE == 1) 627 int fcnlnode; 628 #endif 629 630 reg = mmio_read_32(RCAR_MODEMR); 631 boot_dev = reg & MODEMR_BOOT_DEV_MASK; 632 boot_cpu = reg & MODEMR_BOOT_CPU_MASK; 633 634 bl2_cpg_init(); 635 636 if (boot_cpu == MODEMR_BOOT_CPU_CA57 || 637 boot_cpu == MODEMR_BOOT_CPU_CA53) { 638 rcar_pfc_init(); 639 /* console configuration (platform specific) done in driver */ 640 console_init(0, 0, 0); 641 } 642 643 plat_rcar_gic_driver_init(); 644 plat_rcar_gic_init(); 645 rcar_swdt_init(); 646 647 /* FIQ interrupts are taken to EL3 */ 648 write_scr_el3(read_scr_el3() | SCR_FIQ_BIT); 649 650 write_daifclr(DAIF_FIQ_BIT); 651 652 reg = read_midr(); 653 midr = reg & (MIDR_PN_MASK << MIDR_PN_SHIFT); 654 switch (midr) { 655 case MIDR_CA57: 656 str = cpu_ca57; 657 break; 658 case MIDR_CA53: 659 str = cpu_ca53; 660 break; 661 default: 662 str = unknown; 663 break; 664 } 665 666 NOTICE("BL2: R-Car Gen3 Initial Program Loader(%s) Rev.%s\n", str, 667 version_of_renesas); 668 669 reg = mmio_read_32(RCAR_PRR); 670 product_cut = reg & (RCAR_PRODUCT_MASK | RCAR_CUT_MASK); 671 product = reg & RCAR_PRODUCT_MASK; 672 673 switch (product) { 674 case RCAR_PRODUCT_H3: 675 str = product_h3; 676 break; 677 case RCAR_PRODUCT_M3: 678 str = product_m3; 679 break; 680 case RCAR_PRODUCT_M3N: 681 str = product_m3n; 682 break; 683 case RCAR_PRODUCT_E3: 684 str = product_e3; 685 break; 686 default: 687 str = unknown; 688 break; 689 } 690 691 if (RCAR_PRODUCT_M3_CUT11 == product_cut) { 692 NOTICE("BL2: PRR is R-Car %s Ver.1.1 / Ver.1.2\n", str); 693 } else { 694 major = (reg & RCAR_MAJOR_MASK) >> RCAR_MAJOR_SHIFT; 695 major = major + RCAR_MAJOR_OFFSET; 696 minor = reg & RCAR_MINOR_MASK; 697 NOTICE("BL2: PRR is R-Car %s Ver.%d.%d\n", str, major, minor); 698 } 699 700 if (product == RCAR_PRODUCT_E3) { 701 reg = mmio_read_32(RCAR_MODEMR); 702 sscg = reg & RCAR_SSCG_MASK; 703 str = sscg == RCAR_SSCG_ENABLE ? sscg_on : sscg_off; 704 NOTICE("BL2: %s\n", str); 705 } 706 707 rcar_get_board_type(&type, &rev); 708 709 switch (type) { 710 case BOARD_SALVATOR_X: 711 case BOARD_KRIEK: 712 case BOARD_STARTER_KIT: 713 case BOARD_SALVATOR_XS: 714 case BOARD_EBISU: 715 case BOARD_STARTER_KIT_PRE: 716 case BOARD_EBISU_4D: 717 break; 718 default: 719 type = BOARD_UNKNOWN; 720 break; 721 } 722 723 if (type == BOARD_UNKNOWN || rev == BOARD_REV_UNKNOWN) 724 NOTICE("BL2: Board is %s Rev.---\n", GET_BOARD_NAME(type)); 725 else { 726 NOTICE("BL2: Board is %s Rev.%d.%d\n", 727 GET_BOARD_NAME(type), 728 GET_BOARD_MAJOR(rev), GET_BOARD_MINOR(rev)); 729 } 730 731 #if RCAR_LSI != RCAR_AUTO 732 if (product != TARGET_PRODUCT) { 733 ERROR("BL2: IPL was been built for the %s.\n", TARGET_NAME); 734 ERROR("BL2: Please write the correct IPL to flash memory.\n"); 735 panic(); 736 } 737 #endif 738 rcar_avs_init(); 739 rcar_avs_setting(); 740 741 switch (boot_dev) { 742 case MODEMR_BOOT_DEV_HYPERFLASH160: 743 str = boot_hyper160; 744 break; 745 case MODEMR_BOOT_DEV_HYPERFLASH80: 746 str = boot_hyper80; 747 break; 748 case MODEMR_BOOT_DEV_QSPI_FLASH40: 749 str = boot_qspi40; 750 break; 751 case MODEMR_BOOT_DEV_QSPI_FLASH80: 752 str = boot_qspi80; 753 break; 754 case MODEMR_BOOT_DEV_EMMC_25X1: 755 str = boot_emmc25x1; 756 break; 757 case MODEMR_BOOT_DEV_EMMC_50X8: 758 str = boot_emmc50x8; 759 break; 760 default: 761 str = unknown; 762 break; 763 } 764 NOTICE("BL2: Boot device is %s\n", str); 765 766 rcar_avs_setting(); 767 reg = rcar_rom_get_lcs(&lcs); 768 if (reg) { 769 str = unknown; 770 goto lcm_state; 771 } 772 773 switch (lcs) { 774 case LCS_CM: 775 str = lcs_cm; 776 break; 777 case LCS_DM: 778 str = lcs_dm; 779 break; 780 case LCS_SD: 781 str = lcs_sd; 782 break; 783 case LCS_SE: 784 str = lcs_secure; 785 break; 786 case LCS_FA: 787 str = lcs_fa; 788 break; 789 default: 790 str = unknown; 791 break; 792 } 793 794 lcm_state: 795 NOTICE("BL2: LCM state is %s\n", str); 796 797 rcar_avs_end(); 798 is_ddr_backup_mode(); 799 800 bl2_tzram_layout.total_base = BL31_BASE; 801 bl2_tzram_layout.total_size = BL31_LIMIT - BL31_BASE; 802 803 if (boot_cpu == MODEMR_BOOT_CPU_CA57 || 804 boot_cpu == MODEMR_BOOT_CPU_CA53) { 805 ret = rcar_dram_init(); 806 if (ret) { 807 NOTICE("BL2: Failed to DRAM initialize (%d).\n", ret); 808 panic(); 809 } 810 rcar_qos_init(); 811 } 812 813 /* Set up FDT */ 814 ret = fdt_create_empty_tree(fdt, sizeof(fdt_blob)); 815 if (ret) { 816 NOTICE("BL2: Cannot allocate FDT for U-Boot (ret=%i)\n", ret); 817 panic(); 818 } 819 820 /* Add platform compatible string */ 821 bl2_populate_compatible_string(fdt); 822 823 /* Print DRAM layout */ 824 bl2_advertise_dram_size(product); 825 826 if (boot_dev == MODEMR_BOOT_DEV_EMMC_25X1 || 827 boot_dev == MODEMR_BOOT_DEV_EMMC_50X8) { 828 if (rcar_emmc_init() != EMMC_SUCCESS) { 829 NOTICE("BL2: Failed to eMMC driver initialize.\n"); 830 panic(); 831 } 832 rcar_emmc_memcard_power(EMMC_POWER_ON); 833 if (rcar_emmc_mount() != EMMC_SUCCESS) { 834 NOTICE("BL2: Failed to eMMC mount operation.\n"); 835 panic(); 836 } 837 } else { 838 rcar_rpc_init(); 839 rcar_dma_init(); 840 } 841 842 reg = mmio_read_32(RST_WDTRSTCR); 843 reg &= ~WDTRSTCR_RWDT_RSTMSK; 844 reg |= WDTRSTCR_PASSWORD; 845 mmio_write_32(RST_WDTRSTCR, reg); 846 847 mmio_write_32(CPG_CPGWPR, CPGWPR_PASSWORD); 848 mmio_write_32(CPG_CPGWPCR, CPGWPCR_PASSWORD); 849 850 reg = mmio_read_32(RCAR_PRR); 851 if ((reg & RCAR_CPU_MASK_CA57) == RCAR_CPU_HAVE_CA57) 852 mmio_write_32(CPG_CA57DBGRCR, 853 DBGCPUPREN | mmio_read_32(CPG_CA57DBGRCR)); 854 855 if ((reg & RCAR_CPU_MASK_CA53) == RCAR_CPU_HAVE_CA53) 856 mmio_write_32(CPG_CA53DBGRCR, 857 DBGCPUPREN | mmio_read_32(CPG_CA53DBGRCR)); 858 859 if (product_cut == RCAR_PRODUCT_H3_CUT10) { 860 reg = mmio_read_32(CPG_PLL2CR); 861 reg &= ~((uint32_t) 1 << 5); 862 mmio_write_32(CPG_PLL2CR, reg); 863 864 reg = mmio_read_32(CPG_PLL4CR); 865 reg &= ~((uint32_t) 1 << 5); 866 mmio_write_32(CPG_PLL4CR, reg); 867 868 reg = mmio_read_32(CPG_PLL0CR); 869 reg &= ~((uint32_t) 1 << 12); 870 mmio_write_32(CPG_PLL0CR, reg); 871 } 872 #if (RCAR_LOSSY_ENABLE == 1) 873 NOTICE("BL2: Lossy Decomp areas\n"); 874 875 fcnlnode = fdt_add_subnode(fdt, 0, "reserved-memory"); 876 if (fcnlnode < 0) { 877 NOTICE("BL2: Cannot create reserved mem node (ret=%i)\n", 878 fcnlnode); 879 panic(); 880 } 881 882 bl2_lossy_setting(0, LOSSY_ST_ADDR0, LOSSY_END_ADDR0, 883 LOSSY_FMT0, LOSSY_ENA_DIS0, fcnlnode); 884 bl2_lossy_setting(1, LOSSY_ST_ADDR1, LOSSY_END_ADDR1, 885 LOSSY_FMT1, LOSSY_ENA_DIS1, fcnlnode); 886 bl2_lossy_setting(2, LOSSY_ST_ADDR2, LOSSY_END_ADDR2, 887 LOSSY_FMT2, LOSSY_ENA_DIS2, fcnlnode); 888 #endif 889 890 fdt_pack(fdt); 891 NOTICE("BL2: FDT at %p\n", fdt); 892 893 if (boot_dev == MODEMR_BOOT_DEV_EMMC_25X1 || 894 boot_dev == MODEMR_BOOT_DEV_EMMC_50X8) 895 rcar_io_emmc_setup(); 896 else 897 rcar_io_setup(); 898 } 899 900 void bl2_el3_plat_arch_setup(void) 901 { 902 #if RCAR_BL2_DCACHE == 1 903 NOTICE("BL2: D-Cache enable\n"); 904 rcar_configure_mmu_el3(BL2_BASE, 905 BL2_END - BL2_BASE, 906 BL2_RO_BASE, BL2_RO_LIMIT 907 #if USE_COHERENT_MEM 908 , BL2_COHERENT_RAM_BASE, BL2_COHERENT_RAM_LIMIT 909 #endif 910 ); 911 #endif 912 } 913 914 void bl2_platform_setup(void) 915 { 916 917 } 918