fix(versal2): fix offsets for apu pcil

The current APU_PCIL offsets for disabling power down and wakeup
interrupts are incorrect. The cpuid passed to the register offset
macro is linear (0-8), but t

fix(versal2): fix offsets for apu pcil

The current APU_PCIL offsets for disabling power down and wakeup
interrupts are incorrect. The cpuid passed to the register offset
macro is linear (0-8), but the actual register offsets are
non-linear: 0, 1, 4, 5, 8, 9, 12, 13. As a result, the system
mistakenly disables wakeup and power down interrupts for other
cores. So convert the linear cpuid to a non-linear mapping and
update the APU_PCIL offset macros accordingly.

Change-Id: Ifd823f51d70d9d03fa87cc35ccc733a462eae36a
Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com>

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fix(versal2): initialize counter-timer frequency register

During initialization CNTFRQ_EL0 value is not getting updated and
its remaining 0. Because of that Linux is not able to get system
timer fre

fix(versal2): initialize counter-timer frequency register

During initialization CNTFRQ_EL0 value is not getting updated and
its remaining 0. Because of that Linux is not able to get system
timer frequency and cpu idle with cpu power down state is not
working. So update CNTFRQ_EL0 value during initialization.

Change-Id: I238f67521bbc338c433ce18f60df51efc4c5f387
Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com>

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fix(versal2): use common function to get system counter frequency

Currently, the IOU_SCNTR system counter frequency value is not read from
plat_get_syscnt_freq2(), and it returns the local cpu_freq,

fix(versal2): use common function to get system counter frequency

Currently, the IOU_SCNTR system counter frequency value is not read from
plat_get_syscnt_freq2(), and it returns the local cpu_freq, which is
incorrect. Use the common plat_get_syscnt_freq2() to read the IOU_SCNTR
frequency register and return the correct value.

Change-Id: I277dc6a2e4acd1acd3f048aaf242a3580d06e1c8
Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com>

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fix(versal2): align IOU_SCNTR base address macro name with other platforms

Renamed the IOU_SCNTR base address macro to match the naming
convention used in Versal and Versal NET. This ensures
consist

fix(versal2): align IOU_SCNTR base address macro name with other platforms

Renamed the IOU_SCNTR base address macro to match the naming
convention used in Versal and Versal NET. This ensures
consistency across platforms and enables the use of a common
function for getting and setting the system counter-timer
frequency.

Change-Id: I257a1086d77350858d63859b0fbe6e2b47deb9e5
Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com>

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Merge changes from topic "st_fixes" into integration

* changes:
fix(st-iwdg): remove num_irq
fix(st-drivers): remove useless field in fixed regul
fix(st-bsec): remove useless defines in BSEC3

Merge changes from topic "st_fixes" into integration

* changes:
fix(st-iwdg): remove num_irq
fix(st-drivers): remove useless field in fixed regul
fix(st-bsec): remove useless defines in BSEC3
fix(st-bsec): rename OTPSR field
fix(st-crypto): do not set IPRST if BUSY flag is present
fix(st-ddr): bad refresh update level toggle sequence
fix(st-ddr): remove TODO in STM32MP2 driver
fix(stm32mp2): correct typo in definition header

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feat(st-clock): add STM32MP21 and STM32MP23 RCC variants

Add specific configurations in clock driver for STM32MP21 and STM32MP23
SoCs.
All changes have been merged in stm32mp2_clk.c file using STM32

feat(st-clock): add STM32MP21 and STM32MP23 RCC variants

Add specific configurations in clock driver for STM32MP21 and STM32MP23
SoCs.
All changes have been merged in stm32mp2_clk.c file using STM32MP21,
STM32MP23 and STM32MP25 flags.
STM32MP23 will use the same RCC clock compatible of STM32MP25 SoC.

Change-Id: I6422cd0553067dc92f80da1ad8ec78cadf2432bb
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@foss.st.com>
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>

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refactor(stm32mp2): update display of reset reason

Update the check of reset reason management, update displayed string
aligned with reference manual (por_rstn/bor_rstn/Pin reset), add some
missing

refactor(stm32mp2): update display of reset reason

Update the check of reset reason management, update displayed string
aligned with reference manual (por_rstn/bor_rstn/Pin reset), add some
missing reset reason (C1RST) and reuse string to reduce the size of BL2.

Change-Id: I343a46d69bf0447cafed684eab1b2e812e08ab3a
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>

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feat(stm32mp21): add PWR registers file

Use the new file stm32mp21_pwr.h for STM32MP21 PWR peripheral registers
definition. Update platform code for backup domain write protection
disabling.

Change

feat(stm32mp21): add PWR registers file

Use the new file stm32mp21_pwr.h for STM32MP21 PWR peripheral registers
definition. Update platform code for backup domain write protection
disabling.

Change-Id: Iedfa764529bcd5119be8e94da7f7b84699e86086
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>

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feat(st): introduce SoC family compilation switch

add STM32MP1X and STM3MP2X compilation switch to replace
#if STM32MP21 || STM32MP23 || STM32MP25 for MP2 SoCs and
#if STM32MP13 || STM32MP15 for MP1

feat(st): introduce SoC family compilation switch

add STM32MP1X and STM3MP2X compilation switch to replace
#if STM32MP21 || STM32MP23 || STM32MP25 for MP2 SoCs and
#if STM32MP13 || STM32MP15 for MP1 SoCs.

This will avoid to forget to modify all these files when a new SoC is
introduced.

Change-Id: Ib984b22a19e08af5bc1b62fe2032f10240ec9122
Signed-off-by: Maxime Méré <maxime.mere@foss.st.com>

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docs(stm32mp2): introduce new STM32MP23 family

STM32MP23 is a derivative from STM32MP25. It comes in 3 different lines:
- STM32MP235: Dual Cortex-A35 + Cortex-M33 - 2x Ethernet - 2x CAN FD

docs(stm32mp2): introduce new STM32MP23 family

STM32MP23 is a derivative from STM32MP25. It comes in 3 different lines:
- STM32MP235: Dual Cortex-A35 + Cortex-M33 - 2x Ethernet - 2x CAN FD
H264 - 3D GPU - AI / NN - LVDS / DSI
- STM32MP233: Dual Cortex-A35 + Cortex-M33 - 2x Ethernet - 2x CAN FD
- STM32MP231: Single Cortex-A35 + Cortex-M33 - 1x Ethernet

Change-Id: Iaf3dd7e0c1eda055063361af3c98855b1272d4c6
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>

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docs(stm32mp2): introduce new STM32MP21 family

STM32MP21 is a derivative from STM32MP25. It comes in 3 different lines:
- STM32MP215: Single Cortex-A35 + Cortex-M33 - 2x Ethernet - 2x CAN FD

docs(stm32mp2): introduce new STM32MP21 family

STM32MP21 is a derivative from STM32MP25. It comes in 3 different lines:
- STM32MP215: Single Cortex-A35 + Cortex-M33 - 2x Ethernet - 2x CAN FD
CSI - LTDC
- STM32MP213: Single Cortex-A35 + Cortex-M33 - 2x Ethernet - 2x CAN FD
- STM32MP211: Single Cortex-A35 + Cortex-M33 - 1x Ethernet

Change-Id: Ie3db430bedd86c3b444bec647792be24b20a0cba
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>

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Merge changes from topic "xlnx_versal_custom_sip" into integration

* changes:
feat(versal): add hooks for mmap and early setup
refactor(zynqmp): refactor custom sip service

Merge "fix(qemu): fix variable may be used uninitialized error" into integration

Merge "feat(intel): update CPUECTLR_EL1 to boost ethernet performance" into integration

Merge "feat(mt8189): add IOMMU enable control in SiP service" into integration

Merge changes Ia29fd72f,I31b359ce,I1296aaff,I30e1ee7f,Ib4a3593e, ... into integration

* changes:
feat(mt8196): add SMMU SID stub implementation
feat(mt8196): add SLBC SiP handler
feat(mt8196):

Merge changes Ia29fd72f,I31b359ce,I1296aaff,I30e1ee7f,Ib4a3593e, ... into integration

* changes:
feat(mt8196): add SMMU SID stub implementation
feat(mt8196): add SLBC SiP handler
feat(mt8196): add CPU QoS stub implementation
refactor(mediatek): update EMI stub implementation
feat(mediatek): add APIs exposed to the static library
feat(mt8196): add MMinfra support
feat(mt8196): add UFS functions used by the static library

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Merge "feat(smcc): introduce a new vendor_el3 service for ACS SMC handler" into integration

fix(imx8ulp): fix variable may be used uninitialized error

When building with LTO, the compiler discovers that it is possible to
use the `volt` variable without writing to it. This happens when
upow

fix(imx8ulp): fix variable may be used uninitialized error

When building with LTO, the compiler discovers that it is possible to
use the `volt` variable without writing to it. This happens when
upower_pmic_i2c_read() returns error. Check its return value and panic()
if something went wrong so the error doesn't propagate silently.

Change-Id: I46d460892a2eb24596373ad7a5b07f730a0753de
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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fix(qemu): fix variable may be used uninitialized error

When building with LTO, the compiler discovers that it is possible to
use the `ns_buf_base` variable without writing to it. This happens on
er

fix(qemu): fix variable may be used uninitialized error

When building with LTO, the compiler discovers that it is possible to
use the `ns_buf_base` variable without writing to it. This happens on
error by dt_add_ns_buf_node(). Check its return value and panic() if
something went wrong so the error doesn't propagate silently.

Change-Id: Ia6aa83b0b9301b2db7bfa6ecd66396c37a57e816
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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Merge "chore(fvp): remove unused macro definition" into integration

Merge changes from topic "xlnx_versal_misra_fixes_series_3" into integration

* changes:
fix(xilinx): resolve misra rule 16.3 violations
fix(xilinx): resolve misra rule 2.5 violations
fix(xilin

Merge changes from topic "xlnx_versal_misra_fixes_series_3" into integration

* changes:
fix(xilinx): resolve misra rule 16.3 violations
fix(xilinx): resolve misra rule 2.5 violations
fix(xilinx): resolve misra rule 4.6 violations
fix(xilinx): resolve misra rule 12.2 violations
fix(xilinx): resolve misra rule 10.1 violations
fix(xilinx): resolve misra rule 8.13 violations
fix(xilinx): resolve misra rule 4.5 violations
fix(xilinx): resolve misra rule 16.4 violations

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fix(xilinx): resolve misra rule 16.3 violations

Fixed below MISRA violation:
- MISRA Violation: MISRA-C:2012 R.16.3:
- An unconditional break statement shall terminate every switch-clause.
- Fix:

fix(xilinx): resolve misra rule 16.3 violations

Fixed below MISRA violation:
- MISRA Violation: MISRA-C:2012 R.16.3:
- An unconditional break statement shall terminate every switch-clause.
- Fix:
- Added break statement in default clause to comply with MISRA.

Change-Id: Ie1ed38be671d5788096b2addba8e9a8fbcc4f2ec
Signed-off-by: Devanshi Chauhan Alpeshbhai <devanshi.chauhanalpeshbhai@amd.com>

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fix(xilinx): resolve misra rule 2.5 violations

Fixed below MISRA violation:
- MISRA Violation: MISRA-C:2012 R.2.5:
- A project should not contain unused macro declarations.
- Fix:
- Removed unus

fix(xilinx): resolve misra rule 2.5 violations

Fixed below MISRA violation:
- MISRA Violation: MISRA-C:2012 R.2.5:
- A project should not contain unused macro declarations.
- Fix:
- Removed unused macro declarations.

Change-Id: I2b9deda95d1a3927ab8b4e2c8a41bd85acb62be3
Signed-off-by: Devanshi Chauhan Alpeshbhai <devanshi.chauhanalpeshbhai@amd.com>

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fix(xilinx): resolve misra rule 4.6 violations

Fixed below MISRA violation:
- MISRA Violation: MISRA-C:2012 R.4.6:
- Typedefs that indicate size and signedness should be used in
place of the b

fix(xilinx): resolve misra rule 4.6 violations

Fixed below MISRA violation:
- MISRA Violation: MISRA-C:2012 R.4.6:
- Typedefs that indicate size and signedness should be used in
place of the basic numerical types.
- Fix:
- Used typedefs that indicate size and signedness in place of basic
numerical types and updated return type of function wherever needed.

Change-Id: Ifde2379ee3f9d5ab30ef695d99f59591af575aba
Signed-off-by: Devanshi Chauhan Alpeshbhai <devanshi.chauhanalpeshbhai@amd.com>

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fix(xilinx): resolve misra rule 12.2 violations

Fixed below MISRA violation:
- MISRA Violation: MISRA-C:2012 R.12.2:
- The right hand operand of a shift operator shall lie in the range
zero to

fix(xilinx): resolve misra rule 12.2 violations

Fixed below MISRA violation:
- MISRA Violation: MISRA-C:2012 R.12.2:
- The right hand operand of a shift operator shall lie in the range
zero to one less than the width in bits of the essential type of
the left hand operand.
- Fix:
- Type casted left operand to a larger width than shift.

Change-Id: I662ff57e52d1260e2f1a0de595f19a9143714892
Signed-off-by: Devanshi Chauhan Alpeshbhai <devanshi.chauhanalpeshbhai@amd.com>

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