| 600db4e3 | 01-Aug-2019 |
Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> |
intel: stratix10: Fix BL31 memory mapping
Previous config blocks ATF runtime service communications with SDM mailbox
Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change
intel: stratix10: Fix BL31 memory mapping
Previous config blocks ATF runtime service communications with SDM mailbox
Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: Ia857facd0bd0790056df94ed1e016bcf619a161e
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| b4694a86 | 30-Jul-2019 |
Remi Pommarel <repk@triplefau.lt> |
meson: gxl: Fix CPU hotplug
The CPU[1-3] are reset to initial/cold boot state (with their reset
address set to 0x0). In this state the cpus are waiting for another
one to set the reset address to bl
meson: gxl: Fix CPU hotplug
The CPU[1-3] are reset to initial/cold boot state (with their reset
address set to 0x0). In this state the cpus are waiting for another
one to set the reset address to bl31_warm_entrypoint and wake them up.
The CPU0 needs a bit of a workaround as changing the reset address
either through PSCI mailbox or the mmio mapped RVBAR (at 0xda834650)
does not seem to have any effect. Thus the workaround consists in
emulating the other CPUs' behavior with a WFE loop and manually jumping
to bl31_warm_entrypoint when woken back up by another one.
Change-Id: I11265620b5fd0619285e3993253a3f9a3ff6a7a4
Signed-off-by: Remi Pommarel <repk@triplefau.lt>
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| 43d4a291 | 04-Apr-2019 |
Remi Pommarel <repk@triplefau.lt> |
meson: gxl: Fix reset and power off
Before CPU enters standby state (wfi), the AP needs to signal the SCP
through PSCI mailbox.
Also at boot time the AP has to wait for the SCP to be ready before
s
meson: gxl: Fix reset and power off
Before CPU enters standby state (wfi), the AP needs to signal the SCP
through PSCI mailbox.
Also at boot time the AP has to wait for the SCP to be ready before
sending the first scpi commands or it can crash.
Change-Id: Iacc99f5bec745ad71922c5ea07ca5b87088133b6
Signed-off-by: Remi Pommarel <repk@triplefau.lt>
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| 402b3cf8 | 09-Jul-2019 |
Julius Werner <jwerner@chromium.org> |
Switch AARCH32/AARCH64 to __aarch64__
NOTE: AARCH32/AARCH64 macros are now deprecated in favor of __aarch64__.
All common C compilers pre-define the same macros to signal which
architecture the cod
Switch AARCH32/AARCH64 to __aarch64__
NOTE: AARCH32/AARCH64 macros are now deprecated in favor of __aarch64__.
All common C compilers pre-define the same macros to signal which
architecture the code is being compiled for: __arm__ for AArch32 (or
earlier versions) and __aarch64__ for AArch64. There's no need for TF-A
to define its own custom macros for this. In order to unify code with
the export headers (which use __aarch64__ to avoid another dependency),
let's deprecate the AARCH32 and AARCH64 macros and switch the code base
over to the pre-defined standard macro. (Since it is somewhat
unintuitive that __arm__ only means AArch32, let's standardize on only
using __aarch64__.)
Change-Id: Ic77de4b052297d77f38fc95f95f65a8ee70cf200
Signed-off-by: Julius Werner <jwerner@chromium.org>
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| d5dfdeb6 | 09-Jul-2019 |
Julius Werner <jwerner@chromium.org> |
Replace __ASSEMBLY__ with compiler-builtin __ASSEMBLER__
NOTE: __ASSEMBLY__ macro is now deprecated in favor of __ASSEMBLER__.
All common C compilers predefine a macro called __ASSEMBLER__ when
pre
Replace __ASSEMBLY__ with compiler-builtin __ASSEMBLER__
NOTE: __ASSEMBLY__ macro is now deprecated in favor of __ASSEMBLER__.
All common C compilers predefine a macro called __ASSEMBLER__ when
preprocessing a .S file. There is no reason for TF-A to define it's own
__ASSEMBLY__ macro for this purpose instead. To unify code with the
export headers (which use __ASSEMBLER__ to avoid one extra dependency),
let's deprecate __ASSEMBLY__ and switch the code base over to the
predefined standard.
Change-Id: Id7d0ec8cf330195da80499c68562b65cb5ab7417
Signed-off-by: Julius Werner <jwerner@chromium.org>
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| d8820789 | 01-Aug-2019 |
Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> |
intel: Platform common code refactor
Pull out common code from agilex and stratix10
Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: Iddc0a9e6eccb30823d7b15615d5
intel: Platform common code refactor
Pull out common code from agilex and stratix10
Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: Iddc0a9e6eccb30823d7b15615d5ce9c6bedb2abc
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| bd6ef775 | 31-Jul-2019 |
Alexei Fedorov <Alexei.Fedorov@arm.com> |
Merge "intel: agilex: Fix BL31 memory mapping" into integration |
| df42c311 | 31-Jul-2019 |
Alexei Fedorov <Alexei.Fedorov@arm.com> |
Merge "uniphier: fix typo and coding style" into integration |
| ce12d794 | 31-Jul-2019 |
Alexei Fedorov <Alexei.Fedorov@arm.com> |
Merge "uniphier: replace DIV_ROUND_UP() with div_round_up() from utils_def.h" into integration |
| 3ee48f40 | 31-Jul-2019 |
Alexei Fedorov <Alexei.Fedorov@arm.com> |
Merge "rockchip: px30: Use new bl31_params_parse functions" into integration |
| 4dd4bde4 | 26-Jul-2019 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
uniphier: fix typo and coding style
Fix the typo "warn" -> "warm".
Also fix the following checkpatch.pl warnings:
CHECK: Prefer using the BIT macro
CHECK: No space is necessary after a cast
uniphier: fix typo and coding style
Fix the typo "warn" -> "warm".
Also fix the following checkpatch.pl warnings:
CHECK: Prefer using the BIT macro
CHECK: No space is necessary after a cast
CHECK: Alignment should match open parenthesis
CHECK: Unnecessary parentheses around uniphier_io_policies[image_id].dev_handle
Change-Id: Ic11eea2668c4bf2d1e8f089e6338ba7b7156d80b
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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| f5de1aba | 26-Jul-2019 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
uniphier: replace DIV_ROUND_UP() with div_round_up() from utils_def.h
Use the helper in utils_def.h instead of the own macro.
Change-Id: I527f9e75914d60f66354e365006b960ba5e8cbae
Signed-off-by: Mas
uniphier: replace DIV_ROUND_UP() with div_round_up() from utils_def.h
Use the helper in utils_def.h instead of the own macro.
Change-Id: I527f9e75914d60f66354e365006b960ba5e8cbae
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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| 94eef290 | 30-Jul-2019 |
Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> |
intel: agilex: Fix BL31 memory mapping
Previous config blocks ATF runtime service communications with SDM mailbox
Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id
intel: agilex: Fix BL31 memory mapping
Previous config blocks ATF runtime service communications with SDM mailbox
Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: Ic97aa381d3ceb96395595ec192132859d626b8d1
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| f8aa5d7d | 29-Jul-2019 |
Ambroise Vincent <ambroise.vincent@arm.com> |
rockchip: px30: Use new bl31_params_parse functions
This change is needed for the platform to compile following the changes
made in commits cbdc72b559ab and 3e02c7436cf4.
Change-Id: I3468dd27f3b4f3
rockchip: px30: Use new bl31_params_parse functions
This change is needed for the platform to compile following the changes
made in commits cbdc72b559ab and 3e02c7436cf4.
Change-Id: I3468dd27f3b4f3095fb82f445d51cd8714311eb7
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
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| 66c1dafc | 26-Jul-2019 |
Soby Mathew <soby.mathew@arm.com> |
Merge "sgm775: Fix build fail for TSP support on sgm775" into integration |
| d27c880a | 19-Apr-2018 |
Hongbo Zhang <hongbo.zhang@linaro.org> |
plat/qemu: add gicv3 support for qemu
This patch adds gicv3 support for qemu, in order not to break any legacy
use case, gicv2 is still set by default, gicv3 can be selected by
compiling parameter Q
plat/qemu: add gicv3 support for qemu
This patch adds gicv3 support for qemu, in order not to break any legacy
use case, gicv2 is still set by default, gicv3 can be selected by
compiling parameter QEMU_USE_GIC_DRIVER=QEMU_GICV3.
Signed-off-by: Hongbo Zhang <hongbo.zhang@linaro.org>
Reviewed-by: Radoslaw Biernacki <radoslaw.biernacki@linaro.org>
Tested-by: Radoslaw Biernacki <radoslaw.biernacki@linaro.org>
Change-Id: Ic63f38abf16ed3c36aa60e80d50103cf05cf797b
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| 17953ff2 | 19-Apr-2018 |
Hongbo Zhang <hongbo.zhang@linaro.org> |
plat/qemu: move gicv2 codes to separate file
This file moves gicv2 codes to a new separate files, target is to add
gicv3 support later.
Signed-off-by: Hongbo Zhang <hongbo.zhang@linaro.org>
Reviewe
plat/qemu: move gicv2 codes to separate file
This file moves gicv2 codes to a new separate files, target is to add
gicv3 support later.
Signed-off-by: Hongbo Zhang <hongbo.zhang@linaro.org>
Reviewed-by: Radoslaw Biernacki <radoslaw.biernacki@linaro.org>
Tested-by: Radoslaw Biernacki <radoslaw.biernacki@linaro.org>
Change-Id: I30eb1fda5ea5c2b35d79360c52f46601cbca1bcc
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| ac1adfde | 26-Jul-2019 |
Soby Mathew <soby.mathew@arm.com> |
Merge "rockchip: px30: Fix build error" into integration |
| 41293407 | 26-Jul-2019 |
Soby Mathew <soby.mathew@arm.com> |
Merge changes from topic "advk-serror" into integration
* changes:
marvell/a3700: Prevent SError accessing PCIe link while it is down
marvell: Switch to xlat_tables_v2 |
| df7a906f | 26-Jul-2019 |
Soby Mathew <soby.mathew@arm.com> |
Merge changes from topic "jun-add-imx7-pico" into integration
* changes:
plat: imx7: Add PicoPi iMX7D basic support
plat: imx7: refactor code for reuse |
| 86126439 | 25-Jul-2019 |
Soby Mathew <soby.mathew@arm.com> |
Merge changes from topic "gby/cryptocell-multi-vers" into integration
* changes:
cryptocell: add product version awareness support
cryptocell: move Cryptocell specific API into driver |
| 8a079e88 | 25-Jul-2019 |
Ambroise Vincent <ambroise.vincent@arm.com> |
rockchip: px30: Fix build error
"result of '1 << 31' requires 33 bits to represent, but 'int' only has
32 bits [-Werror=shift-overflow=]"
This is treated as an error since commit 93c690eba8ca ("Ena
rockchip: px30: Fix build error
"result of '1 << 31' requires 33 bits to represent, but 'int' only has
32 bits [-Werror=shift-overflow=]"
This is treated as an error since commit 93c690eba8ca ("Enable
-Wshift-overflow=2 to check for undefined shift behavior")
Only the actual errors are being tackled by this patch. It is up to the
platform to choose whether there needs to be further modifications to
the code.
Change-Id: I70860ae5f2a34d7c684bd491b76da50aa04f778e
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
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| 425ace7d | 22-Jul-2019 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
sgm775: Fix build fail for TSP support on sgm775
Fixed the path to a source file specified in tsp makefile
Created a platform specific tsp makefile
Change-Id: I89565127c67eff510e48e21fd450af4c3088c
sgm775: Fix build fail for TSP support on sgm775
Fixed the path to a source file specified in tsp makefile
Created a platform specific tsp makefile
Change-Id: I89565127c67eff510e48e21fd450af4c3088c2d4
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
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| 36ec2bb0 | 14-May-2019 |
Gilad Ben-Yossef <gilad.benyossef@arm.com> |
cryptocell: move Cryptocell specific API into driver
Code using Cryptocell specific APIs was used as part of the
arm common board ROT support, instead of being abstracted
in Cryptocell specific driv
cryptocell: move Cryptocell specific API into driver
Code using Cryptocell specific APIs was used as part of the
arm common board ROT support, instead of being abstracted
in Cryptocell specific driver code, creating two problems:
- Any none arm board that uses Cryptocell wuld need to
copy and paste the same code.
- Inability to cleanly support multiple versions of Cryptocell
API and products.
Move over Cryptocell specific API calls into the Cryptocell
driver, creating abstraction API where needed.
Signed-off-by: Gilad Ben-Yossef <gilad.benyossef@arm.com>
Change-Id: I9e03ddce90fcc47cfdc747098bece86dbd11c58e
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| d38613df | 25-Jul-2019 |
Soby Mathew <soby.mathew@arm.com> |
Merge changes I0d17ba6c,I540741d2,I9e6475ad,Ifd769320,I12c04a85, ... into integration
* changes:
plat/mediatek/mt81*: Use new bl31_params_parse() helper
plat/rockchip: Use new bl31_params_parse_
Merge changes I0d17ba6c,I540741d2,I9e6475ad,Ifd769320,I12c04a85, ... into integration
* changes:
plat/mediatek/mt81*: Use new bl31_params_parse() helper
plat/rockchip: Use new bl31_params_parse_helper()
Add helper to parse BL31 parameters (both versions)
Factor out cross-BL API into export headers suitable for 3rd party code
Use explicit-width data types in AAPCS parameter structs
plat/rockchip: Switch to use new common BL aux parameter library
Introduce lightweight BL platform parameter library
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