1 /* 2 * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <stdint.h> 9 10 #include <platform_def.h> 11 12 #include <bl31/interrupt_mgmt.h> 13 #include <common/bl_common.h> 14 #include <common/debug.h> 15 #include <common/ep_info.h> 16 #include <drivers/amlogic/meson_console.h> 17 #include <lib/mmio.h> 18 #include <lib/xlat_tables/xlat_tables_v2.h> 19 20 /******************************************************************************* 21 * Platform memory map regions 22 ******************************************************************************/ 23 #define MAP_NSDRAM0 MAP_REGION_FLAT(GXBB_NSDRAM0_BASE, \ 24 GXBB_NSDRAM0_SIZE, \ 25 MT_MEMORY | MT_RW | MT_NS) 26 27 #define MAP_NSDRAM1 MAP_REGION_FLAT(GXBB_NSDRAM1_BASE, \ 28 GXBB_NSDRAM1_SIZE, \ 29 MT_MEMORY | MT_RW | MT_NS) 30 31 #define MAP_SEC_DEVICE0 MAP_REGION_FLAT(GXBB_SEC_DEVICE0_BASE, \ 32 GXBB_SEC_DEVICE0_SIZE, \ 33 MT_DEVICE | MT_RW | MT_SECURE) 34 35 #define MAP_SEC_DEVICE1 MAP_REGION_FLAT(GXBB_SEC_DEVICE1_BASE, \ 36 GXBB_SEC_DEVICE1_SIZE, \ 37 MT_DEVICE | MT_RW | MT_SECURE) 38 39 #define MAP_TZRAM MAP_REGION_FLAT(GXBB_TZRAM_BASE, \ 40 GXBB_TZRAM_SIZE, \ 41 MT_DEVICE | MT_RW | MT_SECURE) 42 43 #define MAP_SEC_DEVICE2 MAP_REGION_FLAT(GXBB_SEC_DEVICE2_BASE, \ 44 GXBB_SEC_DEVICE2_SIZE, \ 45 MT_DEVICE | MT_RW | MT_SECURE) 46 47 #define MAP_SEC_DEVICE3 MAP_REGION_FLAT(GXBB_SEC_DEVICE3_BASE, \ 48 GXBB_SEC_DEVICE3_SIZE, \ 49 MT_DEVICE | MT_RW | MT_SECURE) 50 51 static const mmap_region_t gxbb_mmap[] = { 52 MAP_NSDRAM0, 53 MAP_NSDRAM1, 54 MAP_SEC_DEVICE0, 55 MAP_SEC_DEVICE1, 56 MAP_TZRAM, 57 MAP_SEC_DEVICE2, 58 MAP_SEC_DEVICE3, 59 {0} 60 }; 61 62 /******************************************************************************* 63 * Per-image regions 64 ******************************************************************************/ 65 #define MAP_BL31 MAP_REGION_FLAT(BL31_BASE, \ 66 BL31_END - BL31_BASE, \ 67 MT_MEMORY | MT_RW | MT_SECURE) 68 69 #define MAP_BL_CODE MAP_REGION_FLAT(BL_CODE_BASE, \ 70 BL_CODE_END - BL_CODE_BASE, \ 71 MT_CODE | MT_SECURE) 72 73 #define MAP_BL_RO_DATA MAP_REGION_FLAT(BL_RO_DATA_BASE, \ 74 BL_RO_DATA_END - BL_RO_DATA_BASE, \ 75 MT_RO_DATA | MT_SECURE) 76 77 #define MAP_BL_COHERENT MAP_REGION_FLAT(BL_COHERENT_RAM_BASE, \ 78 BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE, \ 79 MT_DEVICE | MT_RW | MT_SECURE) 80 81 /******************************************************************************* 82 * Function that sets up the translation tables. 83 ******************************************************************************/ 84 void aml_setup_page_tables(void) 85 { 86 #if IMAGE_BL31 87 const mmap_region_t gxbb_bl_mmap[] = { 88 MAP_BL31, 89 MAP_BL_CODE, 90 MAP_BL_RO_DATA, 91 #if USE_COHERENT_MEM 92 MAP_BL_COHERENT, 93 #endif 94 {0} 95 }; 96 #endif 97 98 mmap_add(gxbb_bl_mmap); 99 100 mmap_add(gxbb_mmap); 101 102 init_xlat_tables(); 103 } 104 105 /******************************************************************************* 106 * Function that sets up the console 107 ******************************************************************************/ 108 static console_meson_t gxbb_console; 109 110 void aml_console_init(void) 111 { 112 int rc = console_meson_register(AML_UART0_AO_BASE, 113 AML_UART0_AO_CLK_IN_HZ, 114 AML_UART_BAUDRATE, 115 &gxbb_console); 116 if (rc == 0) { 117 /* 118 * The crash console doesn't use the multi console API, it uses 119 * the core console functions directly. It is safe to call panic 120 * and let it print debug information. 121 */ 122 panic(); 123 } 124 125 console_set_scope(&gxbb_console.console, 126 CONSOLE_FLAG_BOOT | CONSOLE_FLAG_RUNTIME); 127 } 128 129 /******************************************************************************* 130 * Function that returns the system counter frequency 131 ******************************************************************************/ 132 unsigned int plat_get_syscnt_freq2(void) 133 { 134 uint32_t val; 135 136 val = mmio_read_32(GXBB_SYS_CPU_CFG7); 137 val &= 0xFDFFFFFF; 138 mmio_write_32(GXBB_SYS_CPU_CFG7, val); 139 140 val = mmio_read_32(GXBB_AO_TIMESTAMP_CNTL); 141 val &= 0xFFFFFE00; 142 mmio_write_32(GXBB_AO_TIMESTAMP_CNTL, val); 143 144 return GXBB_OSC24M_CLK_IN_HZ; 145 } 146