1 /* 2 * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 9 #include <platform_def.h> 10 11 #include <common/bl_common.h> 12 #include <common/interrupt_props.h> 13 #include <drivers/arm/gicv2.h> 14 #include <lib/xlat_tables/xlat_mmu_helpers.h> 15 #include <plat/common/platform.h> 16 17 #include "aml_private.h" 18 19 /* 20 * Placeholder variables for copying the arguments that have been passed to 21 * BL31 from BL2. 22 */ 23 static entry_point_info_t bl33_image_ep_info; 24 25 /******************************************************************************* 26 * Return a pointer to the 'entry_point_info' structure of the next image for 27 * the security state specified. BL33 corresponds to the non-secure image type 28 * while BL32 corresponds to the secure image type. A NULL pointer is returned 29 * if the image does not exist. 30 ******************************************************************************/ 31 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) 32 { 33 entry_point_info_t *next_image_info; 34 35 assert(type == NON_SECURE); 36 37 next_image_info = &bl33_image_ep_info; 38 39 /* None of the images can have 0x0 as the entrypoint. */ 40 if (next_image_info->pc != 0U) { 41 return next_image_info; 42 } else { 43 return NULL; 44 } 45 } 46 47 /******************************************************************************* 48 * Perform any BL31 early platform setup. Here is an opportunity to copy 49 * parameters passed by the calling EL (S-EL1 in BL2 & S-EL3 in BL1) before 50 * they are lost (potentially). This needs to be done before the MMU is 51 * initialized so that the memory layout can be used while creating page 52 * tables. BL2 has flushed this information to memory, so we are guaranteed 53 * to pick up good data. 54 ******************************************************************************/ 55 struct gxbb_bl31_param { 56 param_header_t h; 57 image_info_t *bl31_image_info; 58 entry_point_info_t *bl32_ep_info; 59 image_info_t *bl32_image_info; 60 entry_point_info_t *bl33_ep_info; 61 image_info_t *bl33_image_info; 62 }; 63 64 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, 65 u_register_t arg2, u_register_t arg3) 66 { 67 struct gxbb_bl31_param *from_bl2; 68 69 /* Initialize the console to provide early debug support */ 70 aml_console_init(); 71 72 /* 73 * In debug builds, we pass a special value in 'arg1' to verify platform 74 * parameters from BL2 to BL31. In release builds it's not used. 75 */ 76 assert(arg1 == GXBB_BL31_PLAT_PARAM_VAL); 77 78 /* Check that params passed from BL2 are not NULL. */ 79 from_bl2 = (struct gxbb_bl31_param *) arg0; 80 81 /* Check params passed from BL2 are not NULL. */ 82 assert(from_bl2 != NULL); 83 assert(from_bl2->h.type == PARAM_BL31); 84 assert(from_bl2->h.version >= VERSION_1); 85 86 /* 87 * Copy BL33 entry point information. It is stored in Secure RAM, in 88 * BL2's address space. 89 */ 90 bl33_image_ep_info = *from_bl2->bl33_ep_info; 91 92 if (bl33_image_ep_info.pc == 0U) { 93 ERROR("BL31: BL33 entrypoint not obtained from BL2\n"); 94 panic(); 95 } 96 } 97 98 void bl31_plat_arch_setup(void) 99 { 100 aml_setup_page_tables(); 101 102 enable_mmu_el3(0); 103 } 104 105 /******************************************************************************* 106 * GICv2 driver setup information 107 ******************************************************************************/ 108 static const interrupt_prop_t gxbb_interrupt_props[] = { 109 INTR_PROP_DESC(IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, 110 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL), 111 INTR_PROP_DESC(IRQ_SEC_SGI_0, GIC_HIGHEST_SEC_PRIORITY, 112 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL), 113 INTR_PROP_DESC(IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, 114 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL), 115 INTR_PROP_DESC(IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, 116 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL), 117 INTR_PROP_DESC(IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY, 118 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL), 119 INTR_PROP_DESC(IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY, 120 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL), 121 INTR_PROP_DESC(IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY, 122 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL), 123 INTR_PROP_DESC(IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, 124 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL), 125 INTR_PROP_DESC(IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, 126 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL), 127 }; 128 129 static const gicv2_driver_data_t gxbb_gic_data = { 130 .gicd_base = AML_GICD_BASE, 131 .gicc_base = AML_GICC_BASE, 132 .interrupt_props = gxbb_interrupt_props, 133 .interrupt_props_num = ARRAY_SIZE(gxbb_interrupt_props), 134 }; 135 136 void bl31_platform_setup(void) 137 { 138 aml_mhu_secure_init(); 139 140 gicv2_driver_init(&gxbb_gic_data); 141 gicv2_distif_init(); 142 gicv2_pcpu_distif_init(); 143 gicv2_cpuif_enable(); 144 145 aml_thermal_unknown(); 146 } 147