1 /* 2 * Copyright (c) 2019, MediaTek Inc. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <arch_helpers.h> 9 #include <common/bl_common.h> 10 #include <common/desc_image_load.h> 11 #include <plat/common/common_def.h> 12 #include <drivers/console.h> 13 #include <common/debug.h> 14 #include <drivers/generic_delay_timer.h> 15 #include <mcucfg.h> 16 #include <mt_gic_v3.h> 17 #include <lib/mmio.h> 18 #include <mtk_plat_common.h> 19 #include <mtspmc.h> 20 #include <plat_debug.h> 21 #include <plat_params.h> 22 #include <plat_private.h> 23 #include <platform_def.h> 24 #include <scu.h> 25 #include <drivers/ti/uart/uart_16550.h> 26 27 static entry_point_info_t bl32_ep_info; 28 static entry_point_info_t bl33_ep_info; 29 30 static void platform_setup_cpu(void) 31 { 32 mmio_write_32((uintptr_t)&mt8183_mcucfg->mp0_rw_rsvd0, 0x00000001); 33 34 VERBOSE("addr of cci_adb400_dcm_config: 0x%x\n", 35 mmio_read_32((uintptr_t)&mt8183_mcucfg->cci_adb400_dcm_config)); 36 VERBOSE("addr of sync_dcm_config: 0x%x\n", 37 mmio_read_32((uintptr_t)&mt8183_mcucfg->sync_dcm_config)); 38 39 VERBOSE("mp0_spmc: 0x%x\n", 40 mmio_read_32((uintptr_t)&mt8183_mcucfg->mp0_cputop_spmc_ctl)); 41 VERBOSE("mp1_spmc: 0x%x\n", 42 mmio_read_32((uintptr_t)&mt8183_mcucfg->mp1_cputop_spmc_ctl)); 43 } 44 45 /******************************************************************************* 46 * Return a pointer to the 'entry_point_info' structure of the next image for 47 * the security state specified. BL33 corresponds to the non-secure image type 48 * while BL32 corresponds to the secure image type. A NULL pointer is returned 49 * if the image does not exist. 50 ******************************************************************************/ 51 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) 52 { 53 entry_point_info_t *next_image_info; 54 55 next_image_info = (type == NON_SECURE) ? &bl33_ep_info : &bl32_ep_info; 56 assert(next_image_info->h.type == PARAM_EP); 57 58 /* None of the images on this platform can have 0x0 as the entrypoint */ 59 if (next_image_info->pc) 60 return next_image_info; 61 else 62 return NULL; 63 } 64 65 /******************************************************************************* 66 * Perform any BL31 early platform setup. Here is an opportunity to copy 67 * parameters passed by the calling EL (S-EL1 in BL2 & S-EL3 in BL1) before they 68 * are lost (potentially). This needs to be done before the MMU is initialized 69 * so that the memory layout can be used while creating page tables. 70 * BL2 has flushed this information to memory, so we are guaranteed to pick up 71 * good data. 72 ******************************************************************************/ 73 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, 74 u_register_t arg2, u_register_t arg3) 75 { 76 static console_16550_t console; 77 78 params_early_setup(arg1); 79 80 console_16550_register(UART0_BASE, UART_CLOCK, UART_BAUDRATE, &console); 81 82 NOTICE("MT8183 bl31_setup\n"); 83 84 bl31_params_parse_helper(arg0, &bl32_ep_info, &bl33_ep_info); 85 } 86 87 88 /******************************************************************************* 89 * Perform any BL31 platform setup code 90 ******************************************************************************/ 91 void bl31_platform_setup(void) 92 { 93 platform_setup_cpu(); 94 generic_delay_timer_init(); 95 96 /* Initialize the GIC driver, CPU and distributor interfaces */ 97 mt_gic_driver_init(); 98 mt_gic_init(); 99 100 /* Init mcsi SF */ 101 plat_mtk_cci_init_sf(); 102 103 #if SPMC_MODE == 1 104 spmc_init(); 105 #endif 106 } 107 108 /******************************************************************************* 109 * Perform the very early platform specific architectural setup here. At the 110 * moment this is only intializes the mmu in a quick and dirty way. 111 ******************************************************************************/ 112 void bl31_plat_arch_setup(void) 113 { 114 plat_mtk_cci_init(); 115 plat_mtk_cci_enable(); 116 117 enable_scu(read_mpidr()); 118 119 plat_configure_mmu_el3(BL_CODE_BASE, 120 BL_COHERENT_RAM_END - BL_CODE_BASE, 121 BL_CODE_BASE, 122 BL_CODE_END, 123 BL_COHERENT_RAM_BASE, 124 BL_COHERENT_RAM_END); 125 } 126